Method for manufacturing ohmic contacts

FIELD: technological processes.

SUBSTANCE: invention relates to the formation technology of ohmic contacts to AlGaN/GaN heterostructures and can be used in the manufacture of semiconductor devices, in particular microwave field effect transistors. After the growth of a high-alloy semiconductor material (n+GaN), which is in contact with a two-dimensional electron gas of the AlGaN/GaN heterostructure, and stripping a dielectric mask, high-temperature annealing of the heterostructure with a high-alloyed semiconductor material at a temperature of 600–650 °C for 10–15 minutes in a nitrogen medium.

EFFECT: decrease in the resistivity of ohmic contacts.

1 cl, 1 dwg



Same patents:

FIELD: process engineering.

SUBSTANCE: invention relates to semiconductor technology, particularly, to production of semiconductor structures of contact-barrier metallisation of instrument. Contact-barrier metallisation is produced by series application of W (15% Ti) 0.17-0.19 mcm deep film at cross-field spraying of alloyed target at the rate of 2.5 E/s and Al (1.5% Si) 0.35-0.45 mcm deep film with subsequent thermal annealing at 450-480°C for 30 minutes in the medium of nitrogen.

EFFECT: decreased density of defects, perfected structure parameters, higher quality and yield.

1 tbl

FIELD: chemistry.

SUBSTANCE: invention relates to electroplating and can be used in producing semiconductors. The composition contains at least one copper source and at least one additive, obtained by reacting a polyatomic alcohol containing at least 5 hydroxyl functional groups with at least a first alkylene oxide and a second alkylene oxide from a mixture of a first alkylene oxide and a second alkylene oxide. The method includes contacting the metal coating composition with a substrate, generating current density in the substrate during a time period sufficient to deposit a metal layer on the substrate.

EFFECT: filling nanometre and micrometre openings without voids and seams.

15 cl, 1 tbl, 7 dwg, 8 ex

FIELD: physics, photography.

SUBSTANCE: invention relates to technology of manufacture of indium microcontacts in IR array photodetectors with photoelectric signal reading LSI circuits. A method of lowering of ohmic resistance of indium microcontacts using thermal annealing with semiconductor wafers with arrayes the LSI circuit of reading or photodiode arrays includes the forming of metal underlayer under indium, forming of protective photoconductivity mask with windows in places of microcontacts, deposition of indium layer, manufacture of indium contacts and annealing of structures in recovery atmosphere or vacuum at the temperature minimum 240°C within 30 minutes.

EFFECT: invention provides manufacture of indium microcontacts with low resistance and high homogeneity of their values within large arrays.

5 dwg

FIELD: chemistry.

SUBSTANCE: in a method of forming nanowires from a colloidal natural material, based on a self-organised formation of linearly ordered nanosized current-conducting structures with a strictly specified orientation for the connection of separate micro- and nanoelectronic elements and/or formation of nanocomponents of an electronic element base, formation of structures and/or elements is carried out in one process for not more than 3 minutes under an impact of an electric constant field only with an intensity not higher than 5×103 V/m, configuration of which directly specifies both the dimensions and forms and the orientation of the nanosized current-conducting carbon structures, which are stably preserved without the application of any protective layers on a substrate from any material, including the one, containing separate micro- and nanoelectronic elements for their connection and/or for the formation of nanocomponents of the electronic element base.

EFFECT: invention makes it possible to simplify the process of control of the form and location of the synthesised particles.

9 dwg

FIELD: electricity.

SUBSTANCE: proposed invention relates to electrical engineering, and namely to a method for obtaining a three-dimensionally structured semiconductor substrate for a field-emission cathode, and it can be used in different electronic devices: SHF, X-ray tubes, light sources, ion beam charge compensators, etc. Creation of a three-dimensionally structured semiconductor substrate, onto which an emitting film of field-emission cathodes is applied in the form of a microacicular quasi-regular cellular-spiking structure with an aspect ratio of at least 2 (the ratio of height of spikes to their height), allows improving emission performance of cathode, which is the technical result of the proposed invention. A semiconductor substrate for formation of the required microacicular structure on it is subject to photoelectrochemical etching in aqueous or nonaqueous electrolyte, thus changing modes of etching and illumination intensity. Besides, the invention proposes a structured semiconductor substrate for a field-emission cathode from crystalline silicon of p-type with conductivity of 1 to 8 Ohm*cm and a field-emission cathode itself with such substrate, which has increased emission characteristics.

EFFECT: obtaining a three-dimensionally structured semiconductor substrate for a field-emission cathode.

6 cl, 5 dwg

FIELD: electricity.

SUBSTANCE: method to create conducting paths includes application of solid layers of metallisation onto a non-conducting substrate, formation of a metallisation pattern, application of a protective barrier layer onto created paths and a layer for soldering and/or welding of parts elements onto conducting paths. Application of solid layers of metallisation is carried out by serial application of an adhesive layer onto a non-conducting path, a current-conducting layer and a metal layer that acts as a mask. To form the metallisation pattern, a mask is created by the method of laser evaporation on sections of the metal layer that acts as a mask, which are not occupied with current-conducting paths, then, using selective chemical etching, the conducting paths and the adhesive sublayer are removed in the opened sections, using selective chemical etching, the mask is removed, afterwards the protective barrier layer is applied, as well as the layer for soldering and/or welding.

EFFECT: invention makes it possible to increase quality of a metallisation pattern, to reduce number of operations and to increase process efficiency.

5 cl, 8 dwg, 6 tbl

FIELD: physics.

SUBSTANCE: in the method of making indium microcontacts, a wafer with arrays of large integrated circuits or photodiode arrays is protected by a photoresist film which is perforated at contact points, a layer of indium having a thickness which corresponds to the height of the microcontacts is sprayed, and a photoresist mask is deposited by photolithography. Microcontacts are formed by etching with ions of an inert gas until indium is fully sprays in spaces between the contacts; remains of the photoresist mask on tops of the microcontacts and the bottom protective film are removed in organic solvents or by etching in oxygen plasma.

EFFECT: technique for forming microcontacts by a separating interval at the base.

6 dwg

FIELD: physics.

SUBSTANCE: in the method of making a nanosized conducting element, the initial condensation phase is carried out in a medium of inert gases by magnetic sputtering of material from which a nanowire is formed onto a single-crystal chip for a predetermined time interval t, sufficient for detecting separate nucleation centres of the condensed material on steps. A substrate is placed such that the normal to its surface makes an angle with the direction of flow of the condensed atoms, a priori preventing formation of nucleation centres between steps, but sufficient for formation of nucleation centres of the condensed material on the steps. A microphotograph of the surface of the single-crystal chip is then made, from which density of nucleation centres of the condensed material on the steps and distance between the steps are determined, which are used to calculate the time of formation of the nanowire. The final phase of condensation of the material takes place during a time when there is no electrical conductivity between steps.

EFFECT: simple technique of forming solid-state one-dimensional nanostructures from different metals, semiconductors and alloys thereof, having environmental resistance and higher breakdown voltage.

2 cl, 4 dwg

FIELD: electrical engineering.

SUBSTANCE: method for formation of nanosized structures on semiconductors surface for usage in microelectronics includes formation of a monoatomic thickness buffer layer of gold with formation of an orderly 2D underlayer Si(111)-Si(111)-α√3×√3-Au, subsequent precipitation of 1-3 fullerene layers of onto the 2D underlayer Si(111)-Si(111)-α√3×√3-Au to form a fullerite-like lattice and precipitation of a 0.6 - 1 gold monolayer onto the prepared substrate under extra-high vacuum conditions, the substrate temperature being 20°C.

EFFECT: invention enables controllable formation of ultrathin gold nanofilms with the preset electric conductivity value on a semiconductor substrate surface.

2 cl, 3 dwg

FIELD: physics.

SUBSTANCE: in the method of making an ohmic contact to GaAs, a mask is formed on the surface of an n-GaAs plate, having a doped layer, in order to carry out a lift-off lithography process. To clean the surface in the windows of the mask, the n-GaAs plate is treated in aqueous H2SO4 or HCl solution and then washed in deionised water and dried. Further, via electron-beam and/or thermal evaporation in a vacuum at residual pressure lower than 5x10-6 torr, Ge and Cu are deposited with total thickness of 100-500 nm and weight content of germanium in the double-layer composition equal to 20-45%. Further, in a single vacuum cycle, the n-GaAs plate undergoes first thermal treatment at temperature T1=150-460°C in an atmosphere of atomic hydrogen with hydrogen atom flux density on the surface of the plate equal to 1013-1016 at.cm2 s-1. The n-GaAs plate is removed form the vacuum chamber, and after removing the mask, undergoes second thermal treatment in an atmosphere of an inert gas or in a vacuum at temperature T2=280-460°C for t=0.5-30 min.

EFFECT: lower value of reduced contact resistance.

2 cl, 1 dwg

FIELD: electronic engineering; integrated circuit manufacture on silicon.

SUBSTANCE: proposed method includes formation of active areas of devices on substrate; masking; opening of contact cuts for active areas; formation of metal deposition system that has amorphous metallide possessing negative mixing heat and incorporating components characterized in higher pressure of inherent vapors or higher sublimation heat than substrate material, and other components of metal deposition system. High stability of metal deposition system provides for manufacturing semiconductor device capable of operating at high temperatures approximately over 650 °C.

EFFECT: provision for preventing ingress of metal deposition system components into active area and escape of impurities from the latter.

6 cl, 2 dwg, 1 tbl

FIELD: micro- and nanoelectronics, micro- and nanomechanics where insulated conductors are used.

SUBSTANCE: proposed method for filling pockets in solid body with conducting material includes coating of solid-body surface, bottom, and side walls of mentioned pockets with first layer that functions as barrier material preventing diffusion of mentioned conducting material in solid body; application of second layer onto first one that functions as wetting layer for conducting material; application of third layer by way of physical or chemical deposition onto third one from gas phase that has in its composition mentioned conducting material; coating of third layer with fourth one that also incorporates conducting material; melting of conducting material by heating and profile leveling; material melting by heating is conducted after applying third layer and fourth layer is applied by any method of physical deposition from gas phase, chemical deposition from gas phase, chemical deposition from solution, electrochemical deposition, or chemical-mechanical deposition.

EFFECT: facilitated procedure, enlarged functional capabilities.

12 cl, 17 dwg

FIELD: ink jet printers.

SUBSTANCE: method includes precipitating resistive layer and conductive layer on insulated substrate, forming a resistive heating element, forming of insulating barrier layer above contour of said conductive layer, forming of gap in said barrier layer, forming of metallic layer being in electrical contact with said conductive layer contour through said gap, having geometry, which opens predetermined portion of said contour of conductive layer, making a layout from metallic layer from said contour of conductive layer through said gap in insulating barrier layer to adjacent portion of said insulated substrate, so that layout from metallic layer on said adjacent portion of said insulating substrate forms a relatively large and flat area, remote from said conductive layer contour, for forming displaced spring contact. After precipitation of resistive layer and conductive layer on insulating substrate, contour of conductive layer is formed first, having a recess, forming later said resistive heating element, and then contour of resistive layer is formed with overlapping of conductive layer contour for value, exceeding precision of combination during lithography process and error of dimensions during etching of resistive layer.

EFFECT: higher quality, higher reliability, higher efficiency.

2 cl, 10 dwg

FIELD: ink-jet printers and their printheads having small holes for programmable ejection of ink droplets.

SUBSTANCE: proposed method for producing printhead thin-film interconnection structure includes deposition of resistor layer and conductor layer onto insulated substrate, formation of patterns of layers deposited onto insulated structure to form resistive heating element, formation of insulating barrier layer onto pattern of mentioned conductor layer, formation of window in mentioned barrier layer, production of metal layer contacting mentioned conductor layer pattern through mentioned window whose geometry opens up predetermined area of mentioned conductor layer pattern, and metal layer pads on insulating barrier layer above heating layer; prior to arrangement of conductors from metal layer, insulating barrier layer is treated with etching solution for cleaning and recovering surface insulating barrier layer, and along with wiring of metal layer from mentioned conductor layer pattern through mentioned window in insulating barrier layer on adjacent area of mentioned insulated substrate metal layer wiring section is made in the form of pad on insulating barrier layer above heating element used as stabilizing evaporation surface. In this way insulating barrier layer is cleaned and its properties are recovered, metal layer wiring adhesion to insulating barrier layer, and especially adhesion of metal layer pad to insulating barrier layer above heating element, is enhanced.

EFFECT: enhanced quality and reliability of printhead.

3 cl, 11 dwg

FIELD: producing copper tracks on insulating substrates.

SUBSTANCE: negative image of track is projected onto copper halide solution layer in organic solvent of substrate with the result that concentric capillary flow occurs in layer which transfers solution to illuminated sections of substrate wherein copper halide tracks remain upon solvent evaporation. These tracks are reduced to copper ones in hydrogen current at temperature sufficient to conduct reducing reaction.

EFFECT: facilitated procedure, reduced cost and copper consumption, improved environmental friendliness due to elimination of wastes.

1 cl, 3 dwg

FIELD: microelectronics; complementary metal-oxide-semiconductor transistors.

SUBSTANCE: proposed method for producing CMOS transistor gate regions includes formation of regions of second polarity of conductivity, insulator, and gate silicon dioxide in substrate of first polarity of conductivity, deposition of polycrystalline silicon layer, its doping, formation of gate regions of p- and n-channel transistors, thermal cleaning in trichloroethylene and oxygen, deposition of separating silicon dioxide, modification, formation of drain and source regions of both polarities of conductivity, thermal cleaning in trichloroethylene and oxygen, deposition of pyrolytic insulating silicon dioxide, its modification by thermal firing in trichloroethylene and oxygen, opening of contact windows, metal deposition, and process operations (removal of natural silicon dioxide, formation of gate silicon dioxide, formation of polycrystalline silicon layer) conducted within single vacuum cycle of one reactor, whereupon polycrystalline silicon layer is doped.

EFFECT: improved and regulated electrophysical properties of gate silicon dioxide enabling enhancement of threshold voltage reproducibility and yield.

4 cl, 3 dwg

FIELD: ohmic contacts for microelectronic devices such as microwave field-effect transistors.

SUBSTANCE: proposed method includes production of vacuum in vacuum chamber, sequential electron-beam evaporation of Ti, Al, Ni, and Au in vacuum chamber onto section of AlGaN layer surface, and high-temperature annealing; prior to Ti, Al, Ni, Au evaporation Ti is sprayed in vacuum chamber to form 2-3 Ti monolayer on surfaces of elements disposed within vacuum chamber; Ti, Al, Ni, Au are evaporated onto section of AlGaN layer surface at vacuum of 1 x 10-7 to 1 x 10-8 mm Hg.

EFFECT: reduced contact resistance of ohmic contacts due to reduced amount of residual oxygen and water vapors in vacuum chamber.

1 cl

FIELD: ohmic contacts for microelectronic devices such as microwave field-effect transistors.

SUBSTANCE: proposed method includes sequential evaporation of Ti, Al, Ni, Au onto section of AlGsN surface layer and fast thermal annealing of semiconductor heterostructure; fast thermal annealing is conducted using contact method and graphite resistive heater, semiconductor heterostructure being disposed on heater surface. In the course of annealing temperature of GaN/AlGsN semiconductor heterostructure is controlled to ensure reproducibility of its parameters.

EFFECT: facilitated procedure, reduced time requirement, enhanced quality of heterostructure.

1 cl

FIELD: light devices production.

SUBSTANCE: method of quantum wells mixing within semiconductor device implies: a) formation of layer structure with quantum wells including doped upper layer; b) formation of etch preventing layer over mentioned upper layer; c) formation of temporary layer over mentioned etch preventing layer, and mentioned etch preventing layer has significantly lower etch rate than mentioned temporary layer on condition that etching requirements are preliminary specified; d) process of quantum wells mixing upon device structure making significant violation of at least a part of consumed layer; e) removal of temporary layer from at least device contact area by etching selective relative to etch preventing layer to uncover mentioned etch preventing layer within contact area; and f) formation of contact over layer structure with quantum wells directly on the surfaced uncovered after execution of stage e) at least within mentioned contact area.

EFFECT: improvement of device contact resistance.

15 cl, 10 dwg

FIELD: electronics.

SUBSTANCE: invention pertains to electronics, particularly to microelectronics, and can be used when making silicon semiconductor devices. The method of making a system for metal plating silicon semiconductor devices involves forming a dielectric film based on silicon dioxide on a silicon substrate with active regions, formation in this film of contact windows to active elements of the substrate, deposition of a film of molten aluminium with a given thickness, formation of the metal pattern and subsequent thermal treatment for obtaining ohmic contacts. Thermal treatment is carried out in a hydrogen atmosphere with addition of 0.5-3.0 vol.% water or 0.25-1.5 vol.% oxygen.

EFFECT: higher quality of the system of metal plating due to reduced defectiveness and improved electrical characteristics.

1 tbl