Method of increase of threshold barrier voltage of gan transistor
SUBSTANCE: method of increasing the threshold barrier voltage of a transistor based on gallium nitride (GaN), which includes creating gate p-GaN mesa on the surface of the silicon wafer with epitaxial heterostructure of GaN/AlGaN/GaN type, inter-instrument mesa-isolation, forming ohmic contacts to the areas of the transistor drain and source, forming a two-layer resistive mask by lithographic methods, cleaning of the surface of the semiconductor, deposition of thin films of gate metallization, removing of the plate from the vacuum chamber of the evaporator, removal of the resistive mask, prior to the evaporation of thin films of gate metallization the plate is subjected to treatment in an atmosphere of atomic hydrogen for t=10-60 seconds at a temperature of t=20-150°C and flow density of hydrogen atoms on the surface of the plate, equal to 1013-1016 at. cm-2 c-1.
EFFECT: increase in the threshold barrier voltage of the GaN transistor when applying barrier metal films to the p-GaN gate area with a high electronic work function.
5 cl, 3 dwg
SUBSTANCE: method for manufacture of powerful SHF transistor includes application of a solder layer to the flange, shaping of pedestal, application of a sublayer fixing the transistor crystal to the pedestal, formation of p-type conductivity oriented at the plane (111) at the base substrate of single-crystalline silicon and auxiliary epitaxial layers, application of the basic layer and buffer layer for growing of epitaxial structure of a semiconductor device based on wide-gap III-nitrides, application of heat conductive layer of CVD polycrystalline diamond to the basic layer, removal of the basic substrate with auxiliary epitaxial layers up to the basic layer, growing of heteroepitaxial structure based on wide-gap III-nitrides on the basic layer and formation of the source, gate and drain. The heat conductive layer of CVD polycrystalline diamond is used as a pedestal; nickel is implanted to its surficial region and annealed. Before formation of the source, gate and drain an additional layer of insulating polycrystalline diamond and additional layers of hafnium dioxide and aluminium oxide are deposited on top of the transistor crystal; the total thickness of the above layers is 1.0-4.0 nm.
EFFECT: invention allows increased heat removal from the active part of SHF-transistor and minimisation of gate current losses.
6 cl, 4 dwg
SUBSTANCE: invention relates to semiconductor technology. Proposed method comprises removal of photoresist from at least one surface of conducting layer with the help of the mix of chemical including first material of self-optimising monolayer and chemical to remove said photoresist. Thus self-optimising monolayer is deposited on at least one surface of said conducting ply. Semiconductor material is deposited on self-optimising monolayer applied on conducting layer without ozone cleaning of conducting layer.
EFFECT: simplified method.
15 cl, 4 dwg
SUBSTANCE: semiconductor device comprises a thinned substrate of single-crystal silicon of p-type conductivity, oriented according to the plane (111), with a buffer layer from AlN on it, above which there is a heat conducting substrate in the form of a deposited layer of polycrystalline diamond with thickness equal to at least 0.1 mm, on the other side of the substrate there is an epitaxial structure of the semiconducting device on the basis of wide-zone III-nitrides, a source from AlGaN, a gate, a drain from AlGaN, ohmic contacts to the source and drain, a solder in the form of a layer including AuSn, a copper pedestal and a flange. At the same time between the source, gate and drain there is a layer of an insulating polycrystalline diamond.
EFFECT: higher reliability of a semiconducting device and increased service life, makes it possible to simplify manufacturing of a device with high value of heat release from an active part.
3 cl, 7 dwg
FIELD: electrical engineering.
SUBSTANCE: method for manufacture of a powerful UHF transistor includes formation of the topology of at least one transistor crystal on the semiconductor substrate face side, formation of the transistor electrodes, formation of at least one protective dielectric layer along the whole of the transistor crystal topology by way of plasma chemical application, the layer total length being 0.15-0.25 mcm, formation of the transistor crystal size by way of lithography and chemical etching processes. Prior to formation of the transistor crystal size, within the choke electrode area one performs local plasma chemical etching of the protective dielectric layer to a depth equal to the layer thickness; immediately after that one performs formation of protectively passivating dielectric layers of silicon nitride and diozide with thickness equal to 0.045-0.050 mm; plasma chemical application of the latter layers and the protective dielectric layer is performed in the same technological modes with plasma power equal to 300-350 W, during 30-35 sec and at a temperature of 150-250°C; during formation of the transistor crystal size ne performs chemical etching of the protectively passivating dielectric layers and the protective dielectric layer within the same technological cycle.
EFFECT: increased power output and augmentation ratio or powerful transistors with their long-term stability preservation.
4 cl, 1 dwg, 1 tbl
SUBSTANCE: method for UHF high-power transistors manufacturing includes formation of transistor topology semiconductor substratum on the face side by electronic lithography and photolithography methods, metals spraying on, dielectrics application and etching, cathodic electrodeposition of gold, formation of preset size grooves on the face side outside the transistor topology, substrate thinning, formation of grounding through holes for the transistors source electrodes, formation of a common integrated heat sink, formation of a integrated heat sink for each transistor crystal, semiconductor substrate division into transistor crystals; one uses a semiconductor substrate with the preset structure of active layers having two stop layers with the preset distance between them, the stop layers ensuring minimum thermal resistance; the semiconductor substrate reverse side thinning is performed down to the stop-layer located close to such side; grounding through holes are formed immediately on the source electrodes with the common integrated heat sink thickness is set by the type of the transistor crystal subsequent mounting.
EFFECT: enhanced output capacity through reduction of thermal resistance, parasitic of the electric resistance in series and source electrodes grounding inductance; increased yield ratio, repeatability and functionalities extension.
4 cl, 1 dwg, 1 tbl
SUBSTANCE: field transistor manufacturing method includes creation of source and drain contacts, active area identification, application of a dielectric film onto the contact layer surface, formation of a submicron chink in the dielectric film for the needs of subsequent operations of contact layer etching and application of gate metal through the resistance mask; immediately after the dielectric film application one performs lithography for opening windows in the dielectric at least one edge whereof coincides with the Schottky gates location in the transistor being manufactured; after the window opening a second dielectric layer is applied onto the whole of the surface with the resistance removed; then, by way of repeated lithography, windows in the resistance are created, surrounding the chinks formed between the two dielectrics; selective etching of the contact layer is performed with metal films sprayed on to form the gates.
EFFECT: simplification of formation of under-gate chinks sized below 100 nm in the dielectric.
SUBSTANCE: manufacturing method of microwave transistor with control electrode of T-shaped configuration of submicron length involves formation on the front side of semi-insulating semi-conductor plate with active layer of the specified structure of a pair of electrodes of transistor, which form ohmic contacts by means of lithographic, etching method and method of sputtering of metal or system of metals, formation of transistor channel by means of electronic lithography and etching, application of masking dielectric layer, formation in masking dielectric layer of submicron slot by means of electronic lithography and etching; at that, submicron slot is formed with variable cross section decreasing as to height from wide upper part adjacent to the head of the above control electrode to narrow lower part adjacent to transistor channel, formation of topology of the above control electrode by means of electronic lithography method, formation of the above control electrode in submicron slot by means of sputtering of metal or system of metals; at that, configuration of its base repeats configuration of submicron slot. During formation of submicron slot with variable cross section in masking dielectric layer, which decreases throughout its height, by means of electronic lithography and etching, the latter of masking dielectric layer is performed in one common production process in high-frequency plasma of hexafluoride of sulphur, oxygen and helium and discharge power of 8-10 W.
EFFECT: increasing output power and amplification factor, increasing reproducibility of the above output parametres and therefore yield ratio, simplifying and decreasing labour input for manufacturing process.
2 cl, 1 dwg, 1 tbl, 5 ex
FIELD: electronic engineering; high-power microwave transistors and small-scale integrated circuits built around them.
SUBSTANCE: proposed method for producing high-power microwave transistors includes formation of transistor-layout semiconductor wafer on face side, evaporation of metals, application and etching of insulators, electrolytic deposition of gold, formation of grooves on wafer face side beyond transistor layout for specifying transistor chip dimensions, thinning of semiconductor wafer, formation of grooves on wafer underside just under those on face side, formation of through holes for grounding transistor leads, formation of integrated heat sinks for transistor chips around integrated heat sink followed by dividing semiconductor wafer into transistor chips by chemical etching using integrated heat sinks of transistor chips as mask.
EFFECT: enhanced power output due to reduced thermal resistance, enhanced yield, and facilitated manufacture.
2 cl, 1 dwg, 1 tbl
FIELD: technologies for making transistors.
SUBSTANCE: method includes following stages: precipitation of electric-conductive material on substrate of semiconductor material, forming of shape of first parallel band electrodes with step, determined by appropriate construction rules, while areas of substrate in form of stripes between first electrodes are left open, precipitation of barrier layer, covering first electrodes down to substrate, alloying of substrate in open areas, precipitation of electric-conductive material above alloyed areas of substrate with forming of second parallel band electrodes, removal of barrier layer, near which vertical channels are left, passing downwards to non-alloyed areas of substrate between first and second electrodes, alloying of substrate in open areas of lower portion of channels, filling channels with barrier material, removal of first electrodes, during which gaps between second electrodes are left and substrate areas are opened between them, alloying of open areas of substrate in gaps, from which first electrodes were removed, removal of electric-conductive material in said gaps for restoration of first electrodes and thus making an electrode layer, containing first and second parallel band electrodes of practically even width, which are adjacent to alloyed substrate and separated from each other only by thin layer of barrier material, while, dependent on alloying admixtures, used during alloying stages, first electrodes form source or discharge electrodes, and second electrodes - respectively discharge or source electrodes of transistor structures, precipitation of insulating barrier layer above electrodes and separating barrier layers. Precipitation of electric-conductive material above barrier layer and forming in said electric-conductive material of shape of parallel band valve electrodes, directed transversely to source and discharge electrodes, thus receiving structures matrix for field transistors with very short channel length and arbitrarily large width of channel, determined by width of valve electrode.
EFFECT: ultra-short channel length of produced transistors.
11 cl, 17 dwg
FIELD: process engineering.
SUBSTANCE: invention relates to semiconductor technology, particularly, to production of semiconductor structures of contact-barrier metallisation of instrument. Contact-barrier metallisation is produced by series application of W (15% Ti) 0.17-0.19 mcm deep film at cross-field spraying of alloyed target at the rate of 2.5 E/s and Al (1.5% Si) 0.35-0.45 mcm deep film with subsequent thermal annealing at 450-480°C for 30 minutes in the medium of nitrogen.
EFFECT: decreased density of defects, perfected structure parameters, higher quality and yield.
SUBSTANCE: in the method of making a nanosized conducting element, the initial condensation phase is carried out in a medium of inert gases by magnetic sputtering of material from which a nanowire is formed onto a single-crystal chip for a predetermined time interval t, sufficient for detecting separate nucleation centres of the condensed material on steps. A substrate is placed such that the normal to its surface makes an angle with the direction of flow of the condensed atoms, a priori preventing formation of nucleation centres between steps, but sufficient for formation of nucleation centres of the condensed material on the steps. A microphotograph of the surface of the single-crystal chip is then made, from which density of nucleation centres of the condensed material on the steps and distance between the steps are determined, which are used to calculate the time of formation of the nanowire. The final phase of condensation of the material takes place during a time when there is no electrical conductivity between steps.
EFFECT: simple technique of forming solid-state one-dimensional nanostructures from different metals, semiconductors and alloys thereof, having environmental resistance and higher breakdown voltage.
2 cl, 4 dwg
SUBSTANCE: method of forming contact drawing from nickel on silicon wafers involves formation of a dielectric film with windows, chemical deposition of nickel in said windows and formation of a nickel silicide interlayer from the gas phase during thermal decomposition of nickel tetracarbonyl vapour at temperature 200-300°C, pressure in the system of (1-10)-10-1 mm Hg and rate of supplying nickel tetracarbonyl vapour equal to 0.5-2 ml/min per dm2 of the covering surface. The nickel layer is then removed up to the nickel silicide layer through chemical etching and nickel is deposited via chemical deposition onto the nickel silicide interlayer in the window of the dielectric film.
EFFECT: invention enables formation of a transparent contact for an electroconductive layer based on nickel with low ohmic resistance, independent of the type of conductivity and degree of doping of the silicon surface.
1 ex, 1 tbl
FIELD: physics; conductors.
SUBSTANCE: invention relates to semiconductor micro- and nanoelectronics and can be used in making integrated circuits, in making electrodes in transistors and capacitor plates, in making contacts and conduction regions on a silicon surface, as conducting, thermostable and barrier layers in metallisation systems. The method of making a thin-film metal structure of tungsten on silicon involves making a nanometer sublayer of an adhesion promoter on a silicon substrate and subsequent deposition of a thin film of tungsten through gas-phase chemical deposition through reduction of tungsten hexafluoride with hydrogen at low pressure. The adhesion promoter used is tungsten silicide W5Si3.
EFFECT: invention improves quality of the obtained metal structure of tungsten on silicon with simplification of the process at the same time.
3 cl, 1 dwg, 3 ex
FIELD: light devices production.
SUBSTANCE: method of quantum wells mixing within semiconductor device implies: a) formation of layer structure with quantum wells including doped upper layer; b) formation of etch preventing layer over mentioned upper layer; c) formation of temporary layer over mentioned etch preventing layer, and mentioned etch preventing layer has significantly lower etch rate than mentioned temporary layer on condition that etching requirements are preliminary specified; d) process of quantum wells mixing upon device structure making significant violation of at least a part of consumed layer; e) removal of temporary layer from at least device contact area by etching selective relative to etch preventing layer to uncover mentioned etch preventing layer within contact area; and f) formation of contact over layer structure with quantum wells directly on the surfaced uncovered after execution of stage e) at least within mentioned contact area.
EFFECT: improvement of device contact resistance.
15 cl, 10 dwg
SUBSTANCE: in manufacturing method of multi-level copper metallisation of VLSIC, which involves application operations of metal and dielectric layers, photolithography and selective etching of those layers, chemical mechanical polishing of dielectric layers, to plate of silicium, which is coated with dielectric material with vertical conductors of underlying structure, which protrude on its surface, there applied is multi-layered conducting film consisting of adhesive barrier, etched and auxiliary layers; grooves are formed in auxiliary layer before etched layers by electrochemical method; copper horizontal conductors are grown inside grooves in open sections of etched layer till grooves are fully filled; the second auxiliary layer is applied to surface of plate, and in that layer holes are made to the surface of horizontal copper conductors; vertical copper conductors are grown by electrochemical method in open sections of horizontal conductors till holes for vertical conductors are fully filled; then, auxiliary layers are removed; conducting layers between horizontal copper conductors are removed; dielectric layers are applied to surface of the plate by smoothing and filling methods, and then dielectric material layers are removed above vertical conductors by means of chemical and mechanical polishing method.
EFFECT: improving quality of copper conductors.
16 cl, 11 dwg, 1 tbl
SUBSTANCE: method involves notching in bulk of a silicon wafer and silicone removing from the wafer back to uncover notch bottoms. Notching enables silicone pattern formation to represent hollow cell walls that is followed with wall-through oxidation to form a dielectric SiO2 conduit system. Silicon removing from the back of the wafer can be conducted by the deep plasma etch process.
EFFECT: high strength of the insulating element which can be used for manufacturing various MEMS devices in bulk of a standard silicon wafer.
2 cl, 13 dwg
SUBSTANCE: invention is attributed to microelectronics and can be used in production of semiconductor devices and integral circuits. Essence of invention: in the method of attaching silicon chip to chip holder, chip seating surface is successively sputtered with two titan-germanium metals, and chip to chip holder soldering is carried out at temperature of 280-300°C.
EFFECT: improvement of chip with chip-holder contact reliability and stability of attachment process.
FIELD: micro- and nanoelectronics, micro- and nanomechanics where insulated conductors are used.
SUBSTANCE: proposed method for filling pockets in solid body with conducting material includes coating of solid-body surface, bottom, and side walls of mentioned pockets with first layer that functions as barrier material preventing diffusion of mentioned conducting material in solid body; application of second layer onto first one that functions as wetting layer for conducting material; application of third layer by way of physical or chemical deposition onto third one from gas phase that has in its composition mentioned conducting material; coating of third layer with fourth one that also incorporates conducting material; melting of conducting material by heating and profile leveling; material melting by heating is conducted after applying third layer and fourth layer is applied by any method of physical deposition from gas phase, chemical deposition from gas phase, chemical deposition from solution, electrochemical deposition, or chemical-mechanical deposition.
EFFECT: facilitated procedure, enlarged functional capabilities.
12 cl, 17 dwg