Method of making semiconductor device

FIELD: instrument making.

SUBSTANCE: invention relates to semiconductor devices production process, in particular to technology of making contacts with lowered resistance. In method of semiconductor device making contacts are formed on basis of platinum. For this film of platinum with thickness of 35-45 nm is applied by electron-beam evaporation on silicon substrate, heated prior to 350 °C, at rate of deposition of 5 nm/min. Then heat treated in three stages: 1 step is carried out at temperature of 200 °C for 15 minutes, 2 step is carried out at temperature of 300 °C for 10 minutes and 3 stage is at 550 °C for 15 min in forming gas, with mixture of gases N2:H2=9:1.

EFFECT: proposed method of semiconductor device making provides reduced contact resistance, high technological effectiveness, improved parameters of devices, high quality and yield.

1 cl, 1 tbl

 



 

Same patents:

FIELD: electricity.

SUBSTANCE: in manufacturing method of multi-level copper metallisation of VLSIC, which involves application operations of metal and dielectric layers, photolithography and selective etching of those layers, chemical mechanical polishing of dielectric layers, to plate of silicium, which is coated with dielectric material with vertical conductors of underlying structure, which protrude on its surface, there applied is multi-layered conducting film consisting of adhesive barrier, etched and auxiliary layers; grooves are formed in auxiliary layer before etched layers by electrochemical method; copper horizontal conductors are grown inside grooves in open sections of etched layer till grooves are fully filled; the second auxiliary layer is applied to surface of plate, and in that layer holes are made to the surface of horizontal copper conductors; vertical copper conductors are grown by electrochemical method in open sections of horizontal conductors till holes for vertical conductors are fully filled; then, auxiliary layers are removed; conducting layers between horizontal copper conductors are removed; dielectric layers are applied to surface of the plate by smoothing and filling methods, and then dielectric material layers are removed above vertical conductors by means of chemical and mechanical polishing method.

EFFECT: improving quality of copper conductors.

16 cl, 11 dwg, 1 tbl

FIELD: electricity.

SUBSTANCE: method involves notching in bulk of a silicon wafer and silicone removing from the wafer back to uncover notch bottoms. Notching enables silicone pattern formation to represent hollow cell walls that is followed with wall-through oxidation to form a dielectric SiO2 conduit system. Silicon removing from the back of the wafer can be conducted by the deep plasma etch process.

EFFECT: high strength of the insulating element which can be used for manufacturing various MEMS devices in bulk of a standard silicon wafer.

2 cl, 13 dwg

FIELD: electronics.

SUBSTANCE: invention is attributed to microelectronics and can be used in production of semiconductor devices and integral circuits. Essence of invention: in the method of attaching silicon chip to chip holder, chip seating surface is successively sputtered with two titan-germanium metals, and chip to chip holder soldering is carried out at temperature of 280-300°C.

EFFECT: improvement of chip with chip-holder contact reliability and stability of attachment process.

FIELD: micro- and nanoelectronics, micro- and nanomechanics where insulated conductors are used.

SUBSTANCE: proposed method for filling pockets in solid body with conducting material includes coating of solid-body surface, bottom, and side walls of mentioned pockets with first layer that functions as barrier material preventing diffusion of mentioned conducting material in solid body; application of second layer onto first one that functions as wetting layer for conducting material; application of third layer by way of physical or chemical deposition onto third one from gas phase that has in its composition mentioned conducting material; coating of third layer with fourth one that also incorporates conducting material; melting of conducting material by heating and profile leveling; material melting by heating is conducted after applying third layer and fourth layer is applied by any method of physical deposition from gas phase, chemical deposition from gas phase, chemical deposition from solution, electrochemical deposition, or chemical-mechanical deposition.

EFFECT: facilitated procedure, enlarged functional capabilities.

12 cl, 17 dwg

The invention relates to semiconductor electronics and can be used in the manufacture of solid-state devices and electrodes

The invention relates to the field of thin-film technology and is intended for use in microelectronics and integrated optics

The invention relates to a MOS semiconductor memory device, particularly to a semiconductor device that improves the high temperature stability of the titanium silicide used for the manufacture of gate lines policed in DRAM (random access memory)

The invention relates to semiconductor electronics and can be used when forming the metallization of semiconductor devices on the basis of monosulfide samarium using methods of thermal evaporation, magnetron and ion-plasma sputtering, etc

FIELD: micro- and nanoelectronics, micro- and nanomechanics where insulated conductors are used.

SUBSTANCE: proposed method for filling pockets in solid body with conducting material includes coating of solid-body surface, bottom, and side walls of mentioned pockets with first layer that functions as barrier material preventing diffusion of mentioned conducting material in solid body; application of second layer onto first one that functions as wetting layer for conducting material; application of third layer by way of physical or chemical deposition onto third one from gas phase that has in its composition mentioned conducting material; coating of third layer with fourth one that also incorporates conducting material; melting of conducting material by heating and profile leveling; material melting by heating is conducted after applying third layer and fourth layer is applied by any method of physical deposition from gas phase, chemical deposition from gas phase, chemical deposition from solution, electrochemical deposition, or chemical-mechanical deposition.

EFFECT: facilitated procedure, enlarged functional capabilities.

12 cl, 17 dwg

FIELD: electronics.

SUBSTANCE: invention is attributed to microelectronics and can be used in production of semiconductor devices and integral circuits. Essence of invention: in the method of attaching silicon chip to chip holder, chip seating surface is successively sputtered with two titan-germanium metals, and chip to chip holder soldering is carried out at temperature of 280-300°C.

EFFECT: improvement of chip with chip-holder contact reliability and stability of attachment process.

FIELD: electricity.

SUBSTANCE: method involves notching in bulk of a silicon wafer and silicone removing from the wafer back to uncover notch bottoms. Notching enables silicone pattern formation to represent hollow cell walls that is followed with wall-through oxidation to form a dielectric SiO2 conduit system. Silicon removing from the back of the wafer can be conducted by the deep plasma etch process.

EFFECT: high strength of the insulating element which can be used for manufacturing various MEMS devices in bulk of a standard silicon wafer.

2 cl, 13 dwg

FIELD: electricity.

SUBSTANCE: in manufacturing method of multi-level copper metallisation of VLSIC, which involves application operations of metal and dielectric layers, photolithography and selective etching of those layers, chemical mechanical polishing of dielectric layers, to plate of silicium, which is coated with dielectric material with vertical conductors of underlying structure, which protrude on its surface, there applied is multi-layered conducting film consisting of adhesive barrier, etched and auxiliary layers; grooves are formed in auxiliary layer before etched layers by electrochemical method; copper horizontal conductors are grown inside grooves in open sections of etched layer till grooves are fully filled; the second auxiliary layer is applied to surface of plate, and in that layer holes are made to the surface of horizontal copper conductors; vertical copper conductors are grown by electrochemical method in open sections of horizontal conductors till holes for vertical conductors are fully filled; then, auxiliary layers are removed; conducting layers between horizontal copper conductors are removed; dielectric layers are applied to surface of the plate by smoothing and filling methods, and then dielectric material layers are removed above vertical conductors by means of chemical and mechanical polishing method.

EFFECT: improving quality of copper conductors.

16 cl, 11 dwg, 1 tbl

FIELD: instrument making.

SUBSTANCE: invention relates to semiconductor devices production process, in particular to technology of making contacts with lowered resistance. In method of semiconductor device making contacts are formed on basis of platinum. For this film of platinum with thickness of 35-45 nm is applied by electron-beam evaporation on silicon substrate, heated prior to 350 °C, at rate of deposition of 5 nm/min. Then heat treated in three stages: 1 step is carried out at temperature of 200 °C for 15 minutes, 2 step is carried out at temperature of 300 °C for 10 minutes and 3 stage is at 550 °C for 15 min in forming gas, with mixture of gases N2:H2=9:1.

EFFECT: proposed method of semiconductor device making provides reduced contact resistance, high technological effectiveness, improved parameters of devices, high quality and yield.

1 cl, 1 tbl

FIELD: physics.

SUBSTANCE: invention relates to the field of semiconductor production technology, namely to a technology of low-resistance silicide layers formation. The method of semiconductor devices manufacture includes formation of an amorphous layer by silicon ion implantation on the silicon plate with the energy of 50 keV and dose⋅ of 5⋅1015 cm-2, at the substrate temperature of 25°C. Prior to the palladium layer application, the substrate is sequentially etched in nitric, sulfuric and hydrofluoric acid, then washed with deionized water. The palladium layer is applied at a temperature of 25-100°C, with a thickness of 0.1 microns at a rate of 1.5 nm/sec. After application of the palladium layer, heat-treated under vacuum is conducted at a pressure of (2-8)⋅ 105 mm Hg, temperature of 250°C for 20-30 minutes. As a result, palladium silicide Pd2Si is formed.

EFFECT: invention reduces drag, improves process efficiency, improves parameters, improves quality and increases yield percentage.

1 tbl

FIELD: electricity.

SUBSTANCE: method of increasing the threshold barrier voltage of a transistor based on gallium nitride (GaN), which includes creating gate p-GaN mesa on the surface of the silicon wafer with epitaxial heterostructure of GaN/AlGaN/GaN type, inter-instrument mesa-isolation, forming ohmic contacts to the areas of the transistor drain and source, forming a two-layer resistive mask by lithographic methods, cleaning of the surface of the semiconductor, deposition of thin films of gate metallization, removing of the plate from the vacuum chamber of the evaporator, removal of the resistive mask, prior to the evaporation of thin films of gate metallization the plate is subjected to treatment in an atmosphere of atomic hydrogen for t=10-60 seconds at a temperature of t=20-150°C and flow density of hydrogen atoms on the surface of the plate, equal to 1013-1016 at. cm-2 c-1.

EFFECT: increase in the threshold barrier voltage of the GaN transistor when applying barrier metal films to the p-GaN gate area with a high electronic work function.

5 cl, 3 dwg

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