Method and apparatus for two-step integration |
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IPC classes for russian patent Method and apparatus for two-step integration (RU 2521305):
 Differentiating unit / 2479024
Method is implemented as per the means of high-quality filling of the shaped pulse-width sequences and allocation by means of a reversible pulse counter of pulse difference in adjacent pulse groups, which is the measure of derived physical quantity with further conversion of pulse difference with demodulator 9 to proportional DC voltage. In the proposed device, the information on the derivative is supplied not only in an analogue form as in a prototype, but also in a digital form, which allows using differentiator in digital adjustment and control systems at the information processing stage prior to the processor.
![Functional structure of procedure of logical differentiation of d/dn positional arguments [m<sub>j</sub>]f(2<sup>n</sup>) with account of their sign m(±) to form positional-sign structure ±[m<sub>j</sub>]f(+/-)<sub>min</sub> with minimised number of active arguments (versions)](http://img.russianpatents.com/img_data/948/9485541-s.gif) Functional structure of procedure of logical differentiation of d/dn positional arguments [mj]f(2n) with account of their sign m(±) to form positional-sign structure ±[mj]f(+/-)min with minimised number of active arguments (versions) / 2428738
In one of invention versions the functional structure is made as a positive and a conditionally negative channels "j" and "j+1" digits of input arguments conversion. Besides, each channel includes elements that realise logical functions AND, OR and NOT.
![Method of transforming position-sign arguments ±[n<sub>j</sub>]f(+/-) into structure of arguments ±[n<sub>j</sub>]f(+/-)<sub>min</sub> with minimised number of active arguments and functional structure for implementing said method (russian logic versions)](http://img.russianpatents.com/img_data/937/9376652-s.gif) Method of transforming position-sign arguments ±[nj]f(+/-) into structure of arguments ±[nj]f(+/-)min with minimised number of active arguments and functional structure for implementing said method (russian logic versions) / 2417432
In one version, the functional structure is implemented using elements which execute logic functions AND, OR and NOT. Each j-th order of the functional structure is in form of a positive and conditionally negative channel for converting input arguments nj of the j-th order, nj-1 of the (j-1)-th; in the positive channel, the resultant arguments are created through logic functions AND1, AND2, AND3, logic function NOT1 and logic function OR1; in the conditionally negative channel, the resultant arguments are created through logic functions AND4, AND5, AND6, logic function NOT2 and logic function OR2.
![Method for selective logic differentiation d*/dn of positional analogue signals ±[m<sub>j</sub>]f(2<sup>n</sup>) taking into account logical sign m(±) thereof and functional structure for implementation thereof (russian logic versions)](http://img.russianpatents.com/img_data/937/9376614-s.gif) Method for selective logic differentiation d*/dn of positional analogue signals ±[mj]f(2n) taking into account logical sign m(±) thereof and functional structure for implementation thereof (russian logic versions) / 2417431
In one version, the functional structure is implemented using elements which execute logic functions AND, OR and NOT. Each j-th order of the functional structure is in form of a positive and conditionally negative channel for converting input arguments mj of the j-th order, mj-1 of the (j-1)-th order, mj-2 of the (j-2)-th order and an argument with sign m(±); in the positive channel, the resultant argument +mj is created through logic functions AND1, AND2, AND3, logic function NOT1 and logic function OR1; in the conditionally negative channel, the resultant argument -mj is created through logic functions AND4, AND5, AND6, logic function NOT2 and logic function OR2.
![Method for logic differentiation d/dn of positional analogue signals ±[n<sub>i</sub>]f(2<sup>n</sup>) taking into account logical sign n(±) thereof (russian logic versions)](http://img.russianpatents.com/img_data/937/9376591-s.gif) Method for logic differentiation d/dn of positional analogue signals ±[ni]f(2n) taking into account logical sign n(±) thereof (russian logic versions) / 2417430
Method is implemented using elements which perform logic functions AND, OR and NOT, and involves simultaneous analysis in a conditional ith order of activity of the system of input analogue signals ni of the ith order and ni-1 of the (i-1)th order taking into account the analogue signal of their logical sign n(±), in the positive functional logical structure +f(&) with formation of a positive argument +mi of the resultant analogue signal, and in a conditionally negative functional logical structure -f(&) with formation of a conditionally negative argument -mi of the resultant analogue signal.
![Functional structure for logic differentiation d/dn of analogue signals ±[n<sub>i</sub>]f(2<sup>n</sup>) taking into account logic sign n(±) thereof (versions)](http://img.russianpatents.com/img_data/934/9341144-s.gif) Functional structure for logic differentiation d/dn of analogue signals ±[ni]f(2n) taking into account logic sign n(±) thereof (versions) / 2413988
In one version, the functional structure is implemented using elements which execute logic functions NAND, OR and NOT. Each i-th bit is in form of a positive and conditionally negative channel for converting input arguments nj of the i-th bit, nj-1 of the (i-1)-th bit and a signed argument n(±). The positive resultant argument +mj is generated through NOT1 logic functions, two OR logic functions and a NAND1 logic function. The conditionally negative resultant argument -mj is generated through NOT2 logic functions, two OR logic functions and a NAND2 logic function.
 Optical differentiating nanodevice / 2412481
Optical differentiating nanodevice consists of two constant optical signal sources, two input optical nanofibre Y-splitters, two optical nanofibre couplers, an optical nanofibre N-output splitter, an optical N-input nanofibre coupler, nanofibre and two extension nanotubes.
 Method of boolean differentiation of analogue signals equivalent to binary code and device for realising said method / 2375749
Invention relates to computer engineering and can be used in designing arithmetic circuits and carrying out arithmetic operations, particularly summation and subtraction, in positional-sign codes. The method of Boolean differentiation of analogue signals [ni], where i → 1, 2, …q, equivalent to a binary code, involving formation in the i-th bit of a system of conditionally positive +mi and conditionally negative -mi analogue signals, which assume either conditionally high or active level, or conditionally low or inactive level, is characterised by that, the system of positive +mi and conditionally negative -mi analogue signals in the i-th bit are formed simultaneously through functions f1(&)-AND and f2(&)-AND from a system of input analogue signals ni of the i-th bit and ni-1 of the (i-1)-th bit, in which when generating the positive analogue signal +mi, the level of the analogue signal ni of the i-th bit is measured through function f1(&)-NOT, and when generating the conditionally negative analogue signal -mi, the level of the analogue signal ni-1 of the (i-1)-th bit is measured through function f2(&)-NOT.
 Functional structure of selective logical differentiation of arguments of binary system format f(2n) / 2373640
Invention is related to computer engineering and may be used in building of arithmetical devices for performance of arithmetic operations of summation and subtraction in position-sign codes. Each digit of device in the first version of realisation comprises logical element NOT, three logical elements AND, logical element OR.
 Method of logical differentiation of analogue signals equivalent to binary code and device to this end / 2361269
Invention relates to computer engineering and can be used in making arithmetic units and carrying out arithmetic operations, particularly summation and subtraction processes in position-sign codes. The device contains four AND elements, two OR elements, and three NOT elements.
Method of logical differentiation of analogue signals equivalent to binary code and device to this end / 2361269
Invention relates to computer engineering and can be used in making arithmetic units and carrying out arithmetic operations, particularly summation and subtraction processes in position-sign codes. The device contains four AND elements, two OR elements, and three NOT elements.
Functional structure of selective logical differentiation of arguments of binary system format f(2n) / 2373640
Invention is related to computer engineering and may be used in building of arithmetical devices for performance of arithmetic operations of summation and subtraction in position-sign codes. Each digit of device in the first version of realisation comprises logical element NOT, three logical elements AND, logical element OR.
Method of boolean differentiation of analogue signals equivalent to binary code and device for realising said method / 2375749
Invention relates to computer engineering and can be used in designing arithmetic circuits and carrying out arithmetic operations, particularly summation and subtraction, in positional-sign codes. The method of Boolean differentiation of analogue signals [ni], where i → 1, 2, …q, equivalent to a binary code, involving formation in the i-th bit of a system of conditionally positive +mi and conditionally negative -mi analogue signals, which assume either conditionally high or active level, or conditionally low or inactive level, is characterised by that, the system of positive +mi and conditionally negative -mi analogue signals in the i-th bit are formed simultaneously through functions f1(&)-AND and f2(&)-AND from a system of input analogue signals ni of the i-th bit and ni-1 of the (i-1)-th bit, in which when generating the positive analogue signal +mi, the level of the analogue signal ni of the i-th bit is measured through function f1(&)-NOT, and when generating the conditionally negative analogue signal -mi, the level of the analogue signal ni-1 of the (i-1)-th bit is measured through function f2(&)-NOT.
Optical differentiating nanodevice / 2412481
Optical differentiating nanodevice consists of two constant optical signal sources, two input optical nanofibre Y-splitters, two optical nanofibre couplers, an optical nanofibre N-output splitter, an optical N-input nanofibre coupler, nanofibre and two extension nanotubes.
Functional structure for logic differentiation d/dn of analogue signals ±[ni]f(2n) taking into account logic sign n(±) thereof (versions) / 2413988
In one version, the functional structure is implemented using elements which execute logic functions NAND, OR and NOT. Each i-th bit is in form of a positive and conditionally negative channel for converting input arguments nj of the i-th bit, nj-1 of the (i-1)-th bit and a signed argument n(±). The positive resultant argument +mj is generated through NOT1 logic functions, two OR logic functions and a NAND1 logic function. The conditionally negative resultant argument -mj is generated through NOT2 logic functions, two OR logic functions and a NAND2 logic function.
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FIELD: physics, computer engineering. SUBSTANCE: group of inventions relates to automation and analogue computer engineering and is intended to build precision analogue control devices in aerospace engineering, functional units of analogue computers and analogue processors. The apparatus comprises an integrator, a switch, two closing switches, two analogue memory units and two adders. EFFECT: high accuracy of calculating an integral function of input voltage. 2 cl, 2 dwg
The technical field The invention relates to automation and analog computing and is designed to build functional sites of analog computing machines, precision analog control devices in aerospace engineering, analog processors and other The level of technology Known methods of reducing the errors from the input currents and bias voltages applied to reduce the error integrators based on operational amplifiers (j. Rutkowski. Integrated operational amplifiers. M.: Mir, 1978, p.71-82), which are compensatory measures by introducing additional resistors in the circuit of the operational amplifier. The disadvantage of this method is the need for individual selection of resistors for each of the operational amplifier and consideration during the design process, the effect of additional elements on the functioning of the device. The known method the sampling interval of integration voltage (see patent 2218599, Russia), in which the reduction of errors from the integration of the input current and the bias voltage of the active element without increasing the methodical error of the integration voltage is achieved by the fact that the process of integration is divided into cycles consisting of intervals, during one of which proizvodid the integration of the input voltage, and the rest intervals are the pause, which changes the structure of the active integrator to prevent integration of the input currents and bias voltages, after the completion of the integration process, the result is multiplied by the number of intervals. For reasons that impede the achievement of specified following technical result include integration over a number of cycles, which significantly reduces the performance limit of the waveform only periodic functions, complicated hardware implementation of the method, the method is not embedded event measurement and correction of errors. Closest to the present invention is a method of integrating a periodic voltage (see patent 2247428, Russia), in which the reduction of errors from the integration of the input current and the bias voltage of the active element is achieved by the fact that the process of integration is divided into N steps, including operating cycles and cycles correction, zero level, and additionally split into two equal cycle times that are multiples of the period of the input voltage so that the number of cycles in each cycle is equal to N/2, during the first cycle of work are odd ticks and ticks correction - even during the second cycle working are even ticks and ticks correction is odd is that is For reasons that impede the achievement of specified following technical result when using the prototype include the constraint waveform only periodic functions, the need for additional, in a way not embedded event measurement and correction of errors. Known integrator current (see patent 2442177, Russia), in which the reduction in the errors of integration is due to the fact that the device contains a primary and secondary integrators current, each of which contains stokowy repeater field effect transistor with an insulated gate, the output of which is connected to the inverting input of the operational amplifier, and a capacitor connected between the output of the operational amplifier and the gate of the transistor, and the input of the first integrator through the key and the resistor is connected to ground, and the output through another switch connected to the input of the second integrator. The yield of the latter through a resistor connected to the pin balancing of the first amplifier, connected to provide negative feedback in the circuit specified a different key. The disadvantage of this device is the necessity of preliminary (before integration) balancing integrator and the restriction of the use of the device small values of current. Closest to the proposed is the elimination of the ETS for integration (see patent 2222827, Russia), which increase the accuracy of integration is achieved by using the schema that contains two blocks of integration, the exemplary source voltage, the pulse shaper, the shaper exemplary time interval and the unit of comparison pulse durations. The output signal of the block is fed to the second information input unit integration, which compensates for the influence of destabilizing factors on the output signal of the integrating device. The influence of destabilizing factors on the output signal of the integrating device is reduced by the supply voltage, compensating errors, to an inverse input of the second unit of integration. For reasons that impede the achievement of specified following technical result include limiting the applicability only to integrate a constant voltage, the need for measurement error by using additional units, the influence of the stability and accuracy of additional blocks for error correction of integration, the latter complicates the achievement of the required technical result. The technical result is to increase the accuracy of calculation of integral functions of the input voltage without pre-selection of the elements of the integrator. The objective of the JV is the FDS is achieved by that at the input of the integrator in two equal time intervals, a signal is generated, the voltage value which is equal to the input voltage at the first time interval and zero on the second output signal is the sum of two components, the first component is obtained by integration of the integrator input signal in the first interval, the second as the difference between the first component and the voltage obtained by the integration by the integrator input during the entire integration period, the second component at the end of the second interval is equal to the integration error input bias current and voltage shift at the first time interval with the opposite sign, the sum of the two components leads to a complete compensation of the accumulated error at the end of the second interval. This objective is achieved in that the device comprises an integrator, a switch, two guard key, two blocks analog memory, the first adder, the second adder, the information input device connected to the first contact of the switch, the second contact of the switch is connected to the ground potential, the information input of the integrator is connected to the third contact of the switch, closed when no control signal at the control input of the switch to ground and connecting the input of the integrator to the information input device is and in the presence of the control signal, the first control input device connected to the control contact of the switch and to the control contact of the first end key, the second control input device connected to the control contact of the second closing key entry reset is connected to the reset input of the integrator, the output of the integrator is connected to the input contacts of the first and second ends of the keys, the output of the first closing of a key connected to the input of the first block analog memory, the output of the second closing key is connected to the input of the second block analog memory, the output of the first block of the analog memory connected to the first input of adders and to the first input of the second adder, the output of the second block analog memory connected to the inverted input of the first adder, the output of the first adder connected to the second input of the second adder, the output of the second adder connected to the output device. Listed distinguishing features of the claimed invention improves the accuracy of the device integrating the input voltage by compensating the effects of spurious currents and voltages at the input of the integrator for a single period without re-computation. The push-pull method of integration is as follows. To calculate the integral of the input voltage Determining the exact value of the integral function is performed in two successive time intervals of duration τ of each. The output device 2 summarizes the stress function which are obtained by integrating the input signal and spurious introduced by the integration of the input current offset voltage offset at the input of the integrators, tandthe time since the start of integration. Voltage In the second interval that the voltage remains unchanged: Voltage where Subtracting from (4) (7) and (5) (8), highlight the value of the error integrator for one interval: Substituting formula(4), (5), (9), (10) in (3), we obtain: From the formula (12) it follows that at t and=2τ the result of integration U∑(2τ) exactly coincides with the mathematical value of the integral: Figure 1 presents a structural diagram of a device implementing the method according to the invention. Figure 2 presents a plot of the voltage of the two-stage integrator. The device contains an integrator (6), the switch (5), two guard key (7), (8), two blocks of analog memory (9), (10), the schema subtraction at the adder (11), a second adder (12), data input (1) device connected to the first contact switch (5), the second contact of the switch is connected to the ground potential, the information input of the integrator (6) is connected to the third contact of the switch (5), closed in the absence of the control signal at the control input of the switch to ground and connecting the input of the integrator to the information input (1) of the device in the presence of the control signal, the first control input (3) devices are connected to the control contact switch (5) and to the control contact of the first closing key (7), the second control input (4) devices are connected to the control contact of the second saycause the key (8), input reset (2) is connected to the reset input of the integrator (6), the output of the integrator (6) is connected to the input contacts of the first (7) and second (8) guard key, the output of the first closing key (7) is connected to the input of the first analog block memory (9), the output of the second closing (8) key is connected to the input of the second block analog memory (10), the output of the first block of the analog memory connected to the first input adders (11) and to the first input of the second adder (12), the output of the second block analog memory connected to the inverted input of the first adder (11), the output of the first adder (11) is connected to the second input of the second adder (12), the output of the second adder connected to the output device. Consider the operation of the device for the case when the input signal uI(t) has the form of rectangular pulses of duration τ (figure 2). Integrating the input signal begins with a supply voltage reset U2input (2), an input (3) rectangular pulse integration period of duration τ and the input (4) rectangular pulse period of operation of the device U4duration 2τ. In the first time interval t1-t2on the control contacts of the first closing key (7) and switch (5) is a rectangular pulse integration period U3duration τ, the control contact is which end key (8) is a rectangular pulse period of operation of the device U 4duration 2τ, while both keys are closed, the switch transmits the input signal uI(t) to the input of the integrator (6), at the output of the integrator signal is formed integral function of the input voltage during the first time interval t1-t2containing the error induced by the bias current and voltage shift. This signal through the first key (7) is fed to the first block of the analog memory (9)and Uwyhis fed to the first inputs of adders (11) and (12), through the closed key (8) signal of the integrator is fed to the second block analog memory (10), which is formed by the voltage Uwyhrepeating in the first half-cycle Uwyhand then this voltage is fed to an inverse input of the first adder (1). Thus, at the output of the adder (11) to a second input of the adder (12) in the first time interval t1-t2the voltage Uwyh(t) will be zero. At time t2through the period of time τ after the start of the integration, the momentum of the first integration period U3ends, with the key (7) is opened, the switch connects the input of the integrator to the ground potential, and continues to integrate only the induced error, which, together with the accumulated integral component of the integration period τ is transmitted through the key (10) in the second block analogues is th memory (10). In the first memory block (9) in the interval t2-t3retained accumulated during the previous interval t1-t2the voltage Uwyh(t1), is equal to the integral of the input voltage plus the integration error for the period τ. It is fed to the first inputs of adders (11) and (12). In the process of integration in the second memory block (10) is formed by a signal Uwyhthat accumulates the integration error for the entire period and summarizes its integral function of the input voltage of the first integration interval. This signal is fed to an inverse input of the adder (11), is subtracted from the voltage Uwyh(t2), forming the error signal integrator Uwyh(t) during the whole interval t2-t3with the opposite sign. At the output of the adder (7) there is a gradual compensation of the accumulated errors. Starting from time t3the voltage U4(t)=0, key (8) is opened, the second memory block (10) are fixed voltages Uwyh(t3). In the first memory block (9) the value of the voltage is equal to the integral of the function along with the integration error for the first interval t1-t2Uwyh(t2), in the memory unit (10) is xed Uwyh(t3), is equal to the sum of the integral of the function over the interval t1-t2and error values of integration, neapleendeara for the interval t 1-t3. Uwyh(t2) is input to the adder (11), and its inverted input Uwyh(t3). Thus, at the output of the first integrator is obtained the difference Uwyh(t3)=Uwyh(t2)-Uwyh(t3), which is allocated in the second interval of the integration error of the integrator with the opposite sign. Feeding Uwyh(t3)=Uwyh(t2and Uwyh(t3) to the inputs of the second adder (12), starting at time t3get the voltage Uo(t) is the exact value of the integral of a function of the input voltage Uo(t) for the period τ (dotted line). Similarly, the device will operate with other forms of input signals. Application error compensation of integration in the method and the push-pull device integration does not require alignment integrators, additional procedures and schemes for measuring spurious integration, allows you to fully offset the effect of shear stresses and displacement currents, which distinguishes the proposed solution from the prototype. The proposed technical solutions are new, because public information is not known, the proposed method and the device of the interval of integration. And h is s technical solutions involve an inventive step because of published scientific data and known technical solution is not obvious that the claimed sequence of operations of the method and construction of the device lead to improved accuracy of the method and device integration. The proposed technical solution is industrially applicable, as it is based on circuit solutions and electronic components, widely used in analog and digital devices. 1. The push-pull method of integration, characterized in that in the process of integration at the input of the integrator in two equal time intervals, a signal is generated, the voltage value which is equal to the input voltage at the first time interval and zero on the second output signal is the sum of two components, the first component is obtained by integration of the integrator input signal in the first interval, the second as the difference between the first component and the voltage obtained by the integration by the integrator input during the entire integration period, the second component at the end of the second interval is equal to the integration error input bias current and voltage shift at the first time interval with the opposite sign, the sum of two components leads to a complete compensation of the accumulated error at the end of the second interval. 2. Unit two the akt integration, characterized in that it contains an integrator, a switch, two guard key, two blocks analog memory, the first adder, the second adder, the information input device connected to the first contact of the switch, the second contact of the switch is connected to the ground potential, the information input of the integrator is connected to the third contact of the switch, closed when no control signal at the control input of the switch to ground and connecting the input of the integrator to the information input device when the control signal, the first control input device connected to the control contact of the switch and to the control contact of the first end key, the second control input device connected to the control contact of the second no key entry reset is connected to the reset input of the integrator, the output of the integrator is connected to the input contacts of the first and second ends of the keys, the output of the first closing of a key connected to the input of the first block analog memory, the output of the second closing key is connected to the input of the second block analog memory, the output of the first block of the analog memory connected to the first input of adders and to the first input of the second adder, the output of the second block analog memory connected to the inverted input of the first adder, the output of the first sums the torus is connected to the second input of the second adder, the output of the second adder connected to the output device.
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