Synchronisation circuit, synchronisation method and receiving system. RU patent 2506626.

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to receiving systems that are configured to search for optimum transfer constants of a feedback circuit and are designed to synchronise received signals. The synchronisation circuit has a first phase-lock loop, a second phase-lock loop, a first output circuit, a second output circuit, a first detection circuit, a second detection circuit, a control circuit and a storage area.

EFFECT: high synchronisation accuracy.

11 cl, 10 dwg

The level of technology

The invention relates to the scheme of synchronization, synchronization method and system of reception. First of all, this invention relates to a scheme of synchronization, synchronization method and system of reception, made with the possibility of search of the optimal coefficients of transmission feedback circuit in accordance with individual differences receivers and jitter signal in time in the channel, even when in the frame transmissions use a lot of ways modulation.

Recent years is phenomenal progress in wireless digital communication technologies, including mobile phones, digital broadcasting system (satellite and terrestrial) and wireless LAN.

With regard to the receiver, used for wireless digital transmission, for example, the effectiveness of each schema synchronization component of the structure of the receiver, is important for the implementation of the expanded work reception. In particular, the effectiveness of synchronization synchronization schemes carrier frequency/phase directly affects the errors in the discharge, and thus is critical for the efficiency of the intake of the receiver.

A typical scheme of frequency/phase synchronization can be a digital PLL (phase locked loop)frequency.

Diagram of frequency/phase synchronization, which uses a digital PLL consists of a detector phase error, filter into the feedback circuit of the generator and numerically controlled (NCO).

Figure 1 is a schematic view of showing incomplete structure of a regular receiver, which includes diagram of frequency/phase synchronization using digital PLL.

As shown in figure 1, the receiver includes a scheme 2 high frequency (HF) and scheme 3 demodulation. Signal received by the antenna 1, the receiving radio waves, fed to the input of multiplier 2-1 scheme 2 HF.

Multiplier 2-1 multiplies signal local generation coming from the local generator 2-2, the signal transmitted from the antenna 1. Signal, obtained by multiplying the send to the filter 2-3 lower frequency (LPF).

Local generator 2-2 generates a signal to local generation and passes it to the multiplier 2-1.

LPF 2-3 receives the signal multiplication coming from the multiplier 2-1, and only allows a low-frequency component of the signal to pass through the filtration process. Signal subjected to the filtering process, transmit analog-to-digital Converter (ADC) 2-4.

It is assumed here that the reference symbol f c refers to the frequency of the signal reception, which was modulation, such as PSK (phase shift keying)theta c - phase signal reception, f 0 - frequency signal local generation generated by the local generator 2-2 and θ 0 - phase frequency local generation. When this assumption signal from the low-pass filter that includes difference frequency F, the corresponding f c-f 0 , and the phase difference o, corresponding θ c theta 0 .

ADC 2-4 performs analog-to-digital conversion for a signal from the LPF 2-3. Signal r i , which is a digital signal, obtained by means of the analog-to-digital conversion, passed in scheme 3 demodulation. Reference symbol i denotes the ordinal position of the signal reception in question, in a sequence of symbols.

Signal r i contains an error phase, which can be set in the form of 2πΔft+θ.

Figure 2 is a schematic view, showing typical structure scheme of frequency/phase synchronization, which uses a digital PLL and which is provided in figure 3, demodulation in figure 1.

As shown in figure 2, diagram of frequency/phase synchronization formed scheme 11 PLL multiplier 12. Figure 11 PLL consists of a multiplier 21, detector 22 phase error, filter 23 feedback circuit of the generator and 24 numerically controlled (NCO).

Signal r i subjected PSK modulation, passed in multiplier 21 figure 11, PLL multiplier and a 12.

Multiplier 21 figure 11, PLL multiplies signal r i on the value of the phase control e-j(2Δft+theta) coming from the generator 24 numerically-controlled. Signal received by means of multiplication, passed in detector 22 phase error.

Detector 22 phase error detects an error phase, which can survive in the signal, coming from the multiplier 21, and passes phase error in the filter 23 the feedback circuit.

For example, if the receive signal r i is a signal of the famous character, the detector 22 phase error detects the error in the phase difference between the phase of the character represented by the signal from the multiplier 21, and the phase of the famous character. If the receive signal r i is not a signal of any known signal detector 22 phase error detects the error in the phase difference between the phase of actual character represented by the signal transferred from the multiplier 21, and the phase of the character received in result of the hard decisions.

Filter 23 feedback circuit represents a proportional integral filter feedback circuit, which filters the value phase error coming from the detector 22 phase error. The filtered value passed into the generator 24 with numerical control.

In particular, the multiplier 23-1 filter 23 a feedback loop multiplies the value phase error coming from the detector 22 phase error on the specified coefficient of chain transfer feedback G1. The result of multiplying passed in multiplier 23-2 and adder 23-4.

Multiplier 23-2 multiplies G1-fold amount of phase error coming from the multiplier 23-1, by a specified factor chain transfer G1. The result of multiplying passed in integrator 23-3. Multipliers 23-1 and 23-2 serve as a block multiplication, which adds weight coefficient of chain transfer G1 or G2 on the input signal.

Integrator 23-3 integrate the output from the multiplier 23-2 and passes the result of integration in the accumulator 23-4.

Adder 23-4 adds the output of the multiplier 23-1 and output of the multiplier 23-3. Amount of transfer in the form of the filtration process in generator 24 with numerical control.

Generator, 24 numeric control generates the magnitude of the phase control e-j(2Δft+theta) on the basis of the filter from the filter 23 feedback and passes the value generated in multipliers 21 and 12.

A multiplier of 12 multiplies signal r i on the value of the phase control e-j(2Δft+theta) coming from the generator 24 with numerical control. Signal received by means of multiplication, passed in the form of a synchronized signal detection d i .

The coefficients of the transfer of a feedback circuit G1 and G2 filter 23 feedback define the bandwidth of the filter, which characterizes the filter 23 the feedback circuit. Filter bandwidth 23 feedback circuit and operation of the circuit 11 PLL known to have a relationship described below.

Namely, when the filter chain of feedback has wide (i.e. most) bandwidth, improving the ability to monitor oscillation phase error, but increases the amount of jitter synchronized signal detection transferred from the PLL. And, Vice versa, when a low-pass filter has a narrow (i.e. small) bandwidth, impaired ability to monitor oscillation phase error, but decreases the value of the jitter output sync signal detection. In this regard, reference can be made to laid-Japan patent №2009-26426.

Disclosure of the invention

However, in the receiver used for the active wireless digital transmission, there may be noise in the phase and frequency of the signal reception due to conditions beyond the control of the temperature characteristics of the local generator or unintentional generation in the RF. With the purpose of realization of optimum operation schema synchronization frequency/phase synchronization using digital PLL can thus you must set the optimum ratios of chain transfer in accordance with the individual differences of receiver characteristics and jitter signal in time in the channel.

A digital PLL scheme is made to install only the fixed coefficient of chain transfer. Achieving optimum reception work includes the installation of the coefficient of transmission chains, optimally tailored environment admission for each individual receiver. In the case when the transmission channels dynamically change due to temperature and other factors so that the optimal rate of transmission chains respectively dynamically changes currently being used by the coefficient of chain transfer will not remain optimal.

Moreover, the optimal rate of chain transfer in the filter chain of feedback in the PLL can vary depending on the method of modulation used in the signal reception. For example, a satellite digital broadcasting scheme, adopted in Japan, enables a variety of ways modulation coexist in the same frame. In such a case, if there are only one coefficient of chain transfer, the transfer rate of the circuit can be optimum for a given modulation mode, but not optimal for other methods of modulation. This can lead to poor work of the reception.

The present invention has been developed taking into account these circumstances and provides the schema synchronization, synchronization method and system for receiving, made with the possibility of search of the optimal coefficients of transmission chain in accordance with individual differences receivers and jitter signal in time in the channel, even when in the frame transmissions use a lot of ways modulation.

According to one variant of the implementation of the present invention provided synchronization scheme, which includes: first scheme PLL, made with the possibility of withdrawal, based on the input signal reception, the first signal adjustment phase, representing the value of the phase adjustment admission; the second scheme PLL, made with the possibility of receiving the same signal, and that signal is fed to the first scheme PLL output of the second signal adjustment phase, representing the value of the phase adjustment admission; the first output scheme, performed with the possibility of controlling the phase of the signal reception on the basis of the first signal phase control the output with regulated phase; the second output schema done to control the phase of the signal reception on the basis of the second signal phase control the output with regulated phases; the first scheme of detection, done with the possibility of detecting errors in the first phase control the PLL-based signal with regulated phase output from the first output circuits; a second circuit detection, made with the possibility of detecting errors in phase control second the PLL-based signal with regulating the phase of the output from the second output of the scheme; the scheme of regulation done so that if the error phase control, detected in the first the PLL first scheme detection, more errors regulation phase, apparently detected in the second the PLL second scheme detection, control scheme is made to set the value of the coefficient of transmission of the feedback circuit of the second filter feedback included in the second PLL, as a factor of transmission of the feedback circuit of the first filter chain feedback included in the first PLL; and site of storage, made with the possibility of storing parameter settings transfer factor feedback circuit to set as transfer factor feedback circuit of the first filter in the chain of feedback included in the first PLL. Signal that has the structure of blocks frame composed of many slots transmitted in a variety of transmission modes corresponding to the different methods of modulation and the site storage stores the parameter settings transfer factor chain for each mode of transmission.

Preferably synchronization scheme according to the present invention may additionally include: segment comparison, made with the possibility of comparing the absolute value of the error regulation phase, apparently detected in the first the PLL first scheme with error detection phase control, apparently detected in the second the PLL second scheme detection; and a site search coefficient of transmission of a feedback circuit designed so that whenever a comparison is performed plot of comparison when the signal reception, the corresponding slots in the specified mode of transmission, plot search coefficient of chain transfer is made searchable settings for optimal ratio feedback for this mode of transmission through changes to the preset value the values of the coefficient of transmission of a feedback circuit of the second filter feedback included in the second PLL. If the magnitude of the coefficient of transmission of the feedback circuit of the second filter feedback modify a specified number of times a plot of search of gain the feedback of the site storage can store a value set as the coefficient of chain transfer in the first lowpass filter, as a setting optimal ratio feedback for this mode of transmission.

Preferably synchronization scheme of the present invention may additionally include the parcel identification of the transmission mode, made with the possibility of identification of the transmission mode, it represents the information for identification of the transfer mode for each slot in the signal reception, on the basis of the control signal, obtained by decoding the signal reception. If identified by the number transfer mode corresponds to the specified transfer mode, then plot search ratio feedback can search for the optimal parameter settings transfer factor feedback; and site of storage can store the optimal parameter settings transfer factor feedback circuit in accordance with the number of the mode of transmission identified plot determine the transfer mode.

Preferably the first PLL scheme may include: first scheme of detection, done with the possibility of error detection phase, remaining in the signal with regulated phase; the first filter feedback circuit, made with the possibility of fulfilling the filtering process the message phase, first scheme detection; the first schema generation, made with the possibility of the conclusion of the first signal adjustment phase, depending on the result of the filtering process, performed by the first filter feedback; and the first output scheme, performed with the possibility of controlling the phase of the signal reception on the basis of the first signal adjustment phase, of an output of the first circuit of the generation, with the first output scheme is additionally completed with the possibility of output signal with regulated phase in the first scheme detection as a signal intended for the detection phase error; and the second the PLL can include: a second circuit detection, made with the possibility of error detection phase, remaining in the signal with regulated phase; the second low-pass filter, made with the possibility of fulfilling the filtration process on message phase, the second scheme of detection; the second scheme of generation, made with the possibility of withdrawal of a second signal phase control depending on the result of the filtering process, made the second a low-pass filter; and a second output schema done to control the phase of the signal reception on the basis of the second signal adjustment phase, of an output of the second schema generation, the second output scheme is additionally completed with the possibility of output signal with impact phase to the second scheme detection as a signal intended for detection phase error.

Preferably the first filter chain of feedback may include: first scheme multiplication, made with the possibility of multiplication phase error, first scheme detection, the first transfer coefficient feedback circuits; a second circuit multiplication, made with the possibility of multiplication phase error multiplied first scheme multiplication, on the second transfer rate feedback; and the first scheme addition, made with the possibility of adding the phase error multiplied first scheme multiplication, and the integration phase error multiplied the second scheme multiplication, with the first scheme addition additionally completed with the possibility of withdrawal of addition in the first schema generation; and the second filter chain of feedback may include: the third scheme multiplication, made with the possibility of multiplication phase error, second scheme detection, on the third transfer coefficient feedback; the fourth scheme multiplication, made with the possibility of multiplication phase error multiplied third multiplication scheme, on the fourth transfer coefficient feedback; and the second scheme addition, made with the possibility of adding the phase error multiplied third scheme multiplication, and the integration phase error multiplied fourth multiplication scheme, while the second scheme addition of advanced is made to transfer the amount of the addition in the second schema generation.

Preferably regulatory scheme can specify a different value for the first coefficient of chain transfer, and for the third coefficient of chain transfer.

Under the additional option of the implementation of the present invention, a system of reception, including: the plot receipt, made with the possibility of receiving signal, transmitted by the transmission channel; section of the decoding process of the transmission channel, made with the possibility of processing, which includes the process of synchronized detection in respect of signal received a plot of receipt. Plot of the decoding process of the transmission channel includes: first scheme PLL, made with the possibility of withdrawal, based on the input signal reception, the first signal adjustment phase, representing the value of the phase adjustment admission; the second scheme PLL, made with the possibility of reception of the same signal, and that signal reception, injected in the first scheme PLL output of the second signal adjustment phase, representing the value of the phase adjustment admission; the first output scheme, made with the possibility of controlling the phase of the signal reception on the basis of the first signal phase control the output with regulated phase; the second output schema done to control the phase of the signal reception on the basis of the second signal phase control the output with regulated phase; the first scheme of detection, done with the possibility of detecting errors in the first phase control the PLL-based signal with the regulation of the phase of the output from the first output circuits; a second circuit detection, made with the possibility of detecting errors in the second phase control the PLL-based signal with the regulation of the phase of the output from the second output of the scheme; the scheme of regulation done so that if the error phase control, in the first the PLL first scheme detection more errors regulation phase, in the second the PLL second scheme detection, the control scheme is made to set the value equal to the transfer of the feedback circuit of the second filter feedback included in the second PLL as a factor of transmission of the feedback circuit of the first filter in the feedback included in the first PLL; and site of storage, made with the possibility of storing parameter settings transfer coefficient of a feedback circuit has been established as the transfer coefficient the feedback of the first filter in the feedback included in the first PLL. Signal that has the structure of blocks frame composed of many slots transmitted in a variety of transmission modes corresponding to the different methods of modulation and the site storage stores the parameter settings transfer factor feedback for each mode of transmission.

According to yet another variant of the implementation of the present invention offered reception system, which includes: a plot of the decoding process of the transmission channel, made with the possibility of processing, which includes the process of synchronized detection of the signal received on the transmission channel; and a plot of the output, made with the possibility of output images and/or sound signal based subjected to processing performed by the plot of the decoding process of the transmission channel. Plot of the decoding process of the transmission channel includes: first scheme PLL, done with the ability to output based on the input signal reception, the first signal adjustment phase, representing the value of the phase adjustment admission; the second scheme PLL, made with the possibility of reception of the same signal, and that signal arriving at the input of the first PLL output of the second signal adjustment phase, representing the value of the phase adjustment admission; the first output scheme, made with the possibility of controlling the phase of the signal reception on the basis of the first signal phase control the output with regulated phase; the second output schema, done to control the phase of the signal reception on the basis of the second signal phase control the output with regulated phase; the first scheme of detection, done with the possibility of detecting errors in the first phase control the PLL-based signal with regulating the phase of the output from the first output circuits; a second circuit detection, made with the possibility of detecting errors in the second phase control the PLL-based signal with regulating the phase of the output from the second output of the scheme; the scheme of regulation done so that if the error phase control, in the first the PLL first scheme detection, more errors regulation phase, in the second the PLL second scheme detection, the control scheme is made to set a value equal to the coefficient of transmission of the feedback circuit of the second filter feedback included in the second PLL, as a factor of transmission of the feedback circuit of the first filter in the feedback included in the first PLL; and site of storage, made with the possibility to store the parameter adjustment factor transfer of a feedback circuit has been established as the transfer coefficient feedback circuit of the first filter in the chain of feedback included in the first PLL. Signal reception has a structure blocks the frame, made of many slots transmitted in a variety of transmission modes corresponding to the different methods of modulation and the site storage stores the parameter settings transfer factor feedback for each mode of transmission.

In case, when the present invention is performed, as indicated above, provide the output of the first PLL based on the input signal reception, the first signal adjustment phase, representing the value of the phase adjustment admission; output of the second PLL of the same signal, and that signal arriving at the first scheme PLL output of the second signal adjustment phase, representing the value of the phase adjustment admission; the first output of the scheme helps to adjust the phase of the signal reception on the basis of the first signal phase control output with regulated phase; the second output of the scheme helps to adjust the phase of the signal reception on the basis of the second signal phase control the output with regulated phase; using the first scheme detection provide detection of errors in the first phase control the PLL-based signal with regulating the phase of the output from the first output of the scheme; with the help of the second circuit detection provide detection of errors in the second phase control the PLL-based signal with regulating the phase of the output from the second output circuits; if the error phase control, in the first the PLL first scheme detection, more errors regulation PLL, in the second the PLL second scheme detection, then set the value equal to the transfer of the feedback circuit of the second filter feedback included in the second PLL, as a factor of transmission of the feedback circuit of the first filter in the feedback included in the first PLL; and retain the option to configure the coefficient of transmission of a feedback circuit established as a ratio of the transfer feedback circuit of the first filter in the chain of feedback included in the first PLL. Signal reception has a structure blocks the frame, made of many slots transmitted in a variety of transmission modes corresponding to the different methods of modulation, and parameter settings transfer factor feedback store for each mode of transmission.

Thus, according to the present invention, you can search for the optimal transmission coefficients of the feedback circuit in accordance with individual differences receivers and phase jitter signal in time in the channel, even when in the frame transmissions use a lot of ways modulation.

Brief description of drawings

Figure 1 is a schematic view, showing the partial structure of a regular receiver, which includes diagram of frequency/phase synchronization using digital PLL;

figure 2 is a schematic view, showing typical the structure of the schema of frequency/phase synchronization, which uses a digital PLL and which is provided in the diagram in figure 1;

figure 3 is a schematic view, full frame structure for Advanced system of digital satellite broadcasting;

figure 4 is a schematic view, showing typical modes of transmission in one frame of a sophisticated system of digital satellite broadcasting;

figure 5 is a block diagram showing the typical structure scheme of frequency/phase synchronization applied in practice as one variant of the implementation of the present invention;

6 is a block diagram explaining the typical process of regulation of the transmission factor of the feedback circuit;

Fig.7 is a block diagram showing the typical configuration of the first variant of the implementation of the reception system, which uses a diagram of frequency/phase synchronization in accordance with the variants of the implementation of the present invention;

Fig.8 is a block diagram showing the typical configuration of the second variant of the implementation of the reception system, which uses a diagram of frequency/phase synchronization in accordance with the variants of the implementation of the present invention;

Fig.9 is a block diagram showing the typical configuration of the third variant of the implementation of the reception system, which uses a diagram of frequency/phase synchronization in accordance with the variants of the implementation of the present invention;

figure 10 is a block diagram showing the typical configuration of the personal computer.

A detailed description of the preferred options for the implementation of

Some preferred embodiments of the present invention will now be discussed in detail with reference to the accompanying drawings.

First included the structure of frame Advanced system of digital satellite broadcasting, proposed as a system of digital satellite broadcasting, next-generation in Japan.

Figure 3 is a schematic view, full frame structure for Advanced system of digital satellite broadcasting. As shown, one frame is assembled from 120 slots modulation. In this example slots modulation numbered from number 1 to number 120.

Each slot modulation includes 24 characters for synchronization purposes (marked as «Fsync», «!Fsync» and «Ssync» in figure 3) and 32 well-known symbol (each labeled as a «Pilot» in figure 3)used for the installation of points of constellations signals.

Also, each slot modulation includes 66 elements of data transferred, each of which consists of 136 characters. For example, the elements of data transferred in slot modulation №1 are designated as the «Number 1» - «Data №66», and the elements of data transferred in slot modulation # 2 are shown as the «№67» - «Data №132».

Moreover, in each slot modulation signal inserted between every two elements of data transferred, and the alarm consists of four characters that form the management information on the transmission and multiplexing. Figure 3 reference symbol T denotes the signal .

Each frame of a sophisticated system of digital satellite broadcasting, the structure of which is formed as described above, drawn together from 1115520 characters.

Advanced system of digital satellite broadcasting gives the opportunity of a variety of modes modulation coexist in each frame. For example, in one frame, you can define up to eight transmission modes, each transfer mode allows you to take different modulation methods. In the Advanced system of digital satellite broadcasting, you can use the five methods of modulation, consisting of BPSK, QPSK, 8PSK, 16APSK and 32APSK.

Figure 4 is a schematic view, showing typical modes of transmission in one frame of the Advanced system of digital satellite broadcasting. In order to simplify identified only two modes of transmission. As shown in figure 4, the transfer mode 1 set for ways to transfer 32APSK, appointed slots modulation №1 - №40, and transfer mode 2 for ways to transfer 16APSK appointed slots modulation №41 - №120.

Transfer mode each slot modulation can be defined signal analysis located two shots previously the current frame. Receiver, thus, made with the possibility of acquiring and retaining all of the signals inserted in each slot modulation frame, adopted two shots before. This device allows the receiver to determine the modulation type for each slot modulation adopted in each frame. Regardless of the mode of transmission of each slot modulation should be noted that the signal usually undergoes modulation BPSK with a shift to p/2.

The present invention aim to search for optimal transmission coefficients of the feedback circuit, even where use many different methods of modulation in each frame transmission, such as shown in figure 4.

Figure 5 is a block diagram showing the typical structure scheme of frequency/phase synchronization as one variant of the implementation of the present invention.

Diagram of frequency/phase synchronization, shown in figure 5, is included in the composition of the circuit 3 demodulation receiver that has the same structure as indicated in figure 1.

Structure diagrams of frequency/phase synchronization, shown in figure 5, mainly differs from the structure of the standard scheme of the following: the main PLL scheme is supplemented by a PLL circuit, which has the same structure; transfer coefficients of the feedback circuit filters feedback circuit schematic PLL and subcircuit PLL are variable; optional setting the regulation of the transmission factor of the feedback circuit.

The basic scheme of 31-1 PLL and subcircuit 31-2 PLL designed to use items that are the same specifications, and have the same structure of the scheme. If as a factor of transmission of the feedback circuit of the filter chain of feedback and schematic 31-1 PLL, and in the subcircuit 31-2 PLL set to the same value, and if one and the same signal is fed to the input of the two schemes, then signal from the base schema 31-1 PLL, coincides with the signal transferred from the subcircuit 31-2 PLL.

As explained below, main circuit 31-1 PLL is a scheme which actually performs synchronous detection. Subcircuit 31-2 PLL can be considered a scheme which performs tests for installation of the transmission factor of the feedback circuit, which determines the technical characteristics of the filter feedback circuit schematic 31-1 PLL.

Signal r i , which is the i-th signal (on the i-th symbol), served on the entrance multiplier 41-1 of the basic scheme of 31-1 PLL multiplier 41-2 subcircuit 31-2 PLL multiplier 32. Signal r i includes a mistake phase, which can be written in the form 2πΔft+θ.

Multiplier 41-1 of the basic scheme of 31-1 PLL multiplies signal r i on the value of the phase control e-j(2Δft+theta) coming from the generator 44-1 with numerical control. Signal d main,i derived through multiplication, passed in detector 42-1 phase error. The signal from the multiplier 41-1, coincides with a synchronized detection main d,i , which is the signal phase control passed from the multiplier 32.

Detector 42-1 phase error detects an error phase, which can survive in the signal, coming from the multiplier 41-1, and prints the value of phase error of the basic scheme of e main,i . Detector 42-1 phase error performs error detection phase in the same way as the detector 22 phase error shown in figure 2. The same is true in relation to the detector 42-2 phase error subcircuit 31-2 PLL, which will be discussed later.

Filter 43-1 feedback circuit represents a proportional integral low-pass filter, which filters the value phase error of the basic scheme of e main,i deduced from the detector 42-1 phase error. The filtered value passed into the generator 44-1 with numerical control.

In particular, the multiplier 51-1 filter 43-1 a feedback loop multiplies the value of phase error of the basic scheme of e main,i on the G1 main, in accordance with the coefficient of chain transfer G1 main feedback loop that is installed plot 34 regulation of the transmission factor of the feedback circuit. The value obtained by multiplying the output of the multiplier 52-1 and adder 54-1.

Multiplier 52-1 further multiplies the G2 G1 main times value phase error of the basic scheme of e main,i deduced from the multiplier 51-1. Amount obtained by multiplying the output of the integrator 53-1.

Integrator 53-1 integrate the output from the multiplier 52-1 and passes the result of integration in the accumulator 54-1.

Adder 54-1 adds the output of the multiplier 51-1 and output of the integrator 53-1 and displays the amount of addition in the form of a filtering θ main,i in generator 44-1 with numerical control.

Generator 44-1 numerically controlled generates value of the phase control e-j(2Δft+theta) on the basis of the filter from the filter 43-1 feedback and sends the generated amount of regulation in multipliers 41-1 and 32.

Multiplier 32 multiplies signal r i on the value of the phase control e-j(2Δft+theta) coming from the generator 44-1 with numerical program control of the basic scheme of 31-1 PLL. Signal, obtained by multiplying the output signal as a synchronized detection d main,i .

When this signal, signal containing main d,i , the value phase error of the basic scheme of e main,i and the result of filtration θ main,i pass from the main circuit 31-1 PLL as intermediate signal core PLL in the detector 61 errors regulation core PLL plot 33 comparison errors regulation of the PLL.

Subcircuit 31-2 PLL also performs the same treatment in respect of the same signal reception r i , as a signal fed to the input of the basic scheme of 31-1 PLL.

Namely multiplier 41-2 subcircuit 31-2 PLL multiplies signal r i on the value of the phase control e-j(2Δft+theta) coming from the generator 44-2 with numerical control. Signal d-sub,i obtained by multiplying the output of the detector 42-2 phase error.

Detector 42-2 phase error detects an error phase, which may persist in the signal, coming from the multiplier 41-2, and accordingly displays the value of e sub,i phase error subcircuit. Value esub.i phase error subcircuit deducible from the detector 42-2 phase error output of the multiplier 51-2 filter 43-2 bass.

Multiplier 51-2 filter 43-2 a feedback loop multiplies the value of e sub,i phase error subcircuit on the G1 sub , the specified plot 34 regulation of the transmission factor of the feedback circuit. The value obtained by multiplying passed in multiplier 52-2 and adder 54-2.

For example, the transmission coefficient G1 sub feedback circuit, specified for the multiplier 51-2, different from the coefficient of transmission G1 main feedback loop that is specified for the multiplier 51-1 of the basic scheme of 31-1 PLL.

Multiplier 52-2 further multiplies the G2 G1 sub-multiple of the value of e sub,i phase error subcircuit coming from the multiplier 51-2. The value obtained by multiplying passed in integrator 53-2. Multiplier 52-1 of the basic scheme of 31-1 PLL multiplier 52-2 subcircuit 31-2 PLL thereby perform weighting using the same coefficient of transmission of a feedback circuit. Transfer factor G2 feedback is given a fixed amount.

Integrator 53-2 integrate the output from the multiplier 52-2 and passes the result of integration in the accumulator 54-2.

Adder 54-2 adds the output from the multiplier 51-2 and output of the integrator 53-2 and transfers the amount of the addition, as a result of filtration θ sub,i in generator 44-2 with numerical control.

Generator 44-2 numerically controlled generates value of the phase control e-j(2Δft+theta) on the basis of the filter from the filter 43-2 the feedback loop and displays the generated amount of regulation in the multiplier 41-2.

When this signal, signal containing main d,i , e sub,i phase error subcircuit and filtering results θ sub,i passed from subcircuit 31-2 PLL as intermediate signal subcircuit PLL in the detector 62 errors regulation subcircuit PLL plot 33 comparison errors regulation of the PLL.

Detector 61 errors regulation core PLL plot 33 comparison errors regulation PLL gets intermediate signal of main PLL coming from the main circuit 31-1 PLL, whenever the output signal r i . For example, a detector 61 errors regulation core PLL calculates the value of e main,i change error phase of basic schema obtained from the signal reception r i , having specified number of characters. The magnitude of the changes thus obtained is passed in the comparator 63 in the form of v main error regulation.

The value of v main error regulation is calculated based on the result of the multiplication performed by a multiplier 41-1, i.e. based on the value of e main,i phase error of the basic scheme, representing error phase, continuing in the signal, which was subjected to regulation phase of the scheme's 31-1 PLL. For this reason, the value v main error regulation indicates a bug phase control performed by the scheme's 31-1 PLL.

Detector 62 errors regulation subcircuit PLL gets intermediate signal subcircuit PLL, coming from a subcircuit 31-2 PLL whenever fed to the input signal that a r i . For example, a detector 62 errors regulation subcircuit PLL calculates the value change the value of e sub,i phase error subcircuit obtained from the signal reception r i , having specified number of characters. Change-value thus obtained is passed in the comparator 63 as the value of v sub error regulation.

The value v sub error regulation is calculated based on the result of the multiplication performed by a multiplier 41-2, i.e. based on the value of e sub,i phase error subcircuit, which is a error phase, continuing in the signal, which was subjected to regulation phase circuit 31-2 PLL. For this reason, the value v sub error regulation indicates a bug regulation phase, made a subcircuit 31-2 PLL.

Comparator 63 compares the absolute value of the value v main error regulation coming from the detector 61 errors regulation core PLL, with the value v sub error regulation coming from the detector 62 errors regulation subcircuit PLL. The result of the comparison pass to a site of 34 regulation of the transmission factor of the feedback in response to the notification of withdrawal of the comparison, coming from the timer 64.

As described, the filter 43-1 the feedback circuit of the basic scheme of 31-1 PLL filter 43-2 bass subcircuit 31-2 PLL use different factors G1 main and G1 sub feedback chain transfer. It follows that the difference reflects a mismatch between the coefficients of the transmission chain G1 main and G1 sub feedback circuit occurs in the value v the main error regulation calculated detector 61 errors regulation core PLL, and in the value of v sub error regulation calculated detector 62 errors regulation subcircuit PLL.

In the preceding paragraphs describes the case in which the main values of v and v sub error regulation calculated based on the values of e main,i and e sub,i phase error of the basic scheme and subcircuit. Conversely, the main values of v and v sub error regulation can be calculated from the signal d main,i ; on the basis of the filtering θ main,i and d-sub signal,I ; or on the basis of the filtering θ sub,i .

Timer 64 begin the countdown after receiving the check box initialization coming from that section 34 of the regulation of the transmission factor of the feedback circuit. After a specified time account timer 64 sends notification of the completion of comparison on a plot of 34 regulation of the transmission factor of the feedback circuit. The time required to calculate the value of the error regulation, set on the timer 64, and this established time is counted timer 64. Timer 64 transmits the notification of withdrawal of the comparison in the comparator 63, simultaneously with the notification on the completion of comparison on a plot of 34 regulation of the transmission factor of the feedback circuit.

Plot 34 regulation of the transmission factor of the feedback has placed in it generator 72 control sequence ratio. Plot 34 regulation of the transmission factor of the feedback conducts the search of the optimal coefficients of transmission feedback when checking the status of the basic scheme of 31-1 PLL and subcircuit 31-2 PLL and sets detected optimal transfer coefficients of the feedback of their respective filters feedback circuit.

For example, if the value of v main error regulation calculated detector 61 errors regulation core PLL, more of the value v sub error regulation calculated detector 62 errors regulation subcircuit PLL, plot 34 regulation of the transmission factor of the feedback sets the value of the coefficient of transmission G1 sub feedback filter 43-1 the feedback circuit of the basic scheme of 31-1 PLL, replacing the previously fixed rate transfer G1 main feedback circuit.

The fact that the value v of the main errors of regulation is more than the value v sub error regulation, means that a synchronous receive may be less error by setting the coefficient of transmission G1 sub feedback given to filter 43-2 feedback subcircuit 31-2 PLL. Thus, in this case, the transmission coefficient G1 main feedback filter 43-1 the feedback circuit of the basic scheme of 31-1 PLL replace transfer coefficient G1 sub feedback circuit.

If the value of v sub error regulation calculated detector 62 errors regulation subcircuit PLL, more of the value v main error regulation calculated detector 61 errors regulation core PLL, generator 72 control sequence coefficient of transfer of land 34 regulation of the transmission factor of the feedback circuit leaves factor G1 main transmission feedback unchanged for the filter 43-1 the feedback circuit of the basic scheme of 31-1 PLL.

What value v sub error regulation is greater than the value v of the main errors of regulation, as described above, means that the use of transfer factor G1 main feedback unchanged allows simultaneous data collection with a smaller error than if you use transfer factor G1 sub feedback circuit. Thus, in this case, the transmission coefficient G1 main feedback filter 43-1 the feedback circuit of the basic scheme of 31-1 PLL will not be replaced transfer coefficient G1 sub feedback circuit.

As described, after it was determined whether to replace the transfer coefficient G1 main feedback, change the transfer rate G1 sub feedback filter 43-2 the feedback circuit. Then spend another comparison absolute value between the value of v sub error regulation and value v main error regulation to determine whether to replace the transfer coefficient G1 main feedback circuit. Thus, continue the search for optimal coefficients of transmission chain.

When will change the transfer rate G1 sub feedback generator 72 control sequence transfer factor sets the transfer rate G1 sub feedback, using the formula G1 sub =G1 sub +a, where a is the smallest step quantization installed G1. In this case, if the fixed G1 sub exceeds the maximum permissible value for the G1 max , plot 34 regulation of the transmission factor of the feedback displays the signal of completion of the search.

Plot 34 regulation of the transmission factor of the feedback makes located inside the plot 71 choice regulation of transfer factor for a specific mode of transmission store transfer coefficient G1 main chain of feedback for each of the modes of transmission, provided for selective output ratio feedback circuit. For this reason plot 71 choice regulation of transfer factor for a particular mode of communication has a number of registers, equal to the maximum number N involved modes of transmission (for example, N=8), and each register is used to store the optimal ratio feedback mode of communication in question. It is assumed that these registers provide output values G1 main0 , G1 main1 , ... G1 mainN-1 .

Transfer mode signal reception r i , modulation type, adopted for each mode of transmission, and slots modulation assigned to the transfer mode in question, are , which comes from the decoder 91 error correction.

Generator 92 rooms transfer mode calculates the received character from the check box of the start of the input frame, and on the basis of a sample value of the received character sets which slot modulation belongs to the current received character. Also on the basis of information received from the signal and representing slots modulation assigned to each mode of transmission, generator 92 rooms transfer mode determines the number of the TM identifying the mode of transmission received current symbol (TM call number transmission mode) and passes the number of transfer mode TM on a plot of 34 regulation of the coefficient of transmission chain.

For example, if the current received the flow is «n» of transmission modes, which are multiplexed in it, then the numbers of transmission modes TM are 0, 1, ..., n-1.

Generator 72 control sequence transfer factor stores the number of the transfer mode TM target to conduct a search of the optimum ratio of a feedback circuit. Only during reception of the character TM=TM target , generator 72 control sequence transfer factor allows for the functioning of section 33 comparison errors regulation PLL section 71 choice regulation of transfer factor for a particular transport mode. Generator 72 control sequence coefficient transfer the updated signal EN (permissions), the level of which is high during the reception of the character TM=TM target , the plot 33 comparison errors regulation PLL plot 71 choice regulation of transfer factor for a particular transport mode.

When the diagram of frequency/phase synchronization, shown in figure 5, actuate, room transfer mode to search for the optimal ratio of a feedback circuit is installed in the initial state (TM target =0). Then in the original position are set transfer coefficients of the feedback circuit schematic 31-1 PLL and subcircuit 31-2 PLL.

After the establishment of the original position of the transmission coefficients of the feedback circuit of the main schemes 31-1 PLL and subcircuit 31-2 PLL plot 34 regulation of the transmission factor of the feedback circuit passes the check box initialization plot 33 comparison errors regulation of the PLL.

After receiving the check box initialization from that section 34 of the regulation of transfer factor feedback plot 33 comparison errors regulation PLL resets the result of the comparison value of the error regulation, which is valid at the moment and timer 64. Then plot the 33 comparison errors regulation PLL calculates the value of the error regulation v main,i and v sub,i as described above. Comparator 63 initiates comparison of these values errors regulation by the absolute value.

After the dissolution of the timer 64 plot 33 comparison errors regulation PLL starts the countdown. When the time frame required for calculating the error regulation expires, the timer 64 sends notification of the completion of comparison on a plot of 34 regulation of the transmission factor of the feedback circuit. At the same time the timer 64 passes the command output the result of the comparison in the comparator 63. This, in turn, makes comparator 63 transmit the results of a comparison of the error regulation on the plot 34 regulation of the transmission factor of the feedback circuit.

Taking into account the result of the comparison errors regulation, plot 34 regulation of the transmission factor of the feedback respectively regulates the transfer coefficients of the feedback that comes in the filters 43-1 and 43-2 the feedback circuit. At this stage, if the transfer rate G1 main feedback will replace transfer coefficient G1 sub feedback generator 72 control sequence factor transfer factor transfer G1 sub feedback on the plot 71 choice regulation of transfer factor for a particular transport mode, as described above.

Plot 71 choice regulation of transfer factor for a specific mode of transmission updates the value stored in the register of transfer factor G1 main [TM] feedback circuit, one of the many internal registers, which corresponds to the transfer mode TM, using the values supplied to the input of the generator 72 control sequence ratio.

A section 71 choice regulation of transfer factor for a specific transfer mode selects from the G1 main0 , G1 main1 , ... G1 mainN-1 transmission ratio of a feedback loop, corresponding to the number of transmission mode TM coming from the generator 92 rooms, transmission mode, and transfers the transfer of the feedback in the form of the coefficient of transmission chain in the filter 43-1 the feedback circuit.

If the signal the end of a search is being passed from the generator 72 control sequence transfer factor before receipt of the notification about the completion of comparison from the plot 33 comparison errors regulation PLL, then perform a check to determine whether the value TM target n-1 to determine whether ended the search for optimal coefficients of transmission feedback for all modes of transmission. If the value of TM target is not equal to n-1, then the value of TM target is incremented by 1 with the purpose of search of the optimal ratio feedback for the next transfer mode. At the same time transfer coefficients of the feedback circuit schematic 31-1 PLL and subcircuit 31-2 PLL are set back to its original position.

In the manner described above, conduct the search of the optimal ratio feedback in relation to each value TM target from 0 to n-1. This allows you to set an optimum transmission ratio of a feedback loop for each mode of transmission, working on the basis of different methods of modulation.

Conversely, if the signal of completion of the search, transfer from the generator 72 control sequence transfer factor before receipt of the notification about the completion of comparison from the plot 33 comparison errors regulation PLL and if the value of TM target equal to n-1, then the value of the TM target can be reset to 0. I.e. after the search of the optimal transmission gain feedback about the values TM target from 0 to n-1, you can re-initiate another search of the optimum ratio of a feedback circuit in respect of each amount TM target from 0 to n-1.

Thus, even in case of jitter signal in time in the characteristics of the transmission of the involved transmission channels, searches for optimal transmission coefficients of the feedback can be performed constantly, and detected transfer coefficients feedback can be used continuously.

At the stage of S12 generator 72 control sequence transfer factor sets the initial state of the register transfer factor a feedback loop within the plot 71 choice regulation of transfer factor for a particular transport mode, which corresponds to the variable TM target . In this example, the installation of the register of the coefficient of chain transfer in question, presents G1 main_new , and its initial value - G1 init . Installing G1 main_new is used as a coefficient of chain transfer G1 main filter 43-1 the feedback circuit.

Also on stage S12 generator 72 control sequence transfer factor sets the initial position of the transmission coefficient of G1 sub feedback filter 43-2 the feedback circuit. The original value of the coefficient of transmission G1 sub feedback circuit represents the smallest coefficient of chain transfer of a feedback, i.e. G1 min . Parameter G1 sub is used as a coefficient of transmission G1 sub feedback filter 43-2 the feedback circuit.

Proceed to S13 carried out after installation of the transmission factor of the feedback to the original position. At the stage of S13 plot 34 regulation of the transmission factor of the feedback box displays the initialization of the plot 33 comparison errors regulation of the PLL.

After receiving the check box initialization plot 33 comparison errors regulation PLL resets already made a diff error regulation, the reading of the internal timer.

Also detector 61 errors regulation core PLL plot 33 comparison errors regulation PLL evaluates the value of v main error regulation on the basis of the intermediate signal core PLL coming from the main circuit 31-1 PLL. Detector 62 errors regulation subcircuit PLL evaluates the value of v sub error regulation on the basis of the intermediate signal subcircuit PLL coming from the subcircuit 31-2 PLL.

After you reset the timer 64 initiates the countdown. After the specified time required for the calculation of the main values of v and v sub error regulation, timer 64 display a notification about the completion of the comparison on a plot of 34 regulation of the transmission factor of the feedback circuit. At the same time the timer 64 displays command output the result of the comparison in the comparator 63. In response to the output of the comparison comparator 63 displays the result of the comparison of absolute value between the values of v main and v sub error regulation on the plot 34 regulation of the transmission factor of the feedback circuit.

At the stage S14 generator 72 control sequence transfer factor determines whether the notification about the completion of comparison, the display of the timer 64. If you determine that the notification about the completion of the comparison is not , control is passed on stage S20.

At the stage of S20 determine displayed if the signal completion of the search. If you determine that signal the end of a search is not already displayed, control is passed at the stage of S21. At the stage of S21 notification of the completion of comparison from the timer 64 request at intervals specified period of time in the idle state. Control then returns to the stage S14.

If at the stage S14 determine what notification of the completion of comparison, control is passed on stage S15.

At the stage S15 generator 72 control sequence transfer factor determines whether v main >v sub on the basis of the comparison, coming from the comparator 63.

If during the S15 determine that v main >v sub shall proceed to S16. At the stage S16 generator 72 control sequence transfer factor replaces the coefficient of chain transfer G1 main_new on the G1 sub that is currently set as a factor of transmission of the feedback filter 43-2 the feedback circuit. At this stage generator 72 control sequence transfer factor displays the preset signal generation plot update check box within the plot 71 choice regulation of transfer factor for a particular transport mode. In turn plot generation checkbox update passes the check box for register transfer factor a feedback loop, corresponding to the number of transmission mode TM, which is valid at the moment.

If during the S15 determine that v main ≤v sub instead v main >v sub , then step S16 miss.

At the stage of S17 generator 72 control sequence transfer factor sets G1 sub +a and together with the updates transfer coefficient G1 sub feedback circuit, where a mean value of the coefficient of transmission, corresponding to the smallest quantization step transfer factor G1 G1 main and G1 sub ) feedback circuit.

At the stage of S18 generator 72 control sequence transfer factor determines whether the coefficient of chain transfer G1 sub , updated on the stage, S17, the maximum allowed value G1 max .

If at the stage of S18 determine that the coefficient of chain transfer G1 sub exceeded the maximum value of G1 max , control is passed on stage S19. At the stage of S19 generator 72 control sequence transfer factor displays the signal completion of the search.

Management return on stage S13, if the stage S18 determine the transfer ratio G1 sub feedback circuit did not exceed the maximum size G1 max , or after completion of phase S19.

After the withdrawal phase S19 signal completion of the search output signal confirm the stage S20. Control then returns to the stage S22.

At the stage of S22 generator 72 control sequence transfer factor determines whether a variable is equal to TM target n-1. If you determine that the variable TM target is not equal to n-1, control is passed PA stage S23. At the stage of S23 generator 72 control sequence transfer coefficient increases variable TM target 1. Management then return to the stage S12. I.e. perform another search of the optimal coefficient of chain transfer in the next transfer mode.

If at the stage of S22 define that variable TM target is equal to n-1, management of return on the stage of S11. I.e. after the search of the optimal coefficients of transmission feedback all rooms transfer mode initiate the second search of the transmission factor of the feedback for each value TM target from 0 to n-1. In the second and subsequent search no need to install G1 main_new the original state at the stage S12.

And, Vice versa, if the stage S22 define that variable TM target is equal to n-1, the process of regulation of the transmission factor of the feedback can be completed.

The process of regulation of the coefficient of transmission chain perform in the manner described above. Thus, according to the present invention, you can search for the optimal transmission coefficients of the feedback circuit in accordance with individual differences receivers and jitter signal in time in the channel, even when in the frame transmissions use a lot of ways modulation.

The preceding paragraphs explain instances in which the search for the optimal ratio feedback as transfer factor G1 a feedback loop for use in direct operations of multiplication performed on mistake phase diagram of frequency/phase synchronization. Conversely, you can search for the coefficient of transmission G2 feedback circuit for use in the operation of multiplication to be run over phase error resulting from the multiplication using transfer factor G1 feedback circuit.

As another alternative, you can perform searches and transfer factor G1 a feedback circuit, gain G2 feedback circuit.

Fig.7 is a block diagram showing the typical configuration of the first variant of the implementation of the reception system, which uses a diagram of frequency/phase synchronization on options for implementation of the present invention.

Reception system figure 7 consists of a plot 101 receipt, section 102 of the decoding process of the transmission channel, and the section 103 of the process of decoding a source of information.

Plot 101 receipt receives a signal through the channels of transmission, such as terrestrial digital broadcasting system, satellite digital broadcasting system, CATV network and the Internet (not shown), and forwards the received signal on the plot 102 of the decoding process of the transmission channel.

Taking into account the signal received plot 101 receiving channels of transmission, plot 102 of the decoding process of the transmission channel is in the process of decoding the transmission channel, including synchronized detection and error correction for the received signal, and sends the signal, received in the result of the decoding process, the plot 103 of the process of decoding a source of information. I.e. plot 102 of the decoding process of the transmission channel includes the structure of the schema of frequency/phase synchronization, shown in figure 5, which complies with the aforementioned synchronized detection.

Plot 103 of the process of decoding a source of information performs the process of decoding a source of information for the signal to be subjected to the process of decoding the transmission channel, the process of decoding a source of information includes the process of expansion of compressed data back to the source of information through which were collected the data transmitted.

I.e. signal, which contains plot 101 collection of data transmission channels, could be subjected to coding to compress by which the original information was compressed to reduce the amount of data, such as video or audio data. In this case, the plot 103 of the process of decoding a source of information performs the process of decoding a source of information for the signal to be subjected to the process of decoding the transmission channel, the process of decoding a source of information includes the process of expansion of compressed data back to the original information.

If the signal received plot 101 receiving channels of transmission, has not been subjected to coding to compress, plot 103 decode processing source of information does not process of expansion of compressed data back to the original information. The process of expansion involves decoding MPEG, for example. The process of decoding a source of information may include scrambling in addition to the enlargement process.

Reception system figure 7 can be used in TV tuners, for example, for reception of digital TV transmissions. Plot 101 receipt, plot 102 decode processing of the transmission channel and plot 103 decode processing source of information can each be performed as a separate device (hardware, for example, the IC (integrated circuit) or a software module).

And, Vice versa, plot 101 receipt, plot 102 decode processing of the transmission channel and plot 103 decode processing source of information may be made all together as a separate device. As an alternative plot 101 obtain a plot of 102 decode processing transmission channel can be performed together as a separate device.

Fig.8 is a block diagram showing the typical configuration of the second variant of the implementation of the reception system, which uses a diagram of frequency/phase synchronization on options for implementation of the present invention.

Components on Fig.8 with relevant equivalents shown in Fig.7 are marked with a similar reference positions, and their explanations can be omitted, when appropriate.

System configuration reception on Fig.8 is shared with the configuration of the equivalent figure 7, which provides plot 101 receipt, plot 102 decode processing of the transmission channel and plot 103 of the process of decoding a source of information. On the other hand, the configuration on Fig.8 differs from the configuration of figure 7 because it is additionally provided with a plot of 111 output.

Plot 111 output can, as a rule, consist of a display device to display images and output speakers sounds. Essentially plot 111 output displays images and sounds extracted from the signal received from a section 103 of the process of decoding a source of information. In short, the plot 111 output is a component that displays images and/or sounds.

Reception system on Fig.8 can be used, for example, in television sets for receiving digital TV and radio receivers for radio reception.

If the signal, which is collected on the section 101 of data collection, not been coding for compression, then the signal transmitted from a section 102 of the decoding process of the transmission channel, served directly on the plot 111 output.

Figure 9 is a block diagram showing the typical configuration of the third variant of the implementation of the reception system, which uses a diagram of frequency/phase synchronization options for the implementation of the present invention.

Components figure 9 with relevant equivalents shown in Fig.7 are marked with a similar reference positions, and their explanations can be omitted, when appropriate.

System configuration reception figure 9 is a common configuration equivalent figure 7, which provides plot 101 obtain a plot of 102 decode processing transmission channel. On the other hand, the configuration of figure 9 is different from the configuration figure 7 because it is not provided in the plot 103 of the process of decoding the information source is additionally provided with a plot of 121 entries.

Plot 121 viewer records(stores) signal (for example, packages TS to MPEG, transmitted from a section 102 of the decoding process of the transmission channel on the recording media(information), such as optical drives, hard drives, floppy disks and flash memory cards.

The above system of reception figure 9 can be used, for example, in the devices for recording to record TV shows.

In another example, the system of reception figure 9 can be provided with a plot of 103 the process of decoding a source of information. In this case the segment 121 recording can record subjected to the process of decoding information source plot 103 of the process of decoding a source of information, i.e., images, and sounds, for which data are gathered through a process of decoding.

A number of processes described above, may be made or hardware, or software. In case when it is necessary to do processing on the basis of the software, the programs composing these programs may be either placed in advance in dedicated hardware of the computer used or installed after use through a computer network or the appropriate media records on the universal personal computer or similar equipment, such as a personal computer 700 shown in figure 10, which is performed with the possibility of performing a variety of functions on the basis of currently installed programs.

10 CPU (Central processing unit) 701 performs various processes in accordance with the programs stored in ROM (read only memory device) 702 or in accordance with the programs that are loaded from the device 708 record in RAM (random access memory) 703. RAM 703 can also place the data and other resources required CPU 701 to perform various processing.

CPU 701, ROM 702 and RAM 703 connected by bus 704. Interface 705 I/o connected to the bus 704.

Interface 705 I/o is connected 706 input device 707 / o device 708 recording device and 709 communication. Device 706 input, as a rule, consists of a keyboard and mouse. Device 707 / o is usually derived unit display such as LCD (liquid crystal display) and speakers. Device 708 record, as a rule, formed a hard disk. Device 709 usually formed the modem interface of the network such as a LAN card. Device 709 connection communicates through computer networks, including the Internet.

Drive 710 can be connected if required interface 705 I/o. Removable media 711, such as magnetic disks, optical disks, magneto-optical disks or semiconductor memory blocks that can be loaded into the drive 710. Computer programs can be extracted from a downloaded removable media and installed if necessary, the device 708 record.

In case, when a number of the above processes will run the software, the programs composing these software tools can be installed through computer networks, including the Internet, or from storage media, such as removable media 711.

As shown in figure 10, the media which in addition to their computers offered to users and which place a program, can be presented not only removable storage 711, such as magnetic disk drives (including floppy disks; a registered trademark), optical disks (including CD-ROM, permanent storage device CD-ROM) and DVD (digital versatile disc), magneto-optical disks (including MD (MiniDisc; a registered trademark)) or semiconductor memory blocks, but also such carriers of information, as ROM 702 or hard disks contained on the device 708 record. Recent media programs stored on them are preinstalled in the computer, which is provided to the user.

In this description, a series of processes described above, which includes not only the processes that are running in the sequence shown (i.e. on the basis of time series, but also the processes that can run concurrently or separately and not necessarily in chronological order.

Professionals should be understood that various modifications, combination, and changes can take place depending on the design requirements and other factors in the volume of the applied formula of the invention or its equivalents.

The present invention contains the object associated with the object disclosed in the priority application for a patent Japan JP 2010-219644, registered in the Patent office of Japan on September 29, 2010, the full contents of which are included in this application by reference.

1. Synchronization scheme, containing: the first scheme, phase-locked loop, made with the possibility of withdrawal, based on the input signal reception, the first signal adjustment phase, representing the value of the phase control referred signal reception; the second scheme, phase-locked loop, made with the possibility of reception of the same signal, and the signal input referred to in the first scheme, phase-locked loop to output the second signal adjustment phase, representing the value of the phase control referred to signal receiving; the first output scheme, made with the possibility of regulating the phase referred signal reception on the basis of the first signal phase control the output with regulated phase; the second output schema, made with the possibility of regulating the phase referred signal reception on the basis of the second signal phase control the output with regulated phase; the first scheme of detection, done with the possibility of error detection phase control referred to in the first scheme, phase-locked loop on the basis of the signal with regulated phase, of an output from the first output circuits; a second circuit detection, made with the possibility of error detection phase control referred to in the second scheme, phase-locked loop on the basis of the signal with regulated phase, of an output from the second output of the scheme; the scheme of regulation done so that if the error phase control, referred to in the first scheme, phase-locked loop first mentioned scheme detection, more errors regulation phase, referred to in the second scheme, phase-locked loop referred to the second scheme detection referred regulatory scheme is made to set the value equal to the transfer of the feedback circuit of the second filter feedback included into the composition of referred second PLLs, as a factor of transmission of the feedback circuit of the first filter in the feedback included in the first mentioned PLLs; and site of storage, made with the possibility of storing parameter settings transfer factor feedback loop that is installed as a chain transfer coefficient feedback referred to the first filter in the chain of feedback included in the first mentioned PLLs; the signal that has the structure of blocks frame composed of many slots transmitted in a variety of transmission modes corresponding to the different methods of modulation, and the aforementioned plot store is made with the possibility of storage of the said parameter settings transfer factor feedback for each referred transfer mode.

2. Synchronization scheme according to claim 1, further comprising: a plot of comparison, made with the possibility of comparing the absolute value of the error regulation phase, apparently detected in the first mentioned scheme, phase-locked loop that first detection scheme, with an error regulation phase, apparently detected referred to in the second scheme, phase-locked loop referred to the second scheme detection; and a site search coefficient of transmission of a feedback circuit designed so that each time you perform the comparison referred to plot comparing the received signal reception, appropriate to the mentioned slots defined mode of transmission, and the said plot search transfer factor feedback circuit is made with the possibility of searching for the optimal parameter settings of the transmission factor of the feedback to this mode of transmission through changes to the preset value the values of the coefficient of transmission of a feedback circuit referred to the second filter, the feedback included into the composition of referred second PLLs; changing the value of the coefficient of transmission of a feedback circuit referred to the second filter, the feedback given number of times mentioned plot search-loop transfer factor communication referred to plot storage is configured to store the value set as the coefficient of transmission of a feedback circuit referred to the first filter in the chain of feedback as the optimal parameter settings transfer factor feedback referred to transfer mode.

5. Synchronization scheme according to claim 4, which referred to the first filter feedback circuit includes: first scheme multiplication, made with the possibility of multiplication phase error, apparently detected that first detection scheme, the first transfer coefficient feedback circuits; a second circuit multiplication, made with the possibility of multiplication phase error multiplied first mentioned scheme multiplication, on the second transfer rate feedback; and the first scheme addition, made with the possibility of adding the phase error multiplied first mentioned scheme multiplication, and the integration phase error multiplied referred to the second scheme multiplication, and referred to the first scheme, adding additional performed with the possibility of withdrawal of addition in the first scheme of generation; and the said second low-pass filter includes: the third scheme multiplication, made with the possibility of multiplication phase error, apparently detected referred to the second scheme detection, on the third transfer coefficient feedback; the fourth scheme multiplication, made with the possibility of multiplication phase error multiplied by such third scheme multiplication, the fourth factor of transmission of the feedback; and the second scheme addition, made with the possibility of adding the phase error multiplied by such third scheme multiplication, and the integration phase error multiplied mentioned fourth multiplication scheme, the above-mentioned second scheme addition additionally completed with the ability to withdraw the amount of the addition in the second scheme of generation.

6. Synchronization scheme of claim 5, which referred to the scheme of regulation is made to set a different value, and for the first coefficient of transmission of a feedback circuit, and for this third factor of transmission of the feedback circuit.

7. Sync, comprising stages: the first PLLs provide a conclusion on the basis of the input signal reception, the first signal adjustment phase, representing the value of the phase control referred signal reception; second PLLs ensure reception of the same signal, and the signal coming in the first scheme, phase-locked loop to output the second signal adjustment phase, representing the value of the phase control referred signal reception; the first output of the scheme helps to adjust the phase referred signal reception on the basis of the first signal phase control the output with regulated phase; the second output of the scheme helps to adjust the phase referred signal reception on the basis of the second signal phase control output with regulated phase; using the first scheme detection provide error detection phase control referred to in the first scheme, phase-locked loop on the basis of the signal with regulated phase, of an output from the first output of the scheme; with the help of the second circuit detection provide error detection phase control referred to in the second scheme, phase-locked loop on the basis of the signal with regulated phase, of an output from the above-mentioned second output circuits; if the error phase control, referred to in the first scheme phase-locked loop first mentioned scheme detection, more errors regulation phase, referred to in the second scheme, phase-locked loop referred to the second scheme detection, then set the value equal to the transfer of the feedback circuit of the second filter feedback included into the composition of referred second PLLs, as a factor of transmission of the feedback circuit of the first filter in the feedback included in the first mentioned PLLs; and retain the option set the transfer of a feedback circuit established as a factor of transmission of the feedback that first filter the feedback included in the first mentioned PLLs; this is referred to signal that has the structure of blocks frame composed of many slots transmitted in a variety of transmission modes corresponding to the different methods of modulation; and the aforementioned parameter settings transfer factor feedback retain for each referred transfer mode.

8. Reception system, containing: a plot of receipt, made with the possibility of receiving signal through a transmission channel; and parcel of the process of decoding the transmission channel, made with the possibility of processing, which includes the process of synchronized detection in respect of the signal received mentioned plot of receipt; the mentioned plot of the decoding process of the transmission channel includes: first scheme, phase-locked loop, made with the possibility of withdrawal, based on the input signal reception, the first signal phase control, which represents the value of the phase control referred signal reception; the second scheme, phase-locked loop, made with the possibility of reception of the same signal, and the signal input referred to in the first scheme, phase-locked loop to output the second signal adjustment phase, representing the value of the phase control referred signal reception; the first output scheme, made with the possibility of regulating the phase referred signal reception on the basis of the first signal phase control the output with regulated phase; the second output schema, made with the possibility of regulating the phase referred signal reception on the basis of the second signal phase control the output with regulated phase; the first scheme of detection, done with the possibility of error detection phase control referred to in the first scheme, phase-locked loop on the basis of the signal with regulating the phase of the output from that first output circuits; a second circuit detection, made with the possibility of error detection phase control referred to in the second scheme, phase-locked loop on the basis of the signal with regulated phase, of an output from the second output of the scheme; the scheme of regulation done so that if the error phase control, referred to in the first scheme, phase-locked loop first mentioned scheme detection, more errors regulation phase, referred to in the second scheme, phase-locked loop referred to the second scheme detection, the afore-regulatory scheme is made to set the value equal to the transfer of the feedback circuit of the second filter of a feedback circuit included in the said second PLLs, as a factor of transmission of the feedback circuit of the first filter in the feedback included in the first mentioned PLLs; and site of storage, made with the possibility of storing parameter settings transfer factor feedback loop that is installed as a factor of transmission of the feedback that first filter the feedback included in the first mentioned PLLs; this is referred to signal that has the structure of the blocks of the frame, made of many slots transmitted in a variety of transmission modes corresponding to the different methods of modulation, and the aforementioned plot store is made with the possibility of storage of the said parameter settings transfer factor feedback for each referred transfer mode.

9. Reception system, containing: a plot of the decoding process of the transmission channel, made with the possibility of processing, which includes the process of synchronized detection in respect of the signal received on the transmission channel; and parcel of the process of decoding a source of information, made with the possibility of decoding, treated performed mentioned plot of the decoding process of the transmission channel, the data to transfer; the mentioned plot of the decoding process of the transmission channel includes: first the scheme of phase-locked loop, made with the possibility of withdrawal, based on the input signal reception, the first signal adjustment phase, representing the value of the phase control referred signal reception; the second scheme, phase-locked loop, made with the possibility of reception of the same signal, and the signal reception, led referred to in the first scheme, phase-locked loop to output the second signal adjustment phase, representing the value of the phase control referred signal reception; the first output scheme, made with the possibility of controlling phase referred signal reception on the basis of the first signal phase control the output with regulated phase; the second output schema, made with the possibility of regulating the phase referred signal reception on the basis of the second signal phase control the output with regulated phase; the first scheme of detection, done with the possibility of error detection phase control referred to in the first scheme, phase-locked loop on the basis of the signal with regulating the phase of the output from that first output circuits; a second circuit detection done with the possibility of error detection phase control referred to in the second scheme, phase-locked loop on the basis of the signal with regulated phase, of an output from the second output of the scheme; the scheme of regulation done so that if the error phase control, referred to in the first scheme, phase-locked loop first mentioned scheme detection, more errors regulation phase, referred to in the second scheme, phase-locked loop referred to the second scheme detection, the afore-regulatory scheme is made with set value equal to the transfer of the feedback circuit of the second filter feedback included into the composition of referred second PLLs, as a factor of transmission of the feedback circuit of the first filter in the feedback included in the first mentioned PLLs; and site of storage, made with the possibility of storing parameter settings transfer factor feedback loop that is installed as a factor of transmission of the feedback that first loop filter connection included in the first mentioned PLLs, referred to signal that has the structure of blocks frame composed of many slots transmitted in a variety of transmission modes corresponding to the different methods of modulation, and the aforementioned plot store is made with the possibility of storage of the said parameter settings transfer factor feedback for each referred transfer mode.

11. Reception system, containing: a plot of the decoding process of the transmission channel, made with the possibility of processing, which includes the process of synchronized detection in respect of the signal received on the transmission channel; and fragment of the record made with the possibility of signal recording treated performed mentioned plot of the decoding process of the transmission channel; the mentioned plot of the decoding process of the transmission channel includes: first scheme, phase-locked loop, made with the possibility of withdrawal, on the basis of input signal reception, the first signal adjustment phase, representing the value of the phase control referred signal reception; the second scheme, phase-locked loop, made with the possibility of reception of the same signal, and the signal input referred to in the first scheme, phase-locked loop to output the second signal adjustment phase, representing the value of the phase control referred signal reception; the first output scheme, made with the possibility of regulating the phase referred signal reception on the basis of the first signal phase control output with regulated phase; the second output schema, made with the possibility of regulating the phase referred signal reception on the basis of the second signal phase control the output with regulated phase; the first scheme of detection, done with the possibility of error detection phase control referred to in the first scheme, phase-locked loop on the basis of the signal with regulating the phase of the output from that first output circuits; a second circuit detection, made with the possibility of error detection phase control referred to in the second the scheme of phase-locked loop on the basis of the signal with regulated phase, of an output from the second output of the scheme; the scheme of regulation done so that if the error phase control, referred to in the first scheme, phase-locked loop first mentioned scheme detection, more errors regulation phase, referred to in the second scheme, phase-locked loop referred to the second scheme detection, the afore-regulatory scheme is made to set the value equal to the transfer of a feedback circuit the second filter, the feedback included into the composition of referred second PLLs as a factor of transmission of the feedback circuit of the first filter in the feedback included in the first mentioned PLLs; and site of storage, made with the possibility of storing parameter settings transfer factor feedback loop that is installed as a factor of transmission of the feedback that first filter the feedback included in the first mentioned PLLs; this referred to signal that has the structure of blocks frame composed of many slots transmitted in a variety of transmission modes corresponding to the different methods of modulation, and the aforementioned plot store is made with the possibility of storage of the said parameter settings transfer factor feedback for each referred transfer mode.