# Apparatus for iterative decoding of block turbo codes and siso decoder for realising said method

FIELD: radio engineering, communication.

SUBSTANCE: apparatus for decoding block turbo codes has a first random-access memory unit 1, a second random-access memory unit 2, a third random-access memory unit 3, a SISO decoder 4, a decision unit 5, a first limiter 6, a read-only memory unit 7, a multiplier unit 8, a second limiter 9. The SISO decoder has a random-access memory unit 10, a clock generator 11, a switch 12, a counter 13, a read-only memory unit 14, a Walsh function coefficient signal former 15, an analysed sequence former 16, a first adder 17, a first subtractor unit 18, a doubling unit 19, a multiplier unit 20, a first divider unit 21, a second adder 22, a third adder 23, a second subtractor unit 24, a second divider unit 25, a third divider unit 26, a limiter 27.

EFFECT: high noise immunity of block turbo codes.

3 cl, 6 dwg

Group of inventions relates to a device for the decoding of block turbocodes and SISO decoder to implement and can be used in digital communication systems.

It is known that block turbocode are formed on the basis of the consolidation of block codes, in particular the Association of Hamming codes or extended Hamming codes [1].

Figure 1 shows the block diagram of the turbo code. Code word block turbo code is equivalent to a two-dimensional matrix - matrix rows correspond to the code words constituting a block code C_{1}with parameters (n_{1}, k_{1}), the columns of the matrix correspond to the code words constituting a block code C_{2}with parameters (n_{2}, k_{2}). Here n is the number of code symbols in the code word, k is the number of information symbols comprising code. The total number of information symbols of the turbo code is k=k_{1}k_{2}the total number of code symbols in the code word is equal to n=n_{1}n_{2}.

For turbocodes apply algorithms for iterative decoding [1], the essence of iteration which is the calculation of the soft symbol decisions based on the algorithm for symbol-by-symbol decoding for horizontal (vertical) components of the codes and the use of data character soft decisions for the subsequent iteration decoding vertical horizon is inih) components of the code.

The calculation of the soft symbol decision is performed by using the SISO decoder (Soft Input - Soft Output) with a soft input and soft output.

Finish decoding occurs after you perform a specified number of iterations. After the last iteration accepted the hard (binary) decisions about the transmitted information symbols.

The prior art known to the device [2] iterative decoding of block turbocodes and SISO decoder. The device contains three blocks of RAM, two adder, SISO (Soft Input - Soft Output decoder, the decision block and the schema normalization. The processed samples of demodulator signals stored in the first memory block, the output of which is connected to the first input of the first adder and to the inverted input of the second adder, the output of the first adder connected to the input of the SISO decoder, the output of which is connected to the first input of the second adder and the input of the decision block, the output of the second adder connected to the input of the second memory block, the output of which is connected to the input schema normalization, the output of which is connected to the second input of the first adder, the output of the decision block is connected to the input of the third memory block, where hard decisions about the transmitted code symbols when performing a given number of iterati is, the output of the third memory block is output iterative decoding of block turbocodes. SISO decoder includes a serially concatenated block decoding on the chase algorithm [3], the unit for computing the likelihood of a hypothetical code-word unit calculating a soft output decisions. The decoder implements a rule character of the reception signals based on block codes. This decoder contains serially connected blocks: block calculating the difference a posteriori symbol probabilities, the first and second blocks forming the analyzed sequence, the first driver signal coefficients of the Walsh functions, the first adder and the first subtraction unit, the computing unit functions of exponential type, the second driver signals of the coefficients of the Walsh functions, the changing unit marks the third block the formation of the analyzed sequence, a second adder, a third driver signals of the coefficients of the Walsh functions, the third adder, a second subtraction unit and the evaluation unit posteriori symbol probabilities.

The disadvantage of the described device is the complexity of its hardware implementation, which is determined by the complexity of SISO decoder. The disadvantage of this decoder is that it does not calculate a soft decision on re anaemic code, and the complexity of its implementation, due to the complexity of intermediate calculations when evaluating a posteriori symbol probabilities using three shapers signals of the coefficients of the Walsh function.

The prior art known to the device [4] iterative decoding of block turbocodes, partly overcoming the difficulty of performing SISO decoder and the SISO decoder that contains one United block decoding algorithm of the chase and the computing unit soft output values. This device contains three blocks of RAM, two adder, SISO decoder, the decision block and the schema normalization. The input device is the input of the first memory block, the output of which is connected to the first input of the first adder and to an inverted input of the second adder, the output of the first adder connected to the input of the SISO decoder, the output of which is connected to the first input of the second adder and the input of the decision block, the output of which is connected to the input of the third memory block, the output of the second adder connected to the input of the second memory block, the output of which is connected to the schema normalization, the output of which is connected with the second input of the first adder. SISO decoder includes serially concatenated block decoding algorithm for chase and soft computing unit in the initial values.

The disadvantage of this device iterative decoding of block turbocodes is low immunity in relation to potential noise immunity data turbocodes due to the use of sub-optimal decoding algorithm of the chase.

Known decoder [5] based on the algorithm Rudolf-Hartman. The device includes a memory block, the driver signals of the coefficients of the Walsh functions, the maximum detector signal shaper sign, clock, key, two counters, block bitwise multiplication, the unit's permanent memory, the parity block. The input of the maximum detector signal is connected to the first output of the driver signals of the coefficients of the Walsh function, an information input shaper sign connected to respective outputs of the block RAM, the outputs of the shaper signs connected with relevant information inputs of the driver signals of the coefficients of the Walsh functions, the second output of which is connected to the first input key, a second input connected to the generator output clock pulses, and the output connected to the input of the first counter, the first installation, the outputs of which are connected to respective address inputs of the memory block and the unit's permanent memory, other installation exit first is th counter is connected to the input of the second counter, with a synchronizing input of the shaper signal coefficients of the Walsh and the third input key, the first installation of the outputs of the second counter connected to respective first inputs of the block bitwise multiplication, the second input of which is connected to respective outputs of the unit's permanent memory, the output of the bitwise multiplication is connected to the input of the parity block, the output of which is connected with the control input of the shaper mark, setting the output of the second counter is connected to the fourth input key. The input of the block RAM is the input device, the output of maximum detector signal is output.

The disadvantage of this device is that it does not calculate a soft decision on the transmitted code symbols, and are calculated only binary (hard) decisions.

The technical result of the claimed invention (device iterative decoding of block turbocodes and SISO decoder for its implementation) is to increase the noise immunity of block turbocodes.

The technical result of the claimed invention device is achieved in that the device iterative decoding of block turbocodes contains the first, second and third blocks of RAM, SISO decoder, the decision block, the input of which is connected to the first choice of the output SISO decoder, and the output connected to the input of the third memory block whose output is the output device and the input device is the input of the first memory block, the device entered the block multiplication, the first and second limiters, the unit's permanent memory, and the output of the first memory block is connected to the input of the first limiter, the output of which is connected to the input of the unit's permanent memory, the output of which is connected to the first input of the multiplication, a second input connected to the output of the second memory block, and the output connected to the input of the second limiter, the output of which is connected to the input of the SISO decoder the second output of which is connected to the input of the second memory block.

SISO decoder device for iterative decoding of block turbocodes contains the memory block, the entrance of which is the entrance SISO decoder, connected in series, respectively, a clock generator, a key and a counter, the unit's permanent memory, the driver signals of the coefficients of the Walsh function, the address input of which is connected to the output of the meter, in the SISO decoder entered the shaper of the analyzed sequence, first, second and third adders, first and second blocks subtraction unit multiplied by two, block multiplication, the first, second and third blocks Affairs of the tion, the limiter, the output of the counter is connected to the address inputs of the memory block, the first output of which is connected to the input of the unit's permanent memory, the first output of which is connected to the input of the shaper of the analyzed sequence, the output of which is connected to the signal input of the shaper signals of the coefficients of the Walsh functions, the first shaper's output signals of the coefficients of the Walsh functions connected to the first input of the first adder with a first input of the first subtraction unit, and its second output is connected to the second input of the first adder, the second input of the first subtraction unit and the input block is multiplied by two, the output of the first subtraction unit connected to the first input the first unit, the output of the first adder connected to the first input of the multiplication, the second input and the second input of the first unit is connected to the second output of the unit's permanent memory, the output of the first unit connected to the first input of the second adder, a second input connected to the output of block multiplication, the output of the second adder connected to the first input of the second subtraction unit and to the first input of the third adder, a second input and a second input of the second subtraction unit is connected to the output of the block multiplied by two, the output of the second subtraction unit connected to the first input of the second bloodline, the second input is connected to the output of the third adder, the first output of the second unit is the first output of the SISO decoder, and its second output connected to the first input of the third unit, the second input is connected to the second output of the memory block, the output of the third unit is connected to the input of the limiter whose output is the second output of the SISO decoder, a second input key is a control input of the SISO decoder.

SISO decoder computes along with hard decisions and soft decisions based on the algorithm Rudolf-Hartman and can improve the noise immunity of block turbocodes.

The essence of the claimed group of inventions is illustrated by drawings showing the following:

Figure 1 - structure of block turbocodes, where

C_{1}C_{2}- components of block codes block turbo code.

Figure 2 - block diagram of the device iterative decoding of block turbocodes, where

1 is a first block of memory;

2 - the second memory block;

3 - the third memory block;

4 - SISO decoder;

5 - the decision block;

6 - the first limiter;

7 is a block permanent memory;

8 is a block multiplication;

9 - second bracket.

Figure 3 - block diagram of the SISO decoder device for iterative decoding of block turbocodes, where

10 - block is operativnoy memory;

11 - clock generator;

12 - key;

13 - counter;

14 - unit permanent memory;

15 - shaper signals of the coefficients of the Walsh functions;

16 - shaper of the analyzed sequence.

17 - the first adder;

18 - first subtraction unit;

19 is a block multiplied by two;

20 is a block multiplication;

21 - the first unit;

22 - the second adder;

23 - the third adder;

24 - second unit subtraction;

25 - second unit;

26 - the third unit;

27 - limiter;

28 - input decoder;

29, a control input of the SISO decoder;

30 - the first SISO decoder;

31 - second output SISO decoder.

4 is a block diagram of the driver of the analyzed sequence, where 32, 33, 34, 35, 36, 37, 38, 39 - the inputs of the driver of the analyzed sequence.

40, 41, 42, 43 blocks multiplying the first column of the block diagram;

44, 45, 46, 47, 48, 49, 50 - the fifteenth, sixteenth, seventeenth, eighteenth, nineteenth, twentieth, twenty first, twenty second, twenty third, twenty-fourth and twenty-fifth blocks multiplying the second column of the block diagram;

51, 52, 53, 54, 55, 56 - blocks multiplying the third column of the block diagram;

5 is a diagram of the basic element of a fast algorithm for spectral conversion in the Walsh basis with the operations of "addition-subtraction";

6 is a diagram of the basic element modificirovannogo is a fast algorithm for spectral conversion in the Walsh basis with the operation "multiplication".

The output of the first memory block 1 is connected to the input of the first limiter 6. The output of the first limiter 6 is connected to the input of the unit's permanent memory 7. The output of the unit's permanent memory 7 connected to the first input of block multiplication 8, the second input is connected to the output of the second memory block 2. The output of block multiplication 8 is connected to the input of the second limiter 9. The output of the second limiter 9 is connected to the input of the SISO decoder 4. The first output of the SISO decoder 4 is connected to the input of the decision block 5. The second output of the SISO decoder 4 is connected to the input of the second memory block 2. The output of the decision block 5 is connected to the input of the third memory block 3. The output of the third memory block 3 is the output iterative decoding of block turbocodes.

Entrance SISO decoder ("sign 28") is the input of the memory block 10. The output of the clock generator 11 is connected with the input key 12. The output of the key 12 is connected to the input of the counter 13. The output of counter 13 is connected to the address inputs of the memory block 10 and the driver signals of the coefficients of the Walsh function 15. The first output of the memory block 10 is connected to the input of the unit's permanent memory 14. The first output unit 14 is connected to the input of the shaper of the analyzed sequence 16. The output of driver 16 is connected to the signal is inym the inputs of the driver signals of the coefficients of the Walsh function 15. The first output of the driver 15 is connected to the first input of the first adder 17 and to the first input (reducing) of the first subtraction unit 18. The second output of the driver 15 is connected to a second input of the first adder 17, a second input (wichitaeagle) of the first subtraction unit 18 and to the input of block multiplication on two 19. The output of the first subtraction unit 18 connected to the first input (the dividend) of the first unit 2. The output of the first adder 17 is connected to the first input of the multiplication 20. The second input unit 20 and the second input (divisor) of the first unit 21 is connected to the second output of the unit's permanent memory 14. The output of the first unit 21 is connected to the first input of the second adder 22. The second input of the adder 22 is connected to the output unit 20 multiplication. The output of the adder 22 is connected to the first input (wichitaeagle) of the second subtraction unit 24 and to the first input of the third adder 23. The second input of the adder 23 is connected to the output of the block multiplied by two 19 and a second input (reducing) of the second subtraction unit 24. The output unit 24 connected to the first input (divisor) of the second unit 25. The second entrance (the dividend) unit 25 is connected to the output of the third adder 23. The first output of the second unit 25 is the first output 30 SISO decoder. The second output of the decoder is connected to the second input (the dividend) the third unit 26. Second input of the divider unit 26 soy is inen with the second output of the memory block 10. The output of the third unit 26 is connected to the input of the limiter 27. The output of the limiter 27 is the second output of the SISO decoder - exit 31". Input key 12 "log 29" is a control input of the SISO decoder.

The block diagram of the driver of the analyzed sequence 16 is shown in figure 4 for the special case of constituting the block Hamming code with parameters (7, 4), i.e. the amount of code words of the code is equal to 2^{4}(k=4), the length of code words is equal to n=7. The basis of the calculation procedure, which is implemented by the driver 16 in the preparation of the analyzed sequence is modified algorithm for fast spectral transformation in the basis of the Walsh-Hadamard transform with the basic operation of "multiplication". The original algorithm of the fast spectral transforms in the Walsh basis dimension 2^{l}(here l is a parameter of the algorithm spectral transformations) is a directed graph containing l columns, each column contains the 2^{l-1}the basic elements of operations "addition-subtraction".

Inputs 32, 33, 34, 35, 36, 37, 38, 39 shaper of the analyzed sequence 16 is connected to the respective signal outputs of the unit's permanent memory 14, the Block diagram contains three columns. The inputs of the multiplier units 40, 41, 42, 43 in the first column are connected respectively to 32 and 36, 33 and 37, 34 and 38, 35 and 39 signals is output to the inputs of the driver 16 of the analyzed sequence.

The inputs of block multiplication 44 in the second column are connected respectively to the output of block multiplication 40 and the output of block multiplication, 42.

The inputs of block multiplication 44 in the second column are connected respectively to the outputs of the multiplier units 40 and 42. The inputs of the multiplier units 45, 46, 47, 48, 49, 50 as part of the second column are connected respectively to 32 and 34, 33 and 35, 37 and 39, 32 and 38, 33 and 39, 35 and 37 of the signal inputs of the driver 16.

The inputs of the multiplier units 51, 52, 53, 54, 55, 56 in the third column are connected respectively to the output of the multiplier units 40 and 41, the output multiplier units 40 and 43, the output multiplier units 45 and 46, to the output of the multiplier units 45 and 47, the output multiplier units 48 and 49, the output multiplier units 48 and 50.

The outputs of multiplier units 44, 51, 52, 53, 54, 55, 56 are respectively the outputs 57, 58, 59, 60, 61, 62, 63 shaper 16 of the analyzed sequence.

In the General case, the driver 16 of the analyzed sequence contains blocks multiplication, which are located in the n-k columns. The first column contains the 2^{n-k-1}multiplier units, the column number i, 2≤i<n-k) contains the 2^{n-k+1}-2^{n-k-i+2}-1 multiplier units, (n-k)-th column contains n-1 blocks the multiplication.

We describe the procedure of iterative decoding, which is implemented in the proposed device when transmitting a sequence of code symbols*a*_{i
block turbo code (i=1, 2, ..., N).}

Getting started begins with an initialization phase is the input of the processed block count y_{i}(i=1, 2, ..., N)corresponding to the block turbo code.

After initialization is implemented by the specified number of iterations of the iterative decoding processing unit λ_{i}=exp(y_{i}). When performing the even-numbered iterations components are decoded codes C_{1}(horizontal codes), and calculates a soft decision for making codes C_{2}(vertical codes). When performing odd iterations are decoded constituent codes C_{2}(vertical codes), and calculates a soft decision for making codes C_{1}(horizontal codes).

Calculating soft decision^{(m+1)}(*a*_{i}=0), Pr^{(m+1)}(a_{i}=1) on the basis of processing the sequence of values

Here

Soft solutions

On the PE the howling iteration believe

On the subsequent (m+2)-th iteration is computed new soft solutions

When performing a set number t of iterations decisions: if Pr^{(t)}(*a*_{i}=0)>Pr^{(t)}(*a*_{i}=1), then*a*_{i}=0, otherwise*a*_{i}=1.

The device iterative decoding of block turbocodes that implements the above procedure works as follows.

The operation of the device begins after receipt discrete implementation of

In the first limiter 6 is a non-linear transformation of the values of y_{i}using a symmetric limiter level ±N_{1}with an area of linearity in order to reduce the dynamic range of the input values and increase the noise immunity of the device iterative decoding of block turbocodes - formed sequence of y_{i, Ogre}. The threshold value of P_{1}is stored in the block limits 6.

The unit's permanent memory 7 are calculated tabular method λ_{i}=exp(y_{i, Ogre}for values of y_{i, Ogre}.

In block multiplication 8 is the calculation of the values of_{i}coming from the output of the unit's permanent memory 7.

In the second limiter 9 is a non-linear transformation of the values of_{2}with an area of linearity in order to reduce the dynamic range of the input values and increase the noise immunity of the device iterative decoding of block turbocodes - formed samples_{2}stored in the second limiter 9.

The sequence of samples from the output of the second limiter 9

In the SISO decoder 4 are calculated soft decision*a*_{i}=0), Pr(*a*_{i}=1) and their relationships

In decision block 5 are calculated tough decisions: if*a*_{i}=0, otherwise*a*_{i}=1. Solutions come in the third block 3 RAM, his exit is the exit device exit.

Describe the work of the SISO decoder 4 for decoding a constituent block code with parameters (n, k). In the SISO decoder 4 are calculated soft decision

where

Here=

_{mi}; 0≤m<n-k; 0≤i<n) constituting the block of code;and^{n-k}-1), ν_{m}- the binary representation ν.

When calculating the values of F(h_{i}) (4) apply the algorithm quickly transformed the education in the Walsh basis with the basic operations of "addition-subtraction".
In the calculation of D_{ν}(5) apply the modified algorithm for rapid transformation in the Walsh basis with the basic operation of "multiplication".

Work SISO decoder begins after the receipt of the implementation of

The driver of the analyzed sequence 16 calculates the value Dν, ν=0, 1, ..., 2^{n-k}-1 (5)using the value of

In the imaging unit 16 is implemented modified algorithm for rapid transformation in the Walsh basis with the basic operation of "multiplication", the scheme of which is shown in Fig.6. The inputs 32-39 received input values. After you perform basic operations with the operation "multiplication" blocks the multiplication 40-56 on outputs 57-63 driver 16 receives the calculated values.

The driver signals of the coefficients of the Walsh function 15 computes the set is tion F(h_{
i}) (4) using the algorithm of the fast spectral transforms in the Walsh basis with the basic operations of "addition-subtraction using the analyzed sequence Dν, ν=0, 1, ..., 2^{n-k}-1 coming from the driver of the analyzed sequence 16.

Calculating soft decision_{i})stored in the driver signals of the coefficients of the Walsh function 15. When the key 12 is opened by signal "upwhat 29". The number of code symbols i (respectively address values_{i}in the driver signals of the coefficients of the Walsh function 15) are given by the counter 13, on which input through the key 12 receives the clock pulse generator 11. Values of

After calculating n values of the soft decision symbol probabilities and their relationship to the counter 13 is reset to zero state, and the key 12 is closed by a signal "upwhat 29". The calculation of these values is carried out in accordance with the expressions (3)to(5), using:

the first adder 17 and the first subtraction unit 18, which calculates the sum F(0)+F(h_{i}and the difference F(0)-F(h_{i}), the value F(0) is supplied from the first output driver signals of the coefficients of the Walsh function 15, and the values F(h_{W}) come from the second output driver signals of the coefficients of the Walsh function 15;

block multiplication on two 19 in which the calculated value of 2·F(0);

block multiplication 20 that calculates the value of_{W})) comes from the output of the first adder 17, a multiplier of

the first unit 21 that calculates the value of_{i})) from the output of the first subtraction unit 18, and the second input signal divider

the second adder 22, in which the calculated values of

the third adder 23 that calculates a posterior probability

the second subtraction unit 24 that calculates a posterior probability

the second unit 25, which are calculated odds ratios

the third unit 26 that calculates a soft decision

stop 27, which limits the calculated soft decision

By computer simulation shows that the proposed condition is the device and the decoder provides a coding gain of up to 2 dB (equivalent to improve noise immunity) in relation to the prototype, using the chase algorithm, for a communication channel with Rayleigh fading characters and additive white Gaussian noise.

Thus, the device and the decoder solves the problem of increasing noise immunity of block turbocodes by replacing the suboptimal algorithm chase when calculating soft decision optimal algorithm Hartman-Rudolf in the SISO decoder.

Sources of information

1. Works on information theory. Institute of electrical and electronics engineers. IEEE Transactions on Information Theory. 1996. V.IT-42. N2. P.429-448.

2. U.S. patent 7185259, IPC H03M 13/00, publ. 27.02.2007.

3. Works on information theory. Institute of electrical and electronics engineers. IEEE Transactions on Information Theory, 1972, Vol.IT-18, pp.170-182.

4. Patent for useful model №79361, H03M 13/29 from 01.02.2007 (prototype).

5. Copyright certificate 1372344, CL G08C 19/18 (prototype), publ. 07.02.88.

6. Works on information theory. Institute of electrical and electronics engineers. IEEE Transactions on Information Theory. 1976. V.IT-22. N5. P.514-517.

1. The device iterative decoding of block turbocodes, containing the first, second and third blocks of RAM, SISO decoder, the decision block, the inlet of which is connected to the first output of the SISO decoder, and the output connected to the input of the third memory block whose output is the output device and the input device is the input Pervov the block RAM, characterized in that it introduced the block multiplication, the first and second limiters, the unit's permanent memory, and the output of the first memory block is connected to the input of the first limiter, the output of which is connected to the input of the unit's permanent memory, the output of which is connected to the first input of the multiplication, a second input connected to the output of the second memory block, and the output connected to the input of the second limiter, the output of which is connected to the input of the SISO decoder, the second output of which is connected to the input of the second memory block.

2. The device according to claim 1, wherein the SISO decoder contains a block of memory, clock generator, key counter, the unit's permanent memory, the driver signals of the coefficients of the Walsh functions, the driver of the analyzed sequence, the first adder, the first subtraction unit, the unit multiplied by two, block multiplication, the first unit, a second adder, a third adder, a second subtraction unit, a second unit, the third unit, the limiter, the input of the block RAM is the entrance SISO decoder, connected in series, respectively, the clock key and the counter output of the counter connected to the address the input of the shaper signals of the coefficients of the Walsh functions, the output of the counter is connected to the address inputs of the Loka RAM, the first output of which is connected to the input of the unit's permanent memory, the first output of which is connected to the input of the shaper of the analyzed sequence, the output of which is connected to the signal input of the shaper signals of the coefficients of the Walsh functions, the first shaper's output signals of the coefficients of the Walsh functions connected to the first input of the first adder with a first input of the first subtraction unit, and its second output is connected to the second input of the first adder, the second input of the first subtraction unit and the input block is multiplied by two, the output of the first subtraction unit connected to the first input of the first unit, the output of the first adder connected to the first input of block multiplication, the second input and the second input of the first unit is connected to the second output of the unit's permanent memory, the output of the first unit connected to the first input of the second adder, a second input connected to the output of block multiplication, the output of the second adder connected to the first input of the second subtraction unit and to the first input of the third adder, a second input and a second input of the second subtraction unit is connected to the output of the block multiplied by two, the output of the second subtraction unit is connected to the first input of the second unit, the second input is connected to the output of the third adder, the first output of the second BL is ka division is the first output of the SISO decoder, and its second output connected to the first input of the third unit, the second input is connected to the second output of the memory block, the output of the third unit is connected to the input of the limiter whose output is the second output of the SISO decoder, a second input key is a control input of the SISO decoder.

3. SISO decoder device for iterative decoding of block turbocodes containing the memory block, the entrance of which is the entrance SISO decoder, connected in series, respectively, a clock generator, a key and a counter, the unit's permanent memory, the driver signals of the coefficients of the Walsh function, the address input of which is connected to the output of the counter, characterized in that it introduced the shaper of the analyzed sequence, first, second and third adders, first and second blocks subtraction unit multiplied by two, block multiplication, the first, second and third blocks division, limiter, and the output of the counter is connected to the address inputs of the block RAM, the first output of which is connected to the input of the unit's permanent memory, the first output of which is connected to the input of the shaper of the analyzed sequence, the output of which is connected to the signal input of the shaper signals of the coefficients of the Walsh functions, the first output driver signals coeff the patients Walsh functions connected to the first input of the first adder with a first input of the first subtraction unit, and its second output is connected to the second input of the first adder, the second input of the first subtraction unit and the input block is multiplied by two, the output of the first subtraction unit connected to the first input of the first unit, the output of the first adder connected to the first input of the multiplication, the second input and the second input of the first unit is connected to the second output of the unit's permanent memory, the output of the first unit connected to the first input of the second adder, a second input connected to the output of block multiplication, the output of the second adder connected to the first input of the second subtraction unit and to the first input of the third adder the second input and the second input of the second subtraction unit is connected to the output of the block multiplied by two, the output of the second subtraction unit is connected to the first input of the second unit, the second input is connected to the output of the third adder, the first output of the second unit is the first output of the SISO decoder, and its second output connected to the first input of the third unit, the second input is connected to the second output of the memory block, the output of the third unit is connected to the input of the limiter whose output is the second output of the SISO decoder, a second input key is a control input of the SISO decoder.

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5 cl, 7 dwg

FIELD: radio engineering, communication.

SUBSTANCE: receiving apparatus, which corresponds to the digital television standard T.2, known as DVB-T2, is configured to perform low-density parity-check (LDPC) decoding for physical layer channels (PLC), which denote data streams, and layer 1 (L1), which represents physical layer transmission parameters. The receiving apparatus includes a LDPC decoding apparatus which is configured such that, when a LDPC encoded data signal and a LDPC encoded transmission control signal are transmitted multiplexed, said LDPC decoding apparatus decodes both the data signal and the transmission control signal. The receiving apparatus also includes a storage device configured to be placed in front of the LDPC decoding device and to store the transmission control signal when receiving the data signal and the transmission control signal.

EFFECT: enabling simultaneous reception of data and control signals using the same apparatus.

4 cl, 12 dwg

FIELD: radio engineering, communication.

SUBSTANCE: receiving apparatus, which corresponds to the digital television standard T.2, known as DVB-T2, is configured to perform low-density parity-check (LDPC) decoding for physical layer channels (PLC), which denote data streams, and layer 1 (L1), which represents physical layer transmission parameters. The receiving apparatus includes a LDPC decoding apparatus which is configured such that, when a LDPC encoded data signal and a LDPC encoded transmission control signal are transmitted multiplexed, said LDPC decoding apparatus decodes both the data signal and the transmission control signal. The receiving apparatus also includes a storage device configured to be placed in front of the LDPC decoding device and to store the transmission control signal when receiving the data signal and the transmission control signal.

EFFECT: enabling simultaneous reception of data and control signals using the same apparatus.

4 cl, 12 dwg

FIELD: radio engineering, communication.

SUBSTANCE: method of generating codes for generating signal ensembles involves generating a source code of N≥4 elements, a number K≥1 of codes of N elements to be generated, as well as a target function for a set of L states of the code elements, and corresponding values of given signal parameters, characterised by an array of states of L×N×K peaks on N×K levels, connected by edges, wherein each of the L states is the initial state; generating codes; selecting a path with the extremum value of the target function, after which each generated code is assigned a symbol which corresponds to the edge of the path with the extremum value of the target function, and selecting 2≤M≤K codes with the maximum value of the ratio of the amplitude of the central peak of the autocorrelation function to the magnitude of the amplitude of the maximum lateral peak of the autocorrelation function and the minimum duration of the section of the autocorrelation function between the point of the maximum of the central peak and the point where the autocorrelation function becomes zero for the first time.

EFFECT: high jamming resistance of signals generated based on corresponding codes.

5 cl, 7 dwg

FIELD: information technology.

SUBSTANCE: intra prediction modes are coded in a bit stream. Brightness and chroma components can potentially have different prediction modes. For chroma components, there are 5 different modes defined in AVC: vertical, horizontal, DC, diagonal down right, and "same as brightness". Statistics show that the "same as brightness" mode is frequently used, but in AVC, this mode is encoded using more bits than other modes during entropy coding, therefore the coding efficiency is decreased. Accordingly, a modified binarisation/codeword assignment for chroma intra mode signalling can be used for high efficiency video coding (HEVC), the next generation video coding standard.

EFFECT: high coding efficiency.

18 cl, 4 dwg

FIELD: information technology.

SUBSTANCE: transmitting device comprises: means of generating frames, which is configured to arrange signal and pilot signal data in each of at least two signal code combinations in a frame, each signal code combination having the same length, and arrange data in said at least one code combination in a frame, a conversion means which is configured to convert said signal code combinations and said data code combinations from a frequency domain into a time domain to generate a time-domain transmission signal, and a transmitting means which is configured to transmit said time-domain transmission signal. Method is intended to be implemented by the given device.

EFFECT: enabling flexible tuning to the required portion of the transmission band and reduced content of service data.

20 cl, 15 dwg

FIELD: radio engineering, communication.

SUBSTANCE: apparatus for decoding block turbo codes has a first random-access memory unit 1, a second random-access memory unit 2, a third random-access memory unit 3, a SISO decoder 4, a decision unit 5, a first limiter 6, a read-only memory unit 7, a multiplier unit 8, a second limiter 9. The SISO decoder has a random-access memory unit 10, a clock generator 11, a switch 12, a counter 13, a read-only memory unit 14, a Walsh function coefficient signal former 15, an analysed sequence former 16, a first adder 17, a first subtractor unit 18, a doubling unit 19, a multiplier unit 20, a first divider unit 21, a second adder 22, a third adder 23, a second subtractor unit 24, a second divider unit 25, a third divider unit 26, a limiter 27.

EFFECT: high noise immunity of block turbo codes.

3 cl, 6 dwg

FIELD: radio engineering, communication.

SUBSTANCE: method of transmitting information bits includes a step of dividing the information bits to be transmitted into at least two groups. Further, according to the method, the information bits in each group to be transmitted are encoded to obtain at least two groups of encoded bits. Said at least two groups of encoded bits are combined to obtain a full sequence of encoded bits. The full sequence of encoded bits is obtained by dividing the encoded bits in each group into N subgroups and reordering said subgroups in each group of encoded bits. Subgroups in at least one group of the encoded bits are discontinuously distributed in the full sequence of encoded bits after reordering.

EFFECT: improved reception quality.

16 cl, 9 dwg, 2 tbl

FIELD: information technology.

SUBSTANCE: input signal is converted to spectral coefficients; the spectral coefficients are grouped into frequency bands and standards are estimated for each band as the average energy in the band; the spectrum is normalised based on the estimated standards; the standards are weighted based on psycho-acoustic properties of sound; bit distribution is calculated based on the weighted standards; the spectrum is quantised and encoded by the obtained number of bits; the method is characterised by that bit distribution is calculated based on a psycho-acoustic model built on quantised standards. Also disclosed is a device for implementing this method.

EFFECT: low level of distortions and easier encoding.

26 cl, 15 dwg

FIELD: radio engineering, communication.

SUBSTANCE: information 1 consisting of five pulses is encoded in form of a series of one positive pulse, two positive pulses, each magnified N times, one negative pulse magnified N times and one positive pulse, and an information 0 consisting of five pulses is encoded in form of a series of one negative pulse, two negative pulses, each magnified N times, one positive pulse magnified N times and one negative pulse, wherein N is a positive number greater than 1; the obtained sequences are transmitted to a data transmitting medium, and the received signal is compared with a reference signal by cross-correlation at the receiving side.

EFFECT: obtaining a clear signal with high level of interference and longer range of signal transmission.

2 cl, 5 dwg

FIELD: radio engineering, communication.

SUBSTANCE: invention relates to a coding method in a wireless mobile communication system. More specifically, the present invention relates to a convolutional turbo coding (CTC) method and a device for implementing the method. The method for CTC includes steps of encoding information bits A and B using a constituent encoder, and outputting parity sequences Y_{1} and W_{1}, interleaving the information bits A and B using a CTC interleaver to obtain information bits C and D, and encoding the interleaved information bits C and D using the constituent encoder to obtain parity sequences Y_{2} and W_{2}, interleaving the information bits A and B, the parity sequences Y_{1} and W_{1} and the parity sequences Y_{2} and W_{2}, respectively, wherein the bits in at least one of a bit group consisting of the information bits A and B, a bit group consisting of the sequences Y_{1 }and W_{1}, and a bit group consisting of the sequences Y_{2} and W_{2} are alternately mapped to bits of constellation points with high reliability and low reliability and puncturing the interleaving result to obtain the encoded bit sequences.

EFFECT: high reliability of encoding with bit mapping of high order modulation.

12 cl, 7 dwg

FIELD: radio engineering, communication.

SUBSTANCE: method of decoding convolutional codes involves receiving radio signals, automatic gain control, demodulation, first deinterleaving, Viterbi algorithm decoding, amplitude detection, averaging, second deinterleaving, nonlinear conversion and multichannel multiplication-summation.

EFFECT: low error probability when decoding and high noise-immunity of transmitted information.

7 dwg