# Device for simulating process of choosing commodity

FIELD: information technology.

SUBSTANCE: device for simulating the process of choosing a commodity has an array of m*n first registers, second registers whose number equals the number of rows of the array, adders whose number equals the number of rows of the array, AND element units whose number equals the number of rows of the array, third and fourth registers whose number equals the number of columns of the array, an array of m*n divider units, an array of multiplier units, a unit of OR elements, a maximum code selecting unit, a decoder, four delay elements and a flip-flop.

EFFECT: broader functional capabilities by providing selection of the best version of a commodity based on given consumer criteria.

1 dwg

The invention relates to the field of computer engineering and can be used to obtain exact solutions of the problem of selection of goods. The purpose of the invention is to enhance the functionality of the device.

The device comprises: a matrix of registers 1i,j(i=1...m, j=1...n), the matrix blocks division 2i,jthe matrix multiplier units 3i,jaccording to the number of columns of the matrix registers 4jand registers 5j(j=1...n), no the number of rows of the matrix registers 6i(i=1...m), blocks of elements And 7i(i=1...m), the adders 8i(i=1...m), the block elements OR 9, the block selection maximum code 10, a decoder 11, the delay elements 12, 13, 14, 15, the trigger 16, the inlet 17, the outputs 18, 19 and 20 together with ties.

The device operation is based on the transformation of the original data set of goods and the choice of them preferred.

The essence of the problem is the following. There are m identical goods with known n characteristics qj(j=1...n) and their reference values of q0j. Also known weights αj, (j=1, ..., n) the importance of the product for a particular consumer. Then measure the competitiveness of each product in relation to the selected reference for the j-th quality is defined as Qj=qj/q0jand for all goods, these figures will be described by the matrix Qm*n.

So about what atom, you can set the Ki- level of competitiveness of the i-th commodity (i=1...m),

$Ki=∑j=1nαjQij$

Consumer choice in this case is to maximize the integral indicator of the competitiveness of the Kii.e. the customer will choose the product with

$maxiKi$.

Known devices for similar modeling [1], which allow to determine the best option on other criteria.

The closest to the technical nature of the claimed device is a device for simulation [1], containing a matrix of m*n of the first registers 1i,j(i=1...m, j=1...n), the number of rows of the second matrix registers 6i(i=1...m), the number of rows of the matrix adders 8i(i=1...m), the number of rows of the matrix blocks of elements And 7i(i=1...m), no the number of columns of the matrix third registers 4j, (j=1...n), the fourth registers 5j, (j=1...n), the output of each second register 6i(i=1...m) is connected to the first input of the block elements And 7i.

The disadvantage of this condition the device is the inability of the simulation to choose the best product for the specified user criteria.

The objective of the invention is to create a device that provides simulation of choosing the best alternative goods by the specified user criteria.

The invention consists in that the device for simulation of the process of selection of goods containing a matrix of m*n of the first registers 1i,j(i=1...m, j=1...n), the number of rows of the second matrix registers 6i(i=1...m), the number of rows of the matrix adders 8i(i=1...m), the number of rows of the matrix blocks of elements And7i(i=1...m), the number of columns of the matrix third registers 4j, (j=1...n), the fourth registers 5j, (j=1...n), the output of each second register 6i(i=1...m) is connected to the first input of the block elements And 7ientered the matrix m*n blocks of division 2i,l(i=1...m, j=1...n), the matrix block multiplication 3i,j(i=1...m, j=1...n), the block elements OR 9, the block selection maximum code 10, a decoder 11, the first delay element 12, the second delay element 13, the third delay element 14, the fourth delay element 15, the trigger 16, the output of which is output 18, and the input connected to the output of the fourth delay element 15, the trigger input 17 is connected to the input of the first delay element 12 and to the control inputs of blocks dividing 2i,j(i=1...m, j=1...n), the second input of each of which is connected to the same output of the first register 1i,j(i=1...m, j=1...n), and the third input to the output of the same name is otwartego register 5 j, (j=1...n), the output of the first delay element 12 is connected to the input of the second delay element 13 and to the control inputs of the multiplier units 3i,j(i=1...m, j=1...n), the second input of each of which is connected to the output of the same block division 2i,j(i=1...m, j=1...n), and the third input to the same output of the third register 4j, (j=1...n), the output of the second delay element 13 is connected to the input of the third delay element 14 and to the control inputs of the adders 8i(i=1...m), the second input of which is connected to the outputs of the same multiplier units 3i,j(i=1...m, j=1...n), and outputs connected to the same inputs of the block select max (code 10), the output of the third delay element 14 is connected to the input of the fourth delay element 15 and to the control input of the block selecting maximum code 10, the first output of which is an output device 20, and the second output to the input of the decoder 11, the outputs of which are connected to the same control inputs of blocks of elements And 7i(i=1...m), the outputs of which are connected to the same inputs of block elements OR 9 whose output is the output 19 of the device

Conducted search in well-known scientific and technical literature did not reveal the presence of such technical solutions.

The novelty of the proposed device is that a new technical device differs from the prototype is the fact that additionally it introduced the matrix m*n blocks of division 2i,j(i=1...m, j=1...n), the matrix block multiplication 3i,j(i=1...m, j=1...n), the block elements OR 9, the block selection maximum code 10, a decoder 11, the first delay element 12, the second delay element 13, the third delay element 14, the fourth delay element 15, the trigger 16, the output of which is output 18, and the input connected to the output of the fourth delay element 15, the trigger input 17 is connected to the input of the first delay element 12 and to the control inputs of blocks dividing 2i,j(i=1...m, j=1...m), the second input of each of which is connected to the same output of the first register 1i,j(i=1...m, j=1...n), and the third input to the same output of the fourth register 5j, (j=1...n), the output of the first delay element 12 is connected to the input of the second delay element 13 and to the control inputs of the multiplier units 3i,j(i=1...m, j=1...n), the second input of each of which is connected to the output of the same block division 2i,j(i=1...m, j=1...n), and the third input to the same output of the third register 4j, (j=1...n), the output of the second delay element 13 is connected to the input of the third delay element 14 and to the control inputs of the adders 8i(i=1...m), the second input of which is connected to the outputs of the same multiplier units 3i,j(i=1...m, j=1...n), and outputs connected to the same inputs of the block you the ora maximum code 10, the output of the third delay element 14 is connected to the input of the fourth delay element 15 and to the control input of the block selecting maximum code 10, the first output of which is an output device 20, and the second output to the input of the decoder 11, the outputs of which are connected to the same control inputs of blocks of elements And 7i(i=1...m), the outputs of which are connected to the same inputs of block elements OR 9 whose output is the output 19 of the device

Inventive step is achieved by entering the corresponding elements in the known prototype together with relationships allows us to solve the new technical problem, the solution of which is known in the computers and in the literature does not currently reflected. The proposed device allows you to extend the functionality of the device.

The invention is illustrated in the drawing. The drawing shows a structural diagram of the device, where the matrix registers 1i,j(i=1...m, j=1...n), the matrix blocks division 2i,jthe matrix multiplier units 3i,jaccording to the number of columns of the matrix registers 4jand registers 5j(j=1...n), the number of rows of the matrix registers 6i(i=1...m), blocks of elements And 7i(i=1...m), the adders 8i(i=1...m), the block elements OR 9, the block selection maximum code 10, a decoder 11, the delay elements 12, 13, 14, 15, Tr is gger 16, input 17, the outputs 18, 19 and 20 together with ties.

The device operates as follows.

In the initial state of the registers 1i,j(i=1...m, j=1...n) are stored j-s indicators of the quality of the i-th commodity in the registers 4jkept the weights the importance of the j-th indicator of quality from the point of view of the consumer goods. On the registers 5j(j=1...n) stored reference estimate (j-s indicators of product quality. On the registers 6i(i=1...m) is stored codes analyzed goods. The trigger 16 is zero (reset) state, and its output 18 is zero signal.

The device starts after the signal START input device 17, and then in blocks of division 2i,j(i=1...m, j=1...n) is a division of the contents of register 1i,j(i=1...m, j=1...n) on the contents of register 5j(j=1...n). At the same time trigger input signal 17 is fed to the input of delay element 12, which delays the signal for a time t12equal to the time reliable operation of the unit 2i,j(i=1...m, j=1...n).

The output signal from the delay element 12 to the input of the delay element 13 and the control inputs of multiplier units 3i,j(i=1...m, j=1...n), where the multiplication of the content block division 2i,j(i=1...m, j=1...n) the designation of the contents of register 4j(j=1...n).

The result with the output of each block multiplication 3i,j(i=1 is m, j=1...n) is fed to the same input of the adder 8i(i=1...m), the control input of which receives an enable signal from the output of the delay element 13, which delays the signal for a time t13equal to the time reliable operation of block multiplication 3i,j(i=1...m, j=1...n).

Codes from the output of the adders 8i(i=1...m) are fed to corresponding inputs of the block select max (code 10), which provides the maximum choice code group received and the sequence number. On the control input unit 10 receives the signal from the output of the delay element 14, which delays the signal for a time t14equal to the time reliable operation of the adder 8i(i=1...m).

The sequence number of the maximum code output unit 10 to the input of the decoder 11, the outputs of which are fed to corresponding inputs of blocks of elements And 7i(i=1...m), with output codes which are received on the corresponding inputs of block elements OR 9, the output 19 which there is a code of best product.

Simultaneously, the outputs of the delay elements 15, which delays the signal for a time t14equal to the time reliable operation of the unit 10, is supplied on the installation in one state, the input of the trigger 16, the output 18 of which appears to signal the end of the operation.

The proposed device for the simulation of the electoral process is as goods as part of elements 1-16 (see 1) can be based on standard chips produced by the domestic industry, the block 10 select the maximum code can be implemented by known a Device for determining extreme code presented in [2].

1. AC No. 22920081 CL G06F 12/14, 2005.

2. AC No. 997028 CL G06F 7/04, 1983.

Device to simulate the process of selecting the product, containing a matrix of m·n of the first registers 1i,j(i=1...m, j=1...n), no the number of rows of the second matrix registers 6i(i=1...m), the number of rows of the matrix adders 8i(i=1...m), the number of rows of the matrix blocks of elements And 7i(i=1...m), no the number of columns of the matrix third registers 4j, (j=1...n), the fourth registers 5j, (j=1...n), the output of each second register 6i(i=1...m) is connected to the first input of the block elements And 7i, characterized in that it introduced the matrix m·n blocks of division 2i,j(i=1...m, j=1...n), the matrix block multiplication 3i,j(i=1...m, j=1...n), the block elements OR 9, the block selection maximum code 10, a decoder 11, the first delay element 12, the second delay element 13, the third delay element 14, the fourth delay element 15, the trigger 16, the output of which is output 18, and the input connected to the output of the fourth delay element 15, the trigger input 17 is connected to the input of the first delay element 12 and to the control inputs of blocks dividing 2i,j (i=1...m, j=1...n), the second input of each of which is connected to the same output of the first register 1i,j(i=1...m, j=1...n), and the third input to the same output of the fourth register 5j, (j=1...n), the output of the first delay element 12 is connected to the input of the second delay element 13 and to the control inputs of the multiplier units 3i,j(i=1...m, j=1...n), the second input of each of which is connected to the output of the same block division 2i,j(i=1...m, j=1...n), and the third input to the same output of the third register 4j, (j=1...n), the output of the second delay element 13 is connected to the input of the third delay element 14 and to the control inputs of the adders 8i(i=1...m), the second input of which is connected to the outputs of the same multiplier units 3i,j(i=1...m, j=1...n), and outputs connected to the same inputs of the block select max (code 10), the output of the third delay element 14 is connected to the input of the fourth delay element 15 and to the control input of the block selecting maximum code 10, the first output of which is an output device 20, and the second output to the input of the decoder 11, the outputs of which are connected to the same control inputs of blocks of elements And 7i(i=1...m), the outputs of which are connected to the same inputs of block elements OR 9 whose output is the output device 19.

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