Decoding device with soft decisions for double-stage cascade code

FIELD: radio engineering, communications.

SUBSTANCE: device comprises a correction device, a circuit of bit quality identification, a demodulator, a circuit of symbol quality detection and selection of least valid symbols, a circuit of code cycle synchronisation with integrated soft and hard decisions, a circuit of error vectors generation for least valid symbols, a unit of summators by module two, a unit of decoders of a BCH code, a circuit for detection of least weight, a controller of PC code decoder.

EFFECT: increased validity of information reception in channels with high level of noise.

1 dwg

 

The invention relates to systems for the transmission of discrete data and can be used in systems robust data protection.

When developing a decoding device, an urgent task is to increase the reliability of the received information in the communication channels with high noise level.

The use of soft decision decoding of error-correcting code provides additional information to increase the reliability of the received information.

Based soft decoding are two optimal rules. One of them consists in selecting the codeword with the minimum distance to the received sequence. This rule is the minimum probability of error in the sequence, and implements its decoder is a maximum likelihood decoder.

Another rule is the decoding of each symbol of the code word with the minimization of the average error probability of the symbol.

Each rule can be accurately implemented only for a very short codes. Currently, methods for soft decoding of longer codes represent attempts to approximate one of the above rules.

A device decoding with soft decision (prototype)that contains the schema of the selection of the least reliable symbol and diagram of the calculation of the syndrome, the outputs of which clicks the form address for the search schema for the table since the output of which is a vector of the most likely error is supplied to one of inputs of the adder, the other input of the adder receives the vector code words after the hard decision for each symbol at the output of the adder is formed codeword with the minimum code distance to the received sequence [Glark, Jan. Encoding with error correction in digital communication systems. Moscow, Radio I Svyaz" 1987, str-165, RIS].

Such a device has poor performance, as it requires a sequential iterative process when calculating the codeword closest to the received sequence.

A similar disadvantage has a circuit implementing the algorithm of the chase, Type II [Rmorales-Zaragoza. The art of error correcting coding. Methods, algorithms, applications. Moscow, Technosphere, 2006, str-213, RIS].

The purpose of the invention is improving the performance of the decoding device and improving the reliability of the received information.

To achieve the goal of the proposed decoder with soft decision for a two-stage cascade code containing a corrective device, the input INF which information is input and the input of which is clocked by the input device, one of the outputs of the correction device is connected to the input of the differential opredeleniya bits another output of the correction device is connected to the input of the demodulator, one of the outputs of the demodulator is connected to one of inputs of the circuit determine the quality of the characters and the selection of the least reliable symbols, the other input of which is connected to the output of the circuit determine the quality of the bits, the output of the circuit determine the quality of the characters and the selection of the least reliable symbols connected to one of inputs of scheme code frame synchronization with integrated soft and hard decisions, the other input of which is connected to the output of the demodulator outputs Q1QU, CBCH, SR scheme code frame synchronization with integrated soft and hard solutions are connected with inputs of the formation pattern of the error vectors for the least reliable symbols the output of the circuit forming the error vectors for the least reliable symbols connected to one of inputs of unit adders modulo two, and the other input of the adders modulo two is connected to the output DBCH scheme code frame synchronization with integrated soft and hard decisions, and the outputs of the unit adders modulo two is connected to the inputs D1-D8 block of code decoders Bose-Roy-Chaudhury-Hocquenghem (BCH), which contains eight decoders for BCH code, other inputs CBCH, SR, EWR, WRRG block decoder BCH code are connected by BUS with CL output schema code frame synchronization with integrated the mi soft and hard decisions, outputs WBCH0-WBCH8 decoder BCH code are connected with inputs of the circuit determine the lowest weight, input quality characters Q0QU which is connected to the circuit output coded frame synchronization with integrated soft and hard decisions, outputs control signals SSN and WRRG which is connected by BUS with CL inputs of the circuit determine the lowest weight, and outputs the permission E1-E8 which are connected with inputs of block decoders BCH code, the outputs WZBCH1-WZBCH8 and OZER1-OZER8 which is connected to the input Ports IN controller code decoder PC inputs interrupt INT1, INT2, INT3 which bus BUS CL connected to the outputs for signals MO and SR scheme code frame synchronization with integrated soft and hard decisions, the outputs d0-d4 which are connected with inputs of controller decoder reed-Solomon code (PC), the output of which is OUT Ports is an information output device.

What's new is that in the device to improve its performance and reliability of the received information entered scheme code frame synchronization with integrated soft and hard decisions, the pattern of formation of the error vectors for the least reliable symbols, a block of adders modulo two, the block decoder BCH code, diagram to determine the lowest weight and the controller code decoder PC to ensure the use of soft decisions, as well as parallel is Yu and pipelining for calculations.

The drawing shows a structural diagram of the device.

The device decoding with soft decision for a two-stage cascade code contains the correction device 1, the detection circuit quality bits 2, the schema definition quality characters and choose the least reliable symbols 3, a demodulator 4, a diagram of a coded frame synchronization with integrated soft and hard solutions 5, a diagram of the formation of the error vectors for the least reliable symbols 6, block adders modulo two 7, the block decoder BCH code 8, consisting of eight BCH decoders 9, 10, 11, scheme determine the lowest weight 12, the controller code decoder PC 13.

The device operates as follows.

On the transmission side as the output information is formed by a sequence of c1⊕c2i⊕c3nrepresenting the bitwise sum modulo two of the three sequences: sequence internal binary cascade code c1synchronizing the binary sequence c2i=c21c22c23...c2nand the sequence c3n=c3c3c3...c3violating the cyclical properties of the source and consisting of repeating cyclic sequences, where n is the number of words BCH code.

To obtain the sequence c on the transmitting side of the original information amount k m-ary (m>1) characters encoded m-ary error-correcting code, such as m-ary error-correcting code PC. Code PC is the external code or code first-stage robust cascade code.

As a result of such encoding the original information is a block of code words PC (n, k), the information length k is equal to the word PC and block - n characters.

The next block of information consisting of words PC, encoded binary code, such as binary BCH code with the check polynomial h1(x). Code BCH is an internal code or code of the second stage of error-correcting cascade code. The word BCH code has the following parameters: n1- block code length, k1information code length. A coding unit of the words PC code BCH receive a block of n binary words BCH code (n1, k1), which is a sequence of c1.

Then the BCH code word are summed modulo two with a synchronizing sequence c2i. As a synchronizing sequence is chosen binary code with block length n1and information length of k2for example code, reed-Muller (RM) first order (sequence maximum period) with the check polynomial h2(x). Information length of k2 code RM corresponds to the binary representation of numbers, words BCH. Between the numbers of words in concatenated BCH code and an information part of the synchronizing sequence is set one-to-one correspondence. The first word BCH is added modulo two and a sequence obtained by encoding a binary write of the first number of words BCH code of the Republic of Moldova, the second word BCH is added modulo two and a sequence obtained by encoding a binary write of the second number word BCH code of the Republic of Moldova and so on. This operation is the summation runs over all words BCH code.

If the check polynomial h1(x) and h2(x) is summable BCH codes and the Republic of Moldova and are coprime divisors of binomial xn1+1, the resulting sum will be obtained n words cyclic BCH code with length n1and information length of k1+k2. This code will correct errors, including

e≤r/log2(n1+1),

where r=n1-k1-k2- the number of check symbols of the code.

The third sequence c3with which words are added BCH, will be a constant sequence of length n1bits for all words. Such a sequence may be any sequence that is not a code word BCH code, for example a sequence of 10000...000.

In real channels and interference, which can be viewed as a sequence of c4the presence of units which corresponds to the placement of misspelled words. For correct word sequence c4contains only zeros.

Information in the form of a sequence with1⊕c2i⊕c3n⊕c4formed of four sequences and, if necessary, modulated, is supplied to the information input device in the correction device 1. The correction device 1 is designed to synchronize bits of information with frequency of use and restoration of the form these bits when possible distortions.

Option correctional device with the structural diagram and a description of the operation given in the source [Whirlpoolsex. Basic techniques of transmission of discrete messages. M: "Link", 1973, s, is].

Corrective device using integrators restores the original form of digital bits and accompanies every bit of the gate.

Definition schema quality bits 2 through integrator registers bit metric values. Justification of the choice of metric values given in [Yourmachine, Sairusi. The device decoding with soft decision for a two-stage cascade code. // Proceedings of IX all-Russian scientific-technical conference "New inform the information technology systems of communication and control". Kaluga, 2010. S.353-369]. With the output of the circuit determine the quality bit 2 signals are sent to one of the inputs of the circuit determine the quality of the characters and the selection of the least reliable symbols 3 and the other input of this circuit from the output of the demodulator comes strobe boundaries for each character. When the modulation signal, for example, to interface S1-FL GOST 27232-87, each symbol has a duration of two bits, so the probability of errors in them can be considered as the sum of the two metrics.

Table metrics, the least reliable symbols and option schemes determine the quality of the characters and the selection of the least reliable symbols are given in [Yourmachine, Sairusi. The device decoding with soft decision for a two-stage cascade code. // Proceedings of IX all-Russian scientific-technical conference "New information technologies in communication and control systems". Kaluga, 2010. S.353-369].

The adder determines the metric value of the symbol corresponding to two bits, and decoders - the presence of at least one bit with a metric of 0 or 1. The gate from the output of the demodulator is fixed, the sum of the metrics for each symbol, and the presence or absence of the sign of the least reliable symbol. From the information output of the demodulator 4 and the output of the circuit determine the quality of the characters and the selection of the least reliable symbols 3 digital signals, which is adequate to the characters and their metrics come in scheme code frame synchronization with integrated soft and hard solutions 5, which is designed to define the boundaries of blocks of information.

Circuit description code frame synchronization with integrated soft and hard solutions given in the application [Device code frame synchronization with integrated soft and hard solutions. Application No. 2011107040, priority 24.02.2011,].

A sequence of characters and their quality are recorded in the drive information. Structural diagram of an information storage shown in Fig.3 in [Yourmachine, Sairusi. The device decoding with soft decision for a two-stage cascade code. // Proceedings of IX all-Russian scientific-technical conference "New information technologies in communication and control systems" Kaluga, 2010. S.353-369].

To remove the words BCH sequences c2iand c3nin this scheme introduced adders and registers with polynomials X5+X2+1 and X5+X4+X2+X+1, and for fixation of rooms these words d0-d4, use the register storage rooms. In the drive information sequence is recorded in one of the two RAM until it is determined the end of a data block, then the control circuit of the drive will begin recording the follow-up information in another RAM, and from the previous RAM beg the em reading of information for further operations for processing and decoding. The use of storage media that contains two RAM allows you to apply a strip method of processing data, providing simultaneous recording and reading information from an information storage that improves performance of the device. From the output of the adder information as a sequence of c1⊕c4through the exit DBCH scheme code frame synchronization with integrated soft and hard solutions 5 is supplied to one of inputs of unit adders modulo two 7, and the other input receives the error vectors with the output of the circuit forming the error vectors for the least reliable symbols 6.

Option scheme of the formation of the error vectors for the least reliable symbols and the description of its operation is given in [Yourmachine, A. Tretyakov, Sairusi. Device synchronization with soft decisions. // Proceedings of IX all-Russian scientific-technical conference "New information technologies in communication and control systems". Kaluga, 2010. S-338, Fig.2].

From the outputs of the unit adders modulo two 7 information with soft decisions supplied to the inputs D1-D8 block decoder BCH code 8, which contains eight identical BCH decoders 9, 10, 11, operating in parallel.

Option schemes of the BCH decoder and a description of its operation is given in [Yourmachine, Sairusi. The device decoding : CTCSS / DCS is Denmark with mild solutions for the two-stage cascade code. // Proceedings of IX all-Russian scientific-technical conference "New information technologies in communication and control systems". Kaluga, 2010. S.353-369, Fig.4].

The BCH decoder corrects an independent errors up to three pieces and packs of errors to seven pieces in the words generated by a polynomial

g(X)=X16+X12+X11+X10+X9+X8+X6+X4+X3+X2+X+1.

Procedure decode words BCH involves cyclic shifts of the received information for each shift calculation of weights Wi(x) between the syndrome Si(x) and covering combinations of Qi(x). When the cyclic shift on any step, the inequality

Wi(x)=Si(x)-Qi(x)≤(d-1)/2,

where d is the minimum code distance of words BCH, then for the corresponding step i done the fix and the code is decoded. If the inequality is not fulfilled, it means that the detected unrecoverable error. As a covering combinations of the following apply:

Q131151110987532+α+1,

Q223118653+1.

Error correction is performed by inverting the respective bits of the intermediate register at the time of operation of the decoder and at the completion of the CEC is but a record of the result of decoding to the output register. The decoded words BCH WBCH1-WBCH8 with their metrics Q0QU arrive at the inputs of the circuit determine the lowest weight. To determine the decoded words BCH with the lowest weight from the original word WBCH0 first, we determine the positions at which their characters have opposite values relative to the characters of the original word WBCH0. Character values in the correction is reversed, which is equivalent to the metric of the symbol and the maximum value of the metric. Obviously, the higher the value of the metric variable symbol, then the greater the distance corrected symbols from the source symbols. Harder shemotehnicheski to choose the word with the minimum distance from the source of the received word, than to choose the word with the maximum distance from the source of the received word, which is enough to high-order bits of the sum of the metric of the decoded words were more high-order bits of the sum of the metrics of the original words. Therefore, the original metric is replaced by the modified metric, equal to the difference between the maximum metric values and the original metric, for which the word with the minimum distance from the source of the word is selected by the maximum amount of these modified metrics.

In the proposed device when soft decisions during decoding correction to six characters that according to what corresponds to the maximum amount of their metrics, equal to 26+25.

Structural diagram determine the lowest weight and its constituent parts diagram for determining metrics 31-bit words BCH, the schema fragment for the selection of the optimal decoded words BCH, the prioritization scheme, and their functional description for the variant of the device is shown in [Yourmachine, Sairusi. The device decoding with soft decision for a two-stage cascade code. // Proceedings of IX all-Russian scientific-technical conference "New information technologies in communication and control systems". Kaluga, 2010. S.353-369, Fig.5, 6, 7, 8, 9].

Signals permissions E1-E8 outputs of circuits determine the lowest weight 12 connect the outputs of the block decoder BCH code 8 on which the decoded word BCH WZBCH1-WZBCH8 with minimal distance from the source word to the bus OZER, WZBCH. The controller decoder PC signal SR reads the input Ports IN the word BCH and information about the quality of the word BCH, and to the inputs d0-d4 reads the number value of the word BCH. As the controller can, for example, to apply the microcontroller type Atmega 128, a block diagram is shown in source [yevstifeev A.V. the AVR Microcontroller family Mega. The user manual. - M.: Publishing house "Dodeca - XXI", 2007, pp.92, 2.2]. Signal MO defines the beginning and the end of the procedure of decoding a BCH code, and achala the decoding procedure code PC. When decoding code PC bug fix and erase, you can use the received BCH code word according to the procedure Messi [Gallager R. information Theory and reliable communication. USA, 1968, TRANS. from English. edited McEntire and Bustybabe, M.: "Soviet radio", 1974, C-276, RIS].

However, to reduce the complexity of decoding is possible to use only the most reliable BCH code word, as in the shortened code is corrected to a smaller number of errors. On the other hand, the robustness of such a decoding algorithm high because you are using only the most reliable characters, with fewer errors. Complete the sorting procedure for soft solutions impractical due to its complexity. In the simplified procedure of sorting, you can make the next selection on quality:

0 - infallible word without soft decisions;

1 - the infallible words with one invalid symbol;

2 words with the same error without the soft decisions;

3 - the infallible words with two invalid characters.

4 - word with one error and one invalid symbol;

5 words with two errors without soft decisions;

6 - the infallible words with three invalid characters.

7 - word with one error and two invalid characters.

8 - a word with two errors and one invalid symbol;

9 - words stirrup errors without soft decisions;

10 - word with one error and three invalid characters.

11 - a word with two errors and two invalid characters.

12 is a word with three errors and one invalid symbol;

13 - packs with four errors without soft decisions;

14 - a word with two errors and three invalid characters.

15 - word with three errors and two invalid characters.

16 - top five mistakes without soft decisions;

17 is a word with three errors and three invalid characters.

18 - packs with six errors;

19 - packs with seven errors;

20 - unrecoverable error.

After the sorting is done, the final decoding procedure code PC, for example, according to the scheme given in source [RF patent for useful model No. 43420, MPK7 H03M 13/05. Kvashennikov CENTURIES decoders reed-Solomon code. Prior. 12.08.2004, publ. 10.01.2005].

Compared to the prototype, in which to simplify circuit solutions for calculations apply a slow iterative procedure, what is new is that in the proposed device to improve its performance and reliability of the received information entered scheme code frame synchronization with integrated soft and hard decisions, the pattern of formation of the error vectors for the least reliable symbols, a block of adders modulo d is a, the block decoder BCH code, diagram to determine the lowest weight and the controller code decoder PC that when using soft decisions provide a parallel and pipelined computation and meet the technological requirements for the implementation of modern microelectronics, for example, technology system on chip.

Achievable technical result of the proposed decoding device is to improve the performance of the device and improving the reliability of received data in channels with high noise level.

The device decoding with soft decision for a two-stage cascade code containing a corrective device, the input INF which is an information input device, and input C which is clocked by the input device, one of the outputs of the correction device is connected to the input schema definition quality bits, the other output of the correction device is connected to the input of the demodulator, one of the outputs of the demodulator is connected to one of inputs of the circuit determine the quality of the characters and the selection of the least reliable symbols, the other input of which is connected to the output of the circuit determine the quality of bits, characterized in that the device entered the scheme code frame synchronization with integrated soft and hard solutions with the EMA formation of the error vectors for the least reliable symbols, the unit adders modulo two, the block decoder code Bose-Roy-Chaudhury-Hocquenghem (BCH)scheme determine the lowest weight diagram of the controller of reed-Solomon (PC), and the output of the circuit determine the quality of the characters and the selection of the least reliable symbols connected to one of inputs of scheme code frame synchronization with integrated soft and hard decisions, the other input of which is connected to the output of the demodulator outputs Q1QU, CDCH, SR scheme code frame synchronization with integrated soft and hard solutions are connected with inputs of the formation pattern of the error vectors for the least reliable symbols, the output of the circuit forming vectors errors for the least reliable symbols connected to one of inputs of unit adders modulo two, and the other input of the adders modulo two is connected to the output DBCH scheme code frame synchronization with integrated soft and hard decisions, and the outputs of the unit adders modulo two is connected to the inputs D1-D8 block decoder BCH code, which contains eight decoders for BCH code, the other inputs of the block decoder BCH code are connected by BUS with CL output schema code frame synchronization with integrated soft and hard decisions, outputs WBCH0-WBCH8 decoder BCH code are connected with inputs of the circuit determine the lowest weight, input quality characters Q0QU which the Oh is connected to the circuit output coded frame synchronization with integrated soft and hard decisions, outputs for control signals SSN and WRRG which is connected by BUS with CL inputs of the circuit determine the lowest weight, and outputs the permission E1-E8 which are connected with inputs of block decoders BCH code, the outputs WZBCH1-WZBCH8 and OZER1-OZER8 which is connected to the input Ports IN controller code decoder PC inputs interrupt INT1, INT2, INT3 which bus BUS CL connected to the output signal MO and SR scheme code frame synchronization with integrated soft and hard decisions, the outputs d0-d4 which are connected with inputs of controller code decoder PC, the output of which OUT Ports is an information output device.



 

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1 cl, 1 dwg

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

The invention relates to the field of communication technology and can be used in data transmission systems, systems, telemetering and telecontrol

The invention relates to a coder/decoder in a communication system, and more particularly to a device for encoding/decoding of linear block codes by analyzing serial concatenated codes

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

FIELD: communications engineering; data transfer, telemetering, and telecontrol systems.

SUBSTANCE: proposed codec has on sending end code-word data part shaper whose output and that of code-word synchronizing part shaper are connected to modulo two adder input; on receiving end it has binary filter whose code-word data part shaper output is connected to accumulator connected to synchronizing sequence decoder and to error connection unit whose outputs are connected to respective inverting inputs of code-word data part shaper; output of the latter functions as data output of device; output of binary-filter code-word synchronizing part is connected through switching unit to input of code-word data part shaping unit; synchronizing sequence decoder output is connected to control input of switching unit and to error correction unit input; on receiving end accumulator outputs are connected to inputs of code-word data part shift decoder whose output is connected to input of delay circuit whose output functions as second control input of switching unit and as synchronizing output of device.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: communications engineering, in particular, engineering of data transfer systems for decoding cyclic interference-resistant codes without preliminary phasing.

SUBSTANCE: during decoding of cyclic interference-resistant code, range of presumed lengths of code combinations [nmin-nmax] is determined, and assumed phase of beginning of code combination f is set, from phase f in received code series several presumed code combinations Si are selected and pairs are formed from selected combinations in accordance to condition Si≠Sk, N of greatest common divisors, represented by polynomials, is calculated, and from calculated polynomials a polynomial of least order is selected, which is considered equal to original polynomial g(x) of cyclic interference-resistant code, if N of greatest common divisors is equal to "1", then length of proposed code combination n is increased by one, phase of proposed beginning of code combination is altered for one, if greatest common divisor, different from "1", is not found for all n∈[nmin-nmax], combinations of errors are determined in code word and selected code combinations are decoded.

EFFECT: development of method for decoding cyclic interference-resistant code under conditions of adaptation of interference-resistant code to quality of information transfer channel.

3 cl

FIELD: communications engineering, possible use in data transmission systems, for remote measurement, remote control, in radio-transmitting equipment of small spacecrafts and for deep space telemetry.

SUBSTANCE: in accordance to the invention, at transmitting side code words are generated by encoding information symbols using cyclic code without usage of synchronizing patterns, parameters of cyclic code are changed depending on level of interference, transferred information is accumulated at receiving side, thus creating a selection, then for phasing by code words limits of code word are determined, supposed length of code word is set, and in set window "sliding" symbol-wise discrete Fourier transformation is performed in Galois field for whole volume of selection being analyzed, while at each step of "sliding" discrete Fourier transformation in Galois field, selection of zero spectral components is performed as well as determining of quantity thereof together with building a function of number of zero spectral components at each step of "sliding" discrete Fourier transformation in Galois field, then decimation of given function is performed with step, equal to supposed length of code word, with building of a function estimate of mathematical expectation of number of zero spectral components, phasing moments reach maximum of mathematical expectation estimation function of number of zero spectral components, with consideration of resulting maximum, code words are selected, and then estimate of mathematical expectation of code word spectrums is performed and parameters of cyclic code are evaluated on basis of resulting code words, and then cyclotomic classes are determined, the generative polynomial of cyclic code is restored and code words are decoded.

EFFECT: increased interference resistance of cyclic code receipt, automatic adaptation of characteristics of transferred signal to interference intensity, increased speed of information transfer and accelerated phasing process during transfer of code words without synchronizing patterns.

4 dwg

FIELD: physics, communication.

SUBSTANCE: invention is related to the field of communication and may be used in devices for transmission of discrete information in communication line with interferences. Device contains memorising register, unit of error detection, unit of error correction, switching unit, which consists of two "AND" circuits, two registers of generator polynomial, two summators by module two, two decoders, programmable logical matrix, comparison unit, processor, inverter. Also method is disclosed for correction of two errors in cyclic code, which is realised by this device.

EFFECT: increase of communication channels equipment interference protection.

2 cl, 2 dwg, 1 tbl

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