Memory cell for high-speed eeprom with controlled potential of under-gate region

FIELD: information technology.

SUBSTANCE: memory cell for high-speed controlled gate-region potential EEPROM, the electric circuit of the memory cell having an n(p)-MOS transistor, first and second diodes, a capacitor, a number, an address and a bit line, wherein the cathode (anode) of the first diode is connected to the number line and the source of the n(p)-MOS transistor, its anode is connected to the anode of the second diode, the region under the gate of the n(p)-MOS transistor and the first lead of the capacitor, the second lead of which is connected to the gate of the n(p)-MOS transistor and the address line, and the cathode of the second diode is connected to the drain region of the n(p)-MOS transistor and the bit line, wherein the electric circuit of the memory cell additionally includes a p(n)-field-effect transistor, a common and control line, wherein its source is connected to the region under the gate of a MOS transistor, the gate is connected to the control line and the drain is connected to the common line.

EFFECT: higher reliability of memory cell work.

2 cl, 6 dwg

 

The invention relates to semiconductor devices, and more particularly to non-volatile electrically programmable permanent memory devices (EEPROM).

Known-transistor memory cells for memory devices) [1. Matsue S, Vamamoto N, Kobayski K, et al. / A 256 Kbit dynamia RAM IEEE, J. 1980. V sc. 15. No. 5, p.872-874, 2. Al Fazio, Mark Bauer "Intel Strata Flash TM Memory Tecnology Dievopment end Impmentation / Intel Tecnology Gournal Q 4,1997 1-13, 3. M.L.French end M.H.White "Scaling of miltidielectric nonvolatile Sonos Memory Structurec " Solid - State Elec., vol.37, p.1913, 1995].

This: cell "Dennard" [1. Matsue S,Vamamoto N, Kobayski K, et al. / A 256 Kbit dynamia RAM IEEE, J. 1980. V sc. 15. No. 5, p.872-874] for dynamic random access memory (DOSE), the memory cell with floating gate "FAMOS" [2. Al Fazio, Mark Bauer "Intel Strata Flash TM Memory Tecnology Dievopment end Impmentation / Intel Tecnology Gournal Q 4, 1997 1-13] for EEPROM, the memory cell on the basis of transistor silicon - oxide - nitride - oxide - polysilicon (MNOP, CONOP, SONOS) [3. M.L.French end M.H.White "Scaling of miltidielectric nonvolatile Sonos Memory Structurec " Solid - State Elec., vol 37, p.1913, 1995]. In these cells the gate region (substrate) of the MOS transistor is connected to the shared bus (earth), shutter - address bus, and a flow - bit bus, and the source - to numeric bus. This cell - cell memory for high-speed EEPROM [4. PCT/EN 2009/000149 from 30.03.2009 "memory Cell for high speed EEPROM and method of programming "].

In such cells, it is difficult to provide a nonvolatile memory, and they have otnositelno large sizes because of the need to have a large area of information capacity. Cells [2. Al Fazio, Mark Bauer "Intel Strata Flash TM Memory Tecnology Dievopment end Impmentation / Intel Tecnology Gournal Q 4,1997 1-13, 3. M.L.French end M.H.White "Scaling of miltidielectric nonvolatile Sonos Memory Structurec " Solid - State Elec., vol.37, p.1913, 1995] do not provide quick programming EEPROM due to the time-serial fashion their programming

Closest to the technical nature of the invention is a memory Cell for high speed EEPROM [4. PCT/EN 2009/000149 from 30.03.2009 "memory Cell for high speed EEPROM and method of programming]. Figure 1 and figure 2 shows respectively the electric circuit and the design of the memory cell.

The electrical circuit of the memory cell contains n(p)MOS transistor, the first and second diodes, a capacitor, number, address and bit bus, while the cathode (anode) of the first diode connected to the digital and the source of n(p)MOS transistor, its anode connected to the anode of the second diode, the gate region of the n(p)MOS transistor and the first output capacitor, the second terminal of which is connected to the gate of n(p)MOS transistor and to the address bus and the cathode of the second diode is connected to area runoff n(p)MOS transistor and the bit-line.

The design of the memory cell

is a single functionally-integrated structure, which contains n(p)MOS transistor with a floating gate region, n(p)-area source assetnation area n(p)-type cathode (anode) of the first diode, and p(n) gate region p(n)-type anode (cathode) of the first diode; n(p)-area runoff area is n(p)-cathode (anode) of the second diode, and n(p) gate region forms a region p(n)-type anode (cathode) of the second diode; a capacitor respectively formed by a gate dielectric and a gate region of the n(p)MOS transistor.

Such a memory cell does not have

high reliability when reading data due to the instability of the threshold voltage due to the "floating" potential of the gate region.

The aim of the invention is to increase the reliability of the EEPROM.

This goal is achieved by the fact that

the electrical circuit of the memory cell additionally contains p(n) field-effect transistor, a common control bus, with its source connected to the gate region of the MOS transistor, the gate - to control the bus and the drain to a common bus. The design of the memory cell (as a prototype) is a single, functionally-integrated structure, which additionally contains p(n) field-effect transistor, the source of which is simultaneously the gate region of the n(p)MOS transistor, the drain semiconductor substrate of p(n)-type conductivity, and the gate of n(p)-type conductivity formed additional semiconductor region.

Programming the memory cells of proishodit two stages, similarly, as the prototype, with the only difference that the floating potential of the gate region is provided not by the presence of a p-n junction gate region of the substrate, and the space charge region of the channel closed p(n) field-effect transistor by applying to its gate positive zero potential relative to p(n)of the substrate.

Thus, in the first stage are recording operational information, i.e. logical units "log.1" by feeding on the address bus is high (low) zero potential, and the bit on the bus is low (high) potential (+V) and charge the capacitor through a second diode, while the floating gate region of the MOS transistor (which is the first capacitor plate) acquires a negative charge and potential in relation to the shutter, which is the second capacitor plate.

The records of operational information in the form of charge in the capacitor can be maintained (similarly as in the memory cell prototype) long enough, and time of storage is determined by the leakage currents of p-n junctions of the drain-source of the MOSFET, the value of the potential difference in the capacitor formed by the gate, gate dielectric and gate region Vc does not exceed the value of the potentials Vp in the gate system of the MOS transistor is required for PR the program memory.

In the second stage to the gate of the MOS transistor is served extra high capacity V, and such that the sum of the potentials Vc and V greater than the programming voltage of the memory cell, ie,

Vc+V>Vp,

when this happens the account is permanent (non-volatile) information in the memory cell.

In the case of "write" logical zero "log.0" the capacitor is charged to a negative potential and write information into the memory cell when applying additional voltage UD does not occur.

Reading data from the memory cell after the programming is carried out in an open condition p(n)-field-effect transistor, teeri applying to its gate zero potential relative to p(n)-substrate. In this case, the gate region becomes the potential of the substrate.

An advantage of the claimed memory cell in comparison with analogues is the same as the prototype, which is evident in the structures of the matrices EEPROM presented in figure 2 and figure 3, with the integration of EEPROM memory, as is apparent from the figures, reaches theoretical limit.

The performance of traditional EEPROM compared with the DOSE rather slow and is determined by the length of the process time-serial programming of the EEPROM memory cells.

The proposed memory cell solves this problem due to the fact that in the beginning, at first this is e in the memory cell is written operational information in the form of charges in the capacitances of the gates of the respective MOS transistors, as in the DOSE relatively quickly.

In the second phase served briefly 1-2 milliseconds auxiliary voltage (or provide exposure to ionizing radiation), resulting in programmed all the memory cells of EEPROM at the same time, thus, the programming time EEPROM is reduced from tens of minutes up to several milliseconds.

An advantage of the claimed memory cell compared with the analogue is greater reliability, because when reading data gate region has a fixed potential and it has the same conductivity type as the substrate. This fact excludes the possibility of the inclusion of the parasitic bipolar n-p-n - p-n-p transistor formed by the n+ - drain - emitter, the p-gate region - base and n-substrate - collector.

It should be noted that the presence in the design of the gate field-effect transistor does not increase the size of the memory cell, because it is located below and is common to all memory cells EEPROM and it is supplied only one "control" electrode.

The electrical circuit of the memory cell shown in figa, B.

It contains n(R)-MOS transistor T1, the source of which is connected to the cathode (anode) of the first diode D1, digital Z, the anode (cathode) of the first diode is connected to anode (cathode) of the second diode D2, the gate area is through the MOS transistor T1 and the first output capacitor, the second output of which is connected to the gate of n(p)MOS transistor T1 and the address bus X, the cathode (anode) of the second diode D2 is connected to the drain of n(p)MOS transistor and the bit-line Y. the Drain of p(n)-field-effect transistor T2 is connected to the gate region of the MOS transistor T1, its shutter - control bus L, and the source - with a shared bus W.

The design and topology of the memory cell shown in Fig 3.

It consists of a substrate 1, on which surface is n(p)MOS-transistor separated from the substrate side of the dielectric layer - 2, on the surface of the substrate is a flow - 3, forming a numeric bus - 10, region of origin - 4, forming bit bus - 9, the gate region 5 on the surface of which is gate dielectric 6, the surface of which is gate - 7, forming the address bus 7, the surface areas of the drain, source, gate is an insulating dielectric - 8, and on the field source - electrode 4 is bit bus - 9.

Gate area - 5 MOS transistor is separated from the substrate 1 by the space charge region SCR - 11, formed by the shutter - 12 field-effect transistor, the drain of which is simultaneously the gate region 5 and the source - substrate - 1. Gate field-effect transistor is the control electrode 13, a source electrode shared bus - 14.

Ball is IKA memory works as follows:

In write mode, the operational information of the gate region of the MOS transistors of the EEPROM matrix isolated from poloski the space charge region formed by the gate field-effect transistor.

Write mode - "log.1" occurs when applying a positive potential on the address bus x, zero - bit bus occurs at the discharge information of the capacitor C through the diode D2, a floating gate region of the MOS transistor is formed negative potential (charge) in relation to the shutter, which may be kept long enough in the storage of operational information, i.e. at a zero potential on the gate of the address bus X) and a positive potential on the drain bit bus y data storage Time of the charge in the capacitor is determined by the leakage currents of the diodes, i.e. the drain-stokovyh p-n junctions of the MOS transistor, and is typically hundreds of milliseconds (as in the usual DOSE on the basis of the memory cells of Dennard"taken as a prototype).

State "log.0" corresponds to the absence of entries in the memory cell information of the charge in the capacitor, as in the usual DOSE.

Thus, all cells of the EEPROM is written operational information in the form of "log.1" and "log.0". At the same time write RAM also corresponds to the time of its recording in the usual DOSE, ie ~10-9c on Chaco. After recording operational information in the memory cell, it is actually transferred to a constant by simultaneous programming of all the MOS transistors, for example, by applying an additional voltage to all of the transistor gates.

It is important that the physical principle of programming MOS-transistor memory cell of the EEPROM is not significant. In the memory cell can be used, in particular MNOP-transistor, FAMOS transistor with a floating gate MOS transistor, programmable hydrogen ions [4], etc.

The mode of reading data from a memory cell is carried out in the usual way, i.e. in the presence of the opening potential to the gate field-effect transistor by feeding opening - positive potential on the address bus 7, i.e. to the gate of the MOS transistor and numeric bus - 10, i.e. its flow reading signal corresponding to the state of the threshold voltage/ with bit bus - 9 the source of the transistor.

Implementation examples

High speed EEPROM on the basis of the proposed memory cell can be implemented, for example, on the basis of traditional CMOS technology, on Monokini, see figure 4 a, b.

1. The memory cell for high speed EEPROM with a controlled potential of the gate region, the electric circuit of the memory cell contains n(R)-MOS transistor of the first and second di the water, capacitor, number, address and bit bus, while the cathode (anode) of the first diode connected to the digital and the source of n(R)-MOSFET, its anode connected to the anode of the second diode, the gate region of the n(R)-MOS transistor and the first output capacitor, the second terminal of which is connected to the gate of n(R)-MOS transistor and to the address bus and the cathode of the second diode is connected to the drain region of the n(R)-MOS transistor and the bit-line, wherein the electric diagram of the memory cell additionally contains R(n)-field-effect transistor, a common control bus, with its source connected to the gate region of the MOS transistor, the gate - to control the bus and the drain to a common bus.

2. The memory cell according to claim 1, which is a single functionally-integrated structure, which contains n(R)-MOS transistor with a floating gate region, with its n(R)is the area of the source is also the region n(p)-type cathode (anode) of the first diode, and p(n) gate region R(n)-type anode (cathode) of the first diode; n(R)is the area of flow is an area of n(R) of the cathode (anode) of the second diode, and p(n) gate region forms a region p(n)-type anode (cathode) of the second diode; a capacitor respectively formed by a gate dielectric and a gate region of the n(R)-MOS transistor, characterized in that additionally which contains R(n)-field-effect transistor, the drain of which is simultaneously the gate region of the n(R)-MOS transistor, the source of the semiconductor substrate is p(n)-type conductivity, and the gate of n(p)-type conductivity formed additional semiconductor region.



 

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