Systems and methods for dynamic power saving in electronic memory operation

FIELD: information technology.

SUBSTANCE: memory has a series segmented bit line for accessing data in said memory, a latch repeater which controls bit line segments, wherein the latch repeater is controlled by memory address bits and determinants selected from a list of read- and write-enable signals. The method describes operation of said memory.

EFFECT: saving power in electronic memory.

15 cl, 4 dwg

 

The technical field to which the invention relates.

This description relates to electronic memory and, in particular, to systems and methods for reducing the power consumption during the operation of mass storage devices.

The level of technology

The amount of power consumption is of great importance in the operations of the electronic storage device. Power consumption is divided into two categories, namely, standby power and dynamic power. In the backup or static mode, the memory uses the least power, so as not performed neither read nor write. Consumption dynamic power occurs during switching, when a memory access for reading and/or writing.

The power consumption in the memory can be reduced by limiting the switching frequency and/or reducing line capacity because:

P=CV2fA,

where P is the dynamic power; C - linear capacitance, V is the voltage applied to the working string; f is the frequency of memory access; and a is the activity coefficient, i.e. the number of switches when the system performs reads and writes.

Often the power consumption of the memory is controlled by dividing the memory into groups and then to actuate each time only one group.

One of the reasons for the creation of groups - reducing switched capacitance and reduce their activity switching, which in turn reduces dynamic power. Usually the frequency is difficult to control because it is desirable to control the memory at high frequencies. Reducing the operating voltage is a very powerful tool to reduce dynamic power, as is achieved by "cube" effect if it is accompanied by decrease in frequency. However, the decrease in voltage affects performance. The limitation of the amplitude of the signal also reduces dynamic power, but such schemes are complex. The decrease in the activity rate (the number of switches per cycle) is another effective method of reducing dynamic power and is connected with the gate clock signal, a logic optimization and design methods schemes (grouping is a good example). In addition, proper shielding of the signal (temporal, logical and physical) leads to savings in dynamic power, especially in wide tire structures. The present invention has the advantage over all of these methods.

The invention

Power reduction in the electronic storage device is performed by the segmentation bit lines and the implementation of the resolution only for certain segments of the bit lines depending on where it will be used for access to memory. In one of the C variants of the invention, bit lines are segmented using repeaters with a latch to control the address selection in relation to the segments beyond the first segment. Repeaters with the latch in one embodiment, may remain in the managed/unmanaged state at the completion of the cycle of the read/write memory. This avoids sequential allow pulses, when the same segment is accessed in sequential cycles.

In one embodiment, the described storage device having at least one segmented bit line for accessing data in memory so that the bit line contains segments, driven by the repeater latch. In one embodiment, the resolved/unresolved status of the repeater latch is controlled by certain bits of the memory address.

In one embodiment, the operation of the storage device is to reduce the power so that certain sectors are segmented, so that less than all the memory is queried for certain memory accesses. During any polling cycle memory is possible, depending on the address to be accessed, to carry out the resolution for the necessary memory segments.

Above is described in rather broad terms the characteristics and technical advantages of the present disclosure of the invention so that further detailed description was more clear. Will be described further characteristics and advantages, which shall constitute the subject-matter of the claims. Professionals should be clear that the concept and described specific embodiments of may be used directly as a basis for modifying or designing other structures to achieve the objectives of this device. Professionals should also be understood that such equivalent constructions are within the essence and scope of the invention defined by the claims. New features which characterize this invention, as to organization and method of operation, together with further objectives and advantages will be clearer from the following description when considered together with the accompanying drawings. However, it should be understood that each of the drawings are presented only to illustrate and describe, not to limit the present invention.

Brief description of drawings

For a more complete understanding of the present invention links below to the following description in conjunction with the attached drawings.

Figure 1 is a block diagram illustrating a typical memory device of the prior art.

Figure 2 is a block diagram illustrating a segmented bit line using at least one repeater latch.

Figure 3 - connection diagram illustrating one variant of the repeater latch, usage is used in the embodiment of figure 2.

4 is a block diagram illustrating an example wireless communication system in which an advantageous way to use a variant embodiment of the invention.

Detailed description of the invention

Figure 1 illustrates a typical memory 10 of the prior art. This storage device (memory) may be a static NVR, dynamic NVR, magnetoresistive NVR or other types of memory. The storage device 10 is typically created using a pre-decoder, such as pre-decoder 11, and a decoder, such as decoder 13. Matrix 12 and memory 14 are matrices containing the memory cell. Matrix 12 and 14 memory consists of a number of global bit lines (e.g., 15), which can be used for reading and/or writing.

The memory device consumes dynamic power in accordance with its size (the length of the bit lines and the power of memory, as mentioned above. The capacity of the C bit lines is determined mainly by the manufacturing technology and is approximately 0.25 femtofarad in microns. Thus, 300-micron bit line will have associated with it a capacity of 75 femtofarad. Accordingly, the capacity of 75 fF will be the minimum capacity of the switch. As will be discussed below, reducing the power consumption to moldstat selective change of the number of memory elements, which is activated for a given memory access.

Figure 2 shows a variant embodiment of the invention using at least one repeater 30-A, 30-B, 30-C with a latch inside the storage device 20. Repeaters 30-A, 30-B, 30-C with a latch can be used to split global bit line in the segmented bit line 25, thereby effectively reduce the active length of the bit lines and, consequently, the capacity for multiple cycles memory. The reduction of capacity leads to an overall reduction in the power consumption of memory.

The decoder 23 repeater latch determines which repeater 30-A, 30-B, 30-C latch is activated at a specific point in time depending on which element of the matrix is accessed. Agents 22-A, 22-B and 22-C of the decoder latches are inside the decoder 23 repeater latch. Agents 22-A, 22-B and 22-C of the decoder latches are latched repeaters 30-A, 30-B, 30-C at a given point in time. Agents 22-A, 22-B and 22-C of the decoder can activate only one repeater with a latch or multiple repeaters 30-A, 30-B, 30-C with a latch at the specified time.

In the present embodiment, the matrix memory and the global bit line is divided into four sectors, and segments of the bit line is separated by three repeaters 30-A, 30-a With the latch. The segment bit line for sector 1 in this embodiment is always in the on state, and thus there is no need for a repeater with a latch inside the segmented bit lines 25 to sector 1. To implement the access to the memory element in sector 2, the repeater 30 And the latch must be activated. Similarly, the repeater 30 In the latch controls access to the memory in sector 3 and the repeater 30 With the latch controls access to memory in sector 4.

Although figure 2 shows four sectors, in fact, the memory may be divided into any number of sectors depending on the user's needs. The reduction capacity of the bit line can be achieved with the use of this sectoral approach. For example, if you have access to sector 1, then the agent of the decoder (e.g., 22-a) is cut off, and thus there is only the capacity of the bit line to the repeater 30 And the latch. If you need access to sector 2, the exciter 22 And decoder activates the repeater 30 And the latch, and the capacity of the line increases. Access to sectors 3 and 4 will cause a further increase in capacity when the agents 22 and/or 22-decoder activate repeaters 30 In and 30 With the latch to access the sectors 3 and 4, respectively.

Note that, although figure 2 shows the only one segmented bit line 25, for 64-bit memory I / o will contain sets of 64-bit lines. For multiport memory should be one set of resources (the causative agent of the decoder and the repeater latch) for each port. Single-port memory has one set of segmented bit lines 25 for reading and one set of segmented bit lines 25 for the record.

Agents 22-a, 22-B, 22-decoders and repeaters 30-A, 30-b and 30-C With latch will introduce a delay in the access time and to consume power and, thus, may affect the characteristics of the memory. Despite this, the overall characteristics are improved, because, as stated above, according to statistics, most of the accesses are performed in the middle part of the memory. Moreover, each repeater input 30-A, 30-B, 30-locking reduces the delay relative to the far end of the bit line due to the shorter lengths of the bit lines. The delay line is proportional to R*C. R and C respectively inversely proportional to the length of the line. Thus, the delay is inversely proportional to the square of the length of the line. When the line is split into two parts, the delay in the result of this is reduced four times. For this reason, when using the repeater 30 And the latch is a performance increase.

Moreover, the repeaters 30-A, 30-b and 30-C With latch increase is ratesno signals, entered in the logic circuit, thereby reducing the possibility of a short circuit. The steepness of the input signal to the logic circuit determines what time the device is in the short circuit mode with simultaneously included loading and unloading transistors. Typically, the short-circuit power is 10-15% of the total dynamic power. But if the slope of the input signal is really insufficient, short-circuit power can be a substantial amount. Split the line into segments and adding repeaters in General improves the steepness of the input signal in each section.

The only disadvantage of adding logic circuits and repeaters is necessary to increase the space on the substrate. However, with the improvement of technology and the reduction in size from 45 nm to 32 nm and less additional space becomes available without increasing the area of the substrate.

The following describes the management agent decoder based on memory addressing. When working each memory requires a certain number of bits in the address each time when accessing memory. For example, consider the 8-bit address structure. This structure will have a discharge from a0to and7,which allow access to 256 cells p is mate. Discharge and7- this is the most significant digit (MSB - most significant bit) of the address. If the discharge and7is null, then the access will be implemented in sectors 1 or 2, and if rank a7is 1, then the access will be implemented in sectors 3 and 4. Thus, if the MSB is equal to one, the signal will be sent through the findings 201-2, 201-3 probably active repeaters 30-a and 30-b latch. Activation of the repeater may depend on determining the signal sent to the output Q, as will be hereinafter set forth.

Addresses usually occur early in the cycle to read or write (before the rise of the front of the clock pulse) so that the system pre-decoder knows in advance which sectors are to be accessed. Using this knowledge, the pre-decoder (if rank a7equal to 1) can prepare for the launch of pathogens 22-a and 22-In decoder (and associated repeaters 30-a and 30-b latch), while the start of the activator 22-decoder (and the associated repeater 30 With the latch) is yet to be determined. Conversely, if rank a70, only the exciter 22 And decoder and its associated repeater 30 With the latch will get a chance to run, and the trigger condition will be determined on the basis of the analysis of the next most significant category of a6.

In the line is the cation discharge a 6pre-decoder 21 can allow state agents 22-a and 22-decoder and associated repeaters 30-a and 30 With the latch. The value of the discharge and6determines whether the target memory access to be at the top or bottom sector of the sectors selected by the discharge and7. Thus, suppose that rank a7is in state 1 and a6also in state 1, then the exciter 22-decoder and its associated repeater 30 With the latch will be activated by the signal on output 201-1, because the memory access will be performed in sector 4. Similarly, if the discharge and7is in the state 0 and the discharge and6in state 0, the agents of the decoder or repeaters with latches will be activated, because the target memory access will be performed in sector 1.

In one embodiment of the invention pathogens 22-a, 22-b and 22-decoder partially controlled by the signals on outputs 201-1, 201-2, 201-3, respectively, from the pre-decoder 21. To avoid switching without the need, determinants, such as signals permissions to read or write, can be used through the output Q of the pre-decoder 21 in addition to the signals related to the bits in the address, to implement solutions for various sector of the century In this embodiment, the causative 22-a, 22-b and 22-C of the decoder can be logic "And". For example, if you receive both signals: the signal recording resolution and the signal of the address discharge, the exciter 22 And decoder and the repeater 30 And the latch will be activated. If the identifier is not used, then agents 22-a, 22-b and 22-C of the decoders may be inverters, and not logic "And". Also note that any number of configurations of memory access can be used to control pathogens 22-a, 22-b and 22-decoders, including sending information directly from another location relative to the choice of a specific sector.

Figure 3 shows one example of the repeater 30 And the latch used in the embodiment of figure 2. The repeater 30 And the latch is located between the points A1 and A2 (figure 2) segmented bit line 25. As shown in the drawing, the repeater 30 And includes two series-connected inverter 31 and 32. He is also the latch 34 (comprising two inverter 35), which opens or closes depending on the switch, such as a valve 33 bandwidth. The valve 33 bandwidth opens and closes in response to a signal on a control line A control received from the exciter 22 And decoder for sector 2. Note that the structure 30 And is shown is only an example, as to perform the described functions can be applied in other patterns.

When the operation of the circuit, assuming that a7is in state 1 (and defines the signal set), the repeater 30 And the latch should be included. Thus, the valve 33 of the transmission receives the signal 1 from the control line control A. In response to this N-channel gate 33 transmission goes into state 1, and the P-channel goes to 0, including repeater latch. If the repeater latch is enabled, the data segment bit line of the sector 1 is transferred into the segment bit line of the sector 2, and also updates the latch 34 these data.

Due to the fact that the latch 34 stores the value of the data latch 34 then controls the value of bit lines in the segment above the repeater 30 And the latch, in this case, the segment bit line of the sector 2. Once installed, the data remains in the same state until active change by re-opening the valve 33 bandwidth. As a consequence, the segment bit line sector 2 stores a fixed value, i.e., the segment bit line of the sector 2 is controlled by the repeater 30 And the latch. If the following value input in sector 2 is the same as that of the previous data, it is not necessary discharge of the discharge segment is sector 2, because the bit lines of the sector 2 already has a fixed value. Thus, this structure has the effect of prehistory, namely, that if all the repeaters 30-A, 30-b and 30-C With snaps open and all segments of the bit lines must appear 1 for the next working cycle, none of the segments of the bit line is discharged.

Some applications of the law of Ukraine can be adapted to take advantage of the structure of such a memory so you can store data in accordance with their expected frequency of access. Accordingly, by storing data having a high frequency of access, in the upper half of the memory and data with a low frequency of access - in the bottom half, you can get more significant savings in power, than by the arbitrary data storage.

Note that although discussed in the main bit line, the essence of the present invention can be applied to lines, words, and lines of words in combination with the bit lines. In this device, the lines of words are segmented controllers segments. Controllers segments are controlled by separate control signals coming to them outside of the address field, restricting ZU the part where the memory access at this time.

Figure 4 shows an example system is neither wireless 400, in which applied a variant of the present invention. To illustrate the invention, figure 4 shows three remote devices 420, 430 and 450 and two base station 440. It is clear that such wireless communication systems may have much more remote devices and base stations. Remote device 420, 430 and 450 include improved full-matrix A, V and S respectively, which are variants of the invention, as will be described below. Figure 4 shows the signals 480 direct line of communication from the base station 440 to remote devices 420, 430 and 450 and signals 490 return line connection from remote devices 420, 430 and 450 base stations 440.

Figure 4 remote device 420 is a mobile phone, the remote device 430, a portable computer, and the remote device 450 - stationary remote device in the wireless local loop. For example, remote devices may be cell phones, handheld devices, personal communications systems (PCS), portable devices with blocks of data, such as a personal digital assistant, or stationary blocks of data, for example, devices for reading the measurement data. Although figure 4 according to this invention shows the remote controller with many brand the main device, the invention is not limited to illustrated examples of devices. The invention can also be applied in devices that have a full size matrix memory.

Although an example of a specific circuit, specialists should be clear that not all schemes are required to implement the present invention. Besides some well-known circuits have not been described in order to focus on the invention. Also, although the invention refers to a state of logical "0" and logical "1" in certain positions, the expert will understand that the data of the logical values can be switched. This consequently will change the rest of the circuit, but this will not affect the operation according to the present invention.

Although the present invention and its advantages have been described in detail, it is necessary to understand that various changes, substitutions and rearrangements within the scope and essence of the invention defined by the claims. In addition, the scope of the present application is not limited to specific examples of this process, machine, manufacture, structures, tools, methods and actions disclosed in the description. From the description of processes, machines, manufacture, structures, tools, methods, or activities that currently exist or will be atrabotana in the future and which perform basically the same function or achieve the same result, the corresponding described above options, specialists should be clear that the same result can be achieved by use of the present invention. Accordingly, the attached claims require the inclusion in its scope such processes, machines, manufacture, structures, tools, methods, and actions.

1. A storage device containing sequentially segmented bit line for accessing data in said storage device; repeater latch that controls the segment bit line, and the repeater latch is controlled by the bits of the memory addresses and the identifiers selected from the list of signals read permissions and signals the write-enable.

2. The storage device according to claim 1, additionally containing a latch to store the state of the above-mentioned repeater latch with multiple accesses.

3. The method of reducing power electronic storage device containing the segment selection bit line based on the address bits of the memory access and update data in at least one repeater with a latch on said bit lines for essentially simultaneously run multiple sequential segments of the bit lines including the selected segment bit line.

4. The method according to claim 3, which contains additional saving the updated values of the mentioned at least one repeater latch with multiple access.

5. The method according to claim 3, additionally containing the delay mentioned selection based on some identifier in addition to the mentioned address bits.

6. The method according to claim 3, additionally containing management mentioned at least one repeater with a latch, at least partially, based on the value of high-order address bits.

7. The method of reducing power electronic storage device containing a selection of line segment words on the basis of the address bits of the memory address and the data updating at least one repeater with a latch on said line of words to essentially simultaneously run multiple consecutive line segments of words, including the selected line segment words.

8. The method according to claim 7, additionally containing management mentioned at least one repeater with a latch, at least partially, based on the value of high-order address bits.

9. A storage device containing multiple memory array, and the above-mentioned matrix memory adapted to store data;
many consistently segmented bit lines, and at least one bit line is designed to control access to the sectors mentioned memory array; and at least one repeater latch, located in each of the sequentially segmented bit lines, moreover, the repeater latch includes a latch operable to store the state of the above-mentioned repeater latch during cycles memory.

10. The storage device according to claim 9, further contains logic to run the above-mentioned repeater latch, and referred to the logic circuitry responds to certain bits in the address access is accepted by the memory.

11. The memory device of claim 10, further containing a control circuit for setting signals to control the aforementioned logic circuit, and said control circuit operates at least in part, using the values contained in the at least one bit position of the address received by the memory, and the above-mentioned address corresponds to the target sector.

12. The storage device according to claim 11, in which said control circuit additionally acts to provide identifiers for additional control permit for the above-mentioned logical schema.

13. The memory device of claim 10, further containing a scheme for resolving the above repeater latch to remain in the enabled state for more than one cycle of memory access.

14. The storage device according to claim 9, in which the said repeater latch comprises a pair of logic circuits are separated by a switch bandwidth moreover, the above-mentioned switch transmission operates to permit the passage of data from the first mentioned pair of logic circuits to the second mentioned pair of logic circuits, when the above-mentioned repeater latch is in the enabled state.

15. The storage device according to claim 9, further containing at least one repeater latch to separate consecutive line segments of words.



 

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SUBSTANCE: device in form of semiconductor memory device has control block with control elements and memory cells, each of which is made with possible connection to system of buses for connection to central processor and has an in-built microprocessor, including registers, made with possible storage of signs of start of data flow name and its end, information about state and mode of in-built microprocessor. Method describes process of data processing in aforementioned recording device.

EFFECT: higher speed of operation.

6 cl, 7 dwg

FIELD: physics; computer technology.

SUBSTANCE: invention refers to the method and device for the implicit preliminary charging of dynamic operative memory. The memory device contains at least one bank consisting of memory cells, organised into a set of lines of memory cells; and the logic control facility connected with at least one bank, and reacting to reception by the memory device to a command of activation of a single line for opening a particular line in such a manner that if there are no open lines when the command has been given, then at least in one bank it opens, and if in the bank another line is open, then the other line closes and the particular line opens. The device of management of memory contains the first site of storage in which is stored data relative to the lines in bank of memory cells in the memory device and a logical control tools transformed, committed to the memory cells. The methods describe the work of the specified devices.

EFFECT: expanding the functional capabilities of the device for preliminary charging of dynamic operating memory.

22 cl, 6 dwg

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