Method for uhf high-power transistors manufacturing

FIELD: electricity.

SUBSTANCE: method for UHF high-power transistors manufacturing includes formation of transistor topology semiconductor substratum on the face side by electronic lithography and photolithography methods, metals spraying on, dielectrics application and etching, cathodic electrodeposition of gold, formation of preset size grooves on the face side outside the transistor topology, substrate thinning, formation of grounding through holes for the transistors source electrodes, formation of a common integrated heat sink, formation of a integrated heat sink for each transistor crystal, semiconductor substrate division into transistor crystals; one uses a semiconductor substrate with the preset structure of active layers having two stop layers with the preset distance between them, the stop layers ensuring minimum thermal resistance; the semiconductor substrate reverse side thinning is performed down to the stop-layer located close to such side; grounding through holes are formed immediately on the source electrodes with the common integrated heat sink thickness is set by the type of the transistor crystal subsequent mounting.

EFFECT: enhanced output capacity through reduction of thermal resistance, parasitic of the electric resistance in series and source electrodes grounding inductance; increased yield ratio, repeatability and functionalities extension.

4 cl, 1 dwg, 1 tbl

 

The invention relates to electronic devices, and in particular to methods of manufacturing of the power transistors and monolithic microwave integrated circuits (MIC) based on them.

The known method of manufacturing of the power field-effect transistors with the barrier Schottky (VTS) microwave oven, including:

forming on a semiconductor wafer (substrate) - epitaxial structure of gallium arsenide topology VTS via electronic methods and photolithography, deposition of metals, deposition and etching of dielectrics, galvanic deposition of gold;

the thinning of the semiconductor wafer to 60-80 microns;

forming through holes for grounding electrodes sources of the transistors;

galvanic deposition of gold with a thickness of 2 μm on the back side of the semiconductor wafer;

the separation of the semiconductor wafer on the crystals transistors sharp diamond disks [1].

The disadvantages of this method are the low output power of the FET microwave due to the large thermal resistance due to the large thickness of 60-80 μm, the semiconductor wafer of gallium arsenide, the low yield due to mechanical damage, chips and cracks that occur when the separation of the semiconductor wafer sharp diamond disks.

A known method of manufacturing a powerful field t is ancestoral microwave and MIS based on them, including:

forming on a semiconductor wafer - epitaxial structure of gallium arsenide topology VTS via electronic methods and photolithography, deposition of metals, deposition and etching of dielectrics, galvanic deposition of gold;

the thinning semiconductor wafer of gallium arsenide to a thickness of 25-30 μm;

the formation of the integral heat sink made of gold with a thickness of about 30 μm by an electroplating deposition on the back side of the semiconductor wafer of gallium arsenide;

the separation of the semiconductor wafer of gallium arsenide on the crystals transistors sharp diamond disks [2].

Integral heat sink allows you to utonet semiconductor wafer of gallium arsenide to a thickness of about 30 μm without mechanical disturbances and thereby compared with the previous method to reduce thermal resistance with 3-4 times, and as a result, significantly increase power output.

However, on the other hand, when the separation of the semiconductor wafer on the crystals transistors to ensure its strength is required to glue a thin semiconductor wafer on a flexible carrier, which complicates the method.

And the separation of the semiconductor wafer on the crystals transistors sharp diamond disks, as in the previous method, Pref is the CIO to the occurrence of mechanical damage, chips and cracks, and consequently the low percentage of yield.

Moreover, in the process of separating plates on crystals, including when cutting the integral heat sink with a thickness of about 30 μm is fast "clogging" of the cutting tool and the formation of gold "collar" around the perimeter of the crystal transistor. This causes difficulties in subsequent mounting of the crystal of the transistor in the circuit of the microwave, which is a negative factor for both electrical characteristics and output.

A known method of manufacturing a powerful microwave transistors, including:

forming on the front side of the semiconductor wafer (substrate) topology transistors through electronic methods and photolithography, deposition of metals, deposition and etching of dielectrics, galvanic deposition of gold,

the thinning of the semiconductor wafer to a thickness less than 30 μm,

etching the semiconductor wafer through the grounding hole for conclusions (source electrodes) of the transistors

forming on the back side of the semiconductor wafer total integrated heat sink of gold electroplating deposition of a thickness exceeding 30 μm,

the separation of the semiconductor wafer on the crystals transistors [3 - prototype], in order to increase capacity, as in the previous the x counterparts, by reducing thermal resistance, higher yield and simplify the method of manufacturing

before thinning semiconductor wafer on its obverse outside of the topology of the transistors form a groove depth of 5-10 μm and a width of 70-100 μm to specify the size of the crystals transistors

and after thinning the semiconductor wafer to form grooves on its underside a depth of 5-10 μm directly under the grooves on the front side, the ratio of their width equal to 3-2, and form the grooves by means of techniques of photolithography and etching,

after the formation of the General integral heat sink forms an integral heat sinks each transistor crystal by means of techniques of photolithography on the total integrated heat sink and subsequent etching in the locations of the grooves on the back side of the semiconductor wafer,

and the separation of the semiconductor wafer on the crystals of the transistors is performed by the method of chemical etching, with integral heat sinks each transistor crystal serve as a mask.

The formation of grooves on the front and back side of the semiconductor wafer opposite to each other and with the specified size in conjunction with other signs allowed:

to increase output power,

to increase the yield,

at the restite method of manufacture.

However, to ensure the thickness of the semiconductor wafer is less than 30 microns is subject to strict requirements to the variation of its thickness (not more than ±1.5 mm) mechanically grinding and polishing the back side to the required thickness before chemical thinning.

Chemical thinning of less than 30 μm is very difficult to provide such a thickness variation across the semiconductor wafer, and particularly with the diameter of the semiconductor wafer more than 75 mm.

The technical result of the claimed invention is to increase the output power by reducing thermal resistance, the parasitic serial electrical resistance and inductance of the grounding electrodes origins, increased yield, reproducibility and enhanced functionality.

The specified technical result is achieved by the claimed method of manufacturing a powerful microwave transistors, including

forming on the front side of the semiconductor substrate with the specified structure of the active layers of the topology of the transistors through electronic methods and photolithography, deposition of metals, deposition and etching of dielectrics, galvanic deposition of gold,

forming on the front side of the semiconductor substrate outside of the topology of the transistors of the grooves of a given size to set the size of the RA of each transistor crystal,

thinning the back side of a semiconductor substrate,

forming in the semiconductor substrate through the grounding hole for the source electrodes of transistors by etching,

forming on the back side of the semiconductor substrate total integrated heat sink required thickness of the gold electroplating deposition,

the formation of the integrated heat sink of each transistor crystal by means of techniques of photolithography on the total integrated heat sink and the subsequent etching

the separation of the semiconductor substrate on the crystal transistors by means of the method of chemical etching, with integral heat sink of each crystal of the transistor serves as a mask, in which use semiconductor substrate with a specified structure of an active layer having two stop layer with a specified distance between them that provides minimum thermal resistance,

and thinning the back side of a semiconductor substrate is carried out until the stop layer located in the vicinity of this side,

and through the grounding hole electrodes and source of the transistor is formed directly on the electrode of the source,

given the thickness of the total integrated heat sink made of gold set type subsequent installation of the transistor crystal,

and subsequent etching when forming the integrated heat sink of each transistor crystal is carried out in the location mentioned grooves on the front side of the semiconductor substrate.

As a semiconductor substrate using semiconductor materials of group AIIIBVsuch as gallium arsenide.

Mentioned grooves on the front side of a semiconductor substrate to form a depth of 3-5 microns and a width of 70-100 μm.

Given the distance between the two stop layers take 1-10 microns.

In the case of soldering the transistor crystal solid solder the General integral heat sink is formed with a thickness equal to 25-30 μm, in the case of installation on an additional heat sink with high thermal conductivity, such as CVD or natural diamond - 5-7 ám.

Disclosure of an entity

Using a semiconductor substrate with a specified structure of an active layer having two stop layer with a specified distance between them, provides,

first, the set distance between the two stop layers provides minimum thermal resistance of the transistor and, as a consequence, the increase of output power;

secondly, the stop layer located near the front side of a semiconductor substrate due to its properties provides controlled etching of the channel of the transistor and, as sredstv is e, the increase of yield and reproducibility.

Thinning the back side of the semiconductor substrate to the stop layer located in the vicinity of this hand, ensures a controlled, predetermined overall thickness of a semiconductor substrate and, as a consequence, the increase of yield.

Forming a through grounding holes for electrodes and source of the transistor directly to these electrodes, the source provides a significant reduction of the parasitic serial electrical resistance and inductance of the grounding electrodes of the source and, consequently, increase power output.

Moreover, a thin semiconductor substrate (thickness less than 30 microns) allows to form the grounding holes through more chemically and environmentally friendly method of chemical etching in contrast to plasma containing chemical compounds toxic element chlorine.

Setting the total thickness of the integral heat sink type subsequent installation of the transistor crystal provides enhanced functionality, namely the ability to use in brazing brazing alloys (when the thickness of the total integrated heat sink, equal to less than 30 microns) and the possibility to use additional heat sink with high thermal conductivity, such as CVD or natural diamond (at 5-7 μm).

Subsequent etching when forming the integrated heat sink of each transistor crystal at the location of the mentioned grooves, namely, the front side of the semiconductor substrate outside of the topology of the transistors provides a controlled size of each transistor crystal and, consequently, increase reproducibility.

The formation of grooves on the front side of semiconductor substrate:

depth is less than 3 μm is not sufficient for the subsequent set the size of the crystal, and more than 5 μm is not desirable because of the possible destruction of the substrate in the subsequent process operations;

a width of less than 70 μm is not desirable because not manufacturability, and more than 100 μm is not advisable due to unnecessary consumption of expensive semiconductor material.

Thus, the set of essential features of the claimed method of manufacturing of the power transistor UHF fully specified technical result, namely the increase in power output, yield, reproducibility and enhanced functionality.

The invention is illustrated in the drawing.

Figure 1 is given the phase separation of a fragment of a semiconductor substrate in the transistor crystals, where

- semiconductor substrate 1, with the specified structure of the active layers

the topology of the transistors -2,

groove 3 on the front side of the semiconductor wafer outside of the topology of the transistors

each transistor crystal - 4,

earthing hole - 5 for the electrodes of the source - 6 transistor

- overall heat - 7,

integral heat sink of each transistor crystal - 8,

two stop layer 9, and 10, respectively.

Example 1 specific performance

On the front side of the semiconductor substrate 1, for example of gallium arsenide, with a total thickness of 520 μm with the specified structure of the active layers, including having two stop layer 9, and 10, respectively, with the distance between them, for example, 5 μm, form the topology of the transistor 2 by the known methods of electronic and photolithography, deposition of metals, deposition and etching of dielectrics, galvanic deposition of gold,

next on the front side of the semiconductor substrate 1 outside of the topology of the transistor 2 is formed of the groove 3 a depth of 4 μm and a width of 85 μm to specify the size of each transistor crystal 4 by means of techniques of photolithography and etching,

- then plunge back side of a semiconductor substrate 1, for which it paste on a medium such as glass, with ploskoparallyel less than 1 μm and methods for mechanical grinding plunge her a thickness of 120 μm, then perekleivat semiconductor substrate to wear the spruce sapphire and method for chemical-dynamic polishing plunge it to the stop layer 10, located near this (reverse) side of the semiconductor substrate.

- form the ground through holes 5 for the source electrodes 6 transistors directly on these source electrodes by means of techniques of photolithography and chemical etching,

- General form of the integral heat sink 7 by an electroplating deposition of gold with a thickness of 25-30 μm,

- form an integral heat sink of each transistor crystal 8 on the General integral heat sink by means of techniques of photolithography and subsequent chemical etching

- divide the semiconductor substrate 1 on the crystals of the transistors 4, wherein the integrated heat sink of each crystal of the transistor 8 serves as a mask, poison semiconductor substrate of gallium arsenide 1 in the locations of the grooves 4 on its front side.

Thus, we have the media of the sapphire separated crystals of powerful transistors UHF, who take off from a carrier in organic solvents.

Examples 2-5

Analogously to example 1 produced powerful microwave transistors, but with different distance between the first and second stop layers and dimensions of the grooves on the front side of a semiconductor substrate of gallium arsenide within the limits specified in the formula of the invention (examples 2-3) and outside it (examples 4-5).

On prepared samples powerful is ransistors microwave oven:

conducted a visual examination under a microscope LEICA INM 100 to mechanical damage, chips, cracks, reproducibility of electrical characteristics of microwave transistors;

b) measured power output.

The data are summarized in table.

As the table shows, the samples of microwave transistors, manufactured by the proposed method (examples 1-3), we have:

output power, exceeding the output power transistor UHF prototype of the order of 50 percent and

the reproducibility of the electrical characteristics about 90 percent (versus 70 percent in the prototype).

In contrast to the sample transistor UHF (example 5), which has a higher value of thermal resistance and therefore lower power output.

The sample transistor UHF (example 4) has electrical parameters slightly higher than the samples (examples 1-3), but it is difficult technologically feasible.

Thus, the proposed method of manufacturing of the power transistors microwave will allow for a comparison with the prototype,

first, to increase the output power of the order of 20 percent by reducing thermal resistance and the parasitic serial electrical resistance and inductance of the grounding electrodes origins

secondly, to improve the yield and reproducibility is ity electrical characteristics

thirdly, to enhance its functionality.

The proposed method for the manufacturing of the power transistors microwave can be used in the manufacture of various microwave devices based on them, and especially in monolithic integrated circuits.

Sources of information

1. Ivashchuk AV, Barefoot V., Kovalchuk NR. Microwave field-effect transistors medium power millimeter waves. The technology and design of electronic equipment, No. 6, 2003, p.27-31.

2. Handbook of Microwave and Optical components, Vol 2, 1990, Fabrication processes, p.518-523.

3. RF patent №2285976, IPC H01L 21/335, priority 06.05.2005, publ. 20.10.2006, bull. 29 prototype.

1. A method of manufacturing a powerful microwave transistors, comprising forming on the front side of the semiconductor substrate with the specified structure of the active layers of the topology of the transistors through electronic methods of photolithography, deposition of metals, deposition and etching of dielectrics, galvanic deposition of gold, forming on the front side of the semiconductor substrate outside of the topology of the transistors of the grooves of a given size to set the size of each transistor crystal, thinning the back side of a semiconductor substrate, forming in the semiconductor substrate through the grounding hole for the source electrodes of transistors by etching, forming on Britney side of the semiconductor substrate total integrated heat sink required thickness of the gold electroplating deposition, the formation of the integrated heat sink of each transistor crystal by means of techniques of photolithography on the total integrated heat sink and subsequent etching, the separation of the semiconductor substrate on the crystal transistors by means of the method of chemical etching, with integral heat sink of each crystal of the transistor serves as a mask, characterized in that use semiconductor substrate with a specified structure of an active layer having two stop layer with a specified distance between them that provides minimum thermal resistance, and thinning the back side of a semiconductor substrate is carried out until the stop layer located near this side and end-to-end grounding holes for the source electrodes of transistors formed directly on the electrode of the source, specified thickness the total integrated heat sink made of gold set type subsequent installation of the transistor crystal, and the subsequent etching when forming the integrated heat sink of each transistor crystal is carried out in the location mentioned grooves on the front side of the semiconductor substrate.

2. A method of manufacturing a powerful microwave transistors according to claim 1, characterized in that a semiconductor substrate using semiconductor materials of group AIIIB Vfor example, gallium arsenide.

3. A method of manufacturing a powerful microwave transistors according to claim 1, characterized in that the said grooves on the front side of a semiconductor substrate to form a depth of 3-5 microns and a width of 70-100 μm.

4. A method of manufacturing a powerful microwave transistors according to claim 1, wherein the set distance between the two stop layers take 1-10 μm.



 

Same patents:

FIELD: electricity.

SUBSTANCE: field transistor manufacturing method includes creation of source and drain contacts, active area identification, application of a dielectric film onto the contact layer surface, formation of a submicron chink in the dielectric film for the needs of subsequent operations of contact layer etching and application of gate metal through the resistance mask; immediately after the dielectric film application one performs lithography for opening windows in the dielectric at least one edge whereof coincides with the Schottky gates location in the transistor being manufactured; after the window opening a second dielectric layer is applied onto the whole of the surface with the resistance removed; then, by way of repeated lithography, windows in the resistance are created, surrounding the chinks formed between the two dielectrics; selective etching of the contact layer is performed with metal films sprayed on to form the gates.

EFFECT: simplification of formation of under-gate chinks sized below 100 nm in the dielectric.

6 dwg

FIELD: electricity.

SUBSTANCE: manufacturing method of microwave transistor with control electrode of T-shaped configuration of submicron length involves formation on the front side of semi-insulating semi-conductor plate with active layer of the specified structure of a pair of electrodes of transistor, which form ohmic contacts by means of lithographic, etching method and method of sputtering of metal or system of metals, formation of transistor channel by means of electronic lithography and etching, application of masking dielectric layer, formation in masking dielectric layer of submicron slot by means of electronic lithography and etching; at that, submicron slot is formed with variable cross section decreasing as to height from wide upper part adjacent to the head of the above control electrode to narrow lower part adjacent to transistor channel, formation of topology of the above control electrode by means of electronic lithography method, formation of the above control electrode in submicron slot by means of sputtering of metal or system of metals; at that, configuration of its base repeats configuration of submicron slot. During formation of submicron slot with variable cross section in masking dielectric layer, which decreases throughout its height, by means of electronic lithography and etching, the latter of masking dielectric layer is performed in one common production process in high-frequency plasma of hexafluoride of sulphur, oxygen and helium and discharge power of 8-10 W.

EFFECT: increasing output power and amplification factor, increasing reproducibility of the above output parametres and therefore yield ratio, simplifying and decreasing labour input for manufacturing process.

2 cl, 1 dwg, 1 tbl, 5 ex

FIELD: electronic engineering; high-power microwave transistors and small-scale integrated circuits built around them.

SUBSTANCE: proposed method for producing high-power microwave transistors includes formation of transistor-layout semiconductor wafer on face side, evaporation of metals, application and etching of insulators, electrolytic deposition of gold, formation of grooves on wafer face side beyond transistor layout for specifying transistor chip dimensions, thinning of semiconductor wafer, formation of grooves on wafer underside just under those on face side, formation of through holes for grounding transistor leads, formation of integrated heat sinks for transistor chips around integrated heat sink followed by dividing semiconductor wafer into transistor chips by chemical etching using integrated heat sinks of transistor chips as mask.

EFFECT: enhanced power output due to reduced thermal resistance, enhanced yield, and facilitated manufacture.

2 cl, 1 dwg, 1 tbl

FIELD: technologies for making transistors.

SUBSTANCE: method includes following stages: precipitation of electric-conductive material on substrate of semiconductor material, forming of shape of first parallel band electrodes with step, determined by appropriate construction rules, while areas of substrate in form of stripes between first electrodes are left open, precipitation of barrier layer, covering first electrodes down to substrate, alloying of substrate in open areas, precipitation of electric-conductive material above alloyed areas of substrate with forming of second parallel band electrodes, removal of barrier layer, near which vertical channels are left, passing downwards to non-alloyed areas of substrate between first and second electrodes, alloying of substrate in open areas of lower portion of channels, filling channels with barrier material, removal of first electrodes, during which gaps between second electrodes are left and substrate areas are opened between them, alloying of open areas of substrate in gaps, from which first electrodes were removed, removal of electric-conductive material in said gaps for restoration of first electrodes and thus making an electrode layer, containing first and second parallel band electrodes of practically even width, which are adjacent to alloyed substrate and separated from each other only by thin layer of barrier material, while, dependent on alloying admixtures, used during alloying stages, first electrodes form source or discharge electrodes, and second electrodes - respectively discharge or source electrodes of transistor structures, precipitation of insulating barrier layer above electrodes and separating barrier layers. Precipitation of electric-conductive material above barrier layer and forming in said electric-conductive material of shape of parallel band valve electrodes, directed transversely to source and discharge electrodes, thus receiving structures matrix for field transistors with very short channel length and arbitrarily large width of channel, determined by width of valve electrode.

EFFECT: ultra-short channel length of produced transistors.

11 cl, 17 dwg

The invention relates to methods of manufacturing field-effect transistors with the structure of a metal-oxide-semiconductor - MOSFETs
The invention relates to microelectronics, and is intended for the manufacture of p-channel MOS LSI with a high voltage level

The invention relates to semiconductor technology and can be used in the manufacture of Schottky field-effect transistors

FIELD: technologies for making transistors.

SUBSTANCE: method includes following stages: precipitation of electric-conductive material on substrate of semiconductor material, forming of shape of first parallel band electrodes with step, determined by appropriate construction rules, while areas of substrate in form of stripes between first electrodes are left open, precipitation of barrier layer, covering first electrodes down to substrate, alloying of substrate in open areas, precipitation of electric-conductive material above alloyed areas of substrate with forming of second parallel band electrodes, removal of barrier layer, near which vertical channels are left, passing downwards to non-alloyed areas of substrate between first and second electrodes, alloying of substrate in open areas of lower portion of channels, filling channels with barrier material, removal of first electrodes, during which gaps between second electrodes are left and substrate areas are opened between them, alloying of open areas of substrate in gaps, from which first electrodes were removed, removal of electric-conductive material in said gaps for restoration of first electrodes and thus making an electrode layer, containing first and second parallel band electrodes of practically even width, which are adjacent to alloyed substrate and separated from each other only by thin layer of barrier material, while, dependent on alloying admixtures, used during alloying stages, first electrodes form source or discharge electrodes, and second electrodes - respectively discharge or source electrodes of transistor structures, precipitation of insulating barrier layer above electrodes and separating barrier layers. Precipitation of electric-conductive material above barrier layer and forming in said electric-conductive material of shape of parallel band valve electrodes, directed transversely to source and discharge electrodes, thus receiving structures matrix for field transistors with very short channel length and arbitrarily large width of channel, determined by width of valve electrode.

EFFECT: ultra-short channel length of produced transistors.

11 cl, 17 dwg

FIELD: electronic engineering; high-power microwave transistors and small-scale integrated circuits built around them.

SUBSTANCE: proposed method for producing high-power microwave transistors includes formation of transistor-layout semiconductor wafer on face side, evaporation of metals, application and etching of insulators, electrolytic deposition of gold, formation of grooves on wafer face side beyond transistor layout for specifying transistor chip dimensions, thinning of semiconductor wafer, formation of grooves on wafer underside just under those on face side, formation of through holes for grounding transistor leads, formation of integrated heat sinks for transistor chips around integrated heat sink followed by dividing semiconductor wafer into transistor chips by chemical etching using integrated heat sinks of transistor chips as mask.

EFFECT: enhanced power output due to reduced thermal resistance, enhanced yield, and facilitated manufacture.

2 cl, 1 dwg, 1 tbl

FIELD: electricity.

SUBSTANCE: manufacturing method of microwave transistor with control electrode of T-shaped configuration of submicron length involves formation on the front side of semi-insulating semi-conductor plate with active layer of the specified structure of a pair of electrodes of transistor, which form ohmic contacts by means of lithographic, etching method and method of sputtering of metal or system of metals, formation of transistor channel by means of electronic lithography and etching, application of masking dielectric layer, formation in masking dielectric layer of submicron slot by means of electronic lithography and etching; at that, submicron slot is formed with variable cross section decreasing as to height from wide upper part adjacent to the head of the above control electrode to narrow lower part adjacent to transistor channel, formation of topology of the above control electrode by means of electronic lithography method, formation of the above control electrode in submicron slot by means of sputtering of metal or system of metals; at that, configuration of its base repeats configuration of submicron slot. During formation of submicron slot with variable cross section in masking dielectric layer, which decreases throughout its height, by means of electronic lithography and etching, the latter of masking dielectric layer is performed in one common production process in high-frequency plasma of hexafluoride of sulphur, oxygen and helium and discharge power of 8-10 W.

EFFECT: increasing output power and amplification factor, increasing reproducibility of the above output parametres and therefore yield ratio, simplifying and decreasing labour input for manufacturing process.

2 cl, 1 dwg, 1 tbl, 5 ex

FIELD: electricity.

SUBSTANCE: field transistor manufacturing method includes creation of source and drain contacts, active area identification, application of a dielectric film onto the contact layer surface, formation of a submicron chink in the dielectric film for the needs of subsequent operations of contact layer etching and application of gate metal through the resistance mask; immediately after the dielectric film application one performs lithography for opening windows in the dielectric at least one edge whereof coincides with the Schottky gates location in the transistor being manufactured; after the window opening a second dielectric layer is applied onto the whole of the surface with the resistance removed; then, by way of repeated lithography, windows in the resistance are created, surrounding the chinks formed between the two dielectrics; selective etching of the contact layer is performed with metal films sprayed on to form the gates.

EFFECT: simplification of formation of under-gate chinks sized below 100 nm in the dielectric.

6 dwg

FIELD: electricity.

SUBSTANCE: method for UHF high-power transistors manufacturing includes formation of transistor topology semiconductor substratum on the face side by electronic lithography and photolithography methods, metals spraying on, dielectrics application and etching, cathodic electrodeposition of gold, formation of preset size grooves on the face side outside the transistor topology, substrate thinning, formation of grounding through holes for the transistors source electrodes, formation of a common integrated heat sink, formation of a integrated heat sink for each transistor crystal, semiconductor substrate division into transistor crystals; one uses a semiconductor substrate with the preset structure of active layers having two stop layers with the preset distance between them, the stop layers ensuring minimum thermal resistance; the semiconductor substrate reverse side thinning is performed down to the stop-layer located close to such side; grounding through holes are formed immediately on the source electrodes with the common integrated heat sink thickness is set by the type of the transistor crystal subsequent mounting.

EFFECT: enhanced output capacity through reduction of thermal resistance, parasitic of the electric resistance in series and source electrodes grounding inductance; increased yield ratio, repeatability and functionalities extension.

4 cl, 1 dwg, 1 tbl

FIELD: electrical engineering.

SUBSTANCE: method for manufacture of a powerful UHF transistor includes formation of the topology of at least one transistor crystal on the semiconductor substrate face side, formation of the transistor electrodes, formation of at least one protective dielectric layer along the whole of the transistor crystal topology by way of plasma chemical application, the layer total length being 0.15-0.25 mcm, formation of the transistor crystal size by way of lithography and chemical etching processes. Prior to formation of the transistor crystal size, within the choke electrode area one performs local plasma chemical etching of the protective dielectric layer to a depth equal to the layer thickness; immediately after that one performs formation of protectively passivating dielectric layers of silicon nitride and diozide with thickness equal to 0.045-0.050 mm; plasma chemical application of the latter layers and the protective dielectric layer is performed in the same technological modes with plasma power equal to 300-350 W, during 30-35 sec and at a temperature of 150-250°C; during formation of the transistor crystal size ne performs chemical etching of the protectively passivating dielectric layers and the protective dielectric layer within the same technological cycle.

EFFECT: increased power output and augmentation ratio or powerful transistors with their long-term stability preservation.

4 cl, 1 dwg, 1 tbl

FIELD: electricity.

SUBSTANCE: semiconductor device comprises a thinned substrate of single-crystal silicon of p-type conductivity, oriented according to the plane (111), with a buffer layer from AlN on it, above which there is a heat conducting substrate in the form of a deposited layer of polycrystalline diamond with thickness equal to at least 0.1 mm, on the other side of the substrate there is an epitaxial structure of the semiconducting device on the basis of wide-zone III-nitrides, a source from AlGaN, a gate, a drain from AlGaN, ohmic contacts to the source and drain, a solder in the form of a layer including AuSn, a copper pedestal and a flange. At the same time between the source, gate and drain there is a layer of an insulating polycrystalline diamond.

EFFECT: higher reliability of a semiconducting device and increased service life, makes it possible to simplify manufacturing of a device with high value of heat release from an active part.

3 cl, 7 dwg

FIELD: physics.

SUBSTANCE: invention relates to semiconductor technology. Proposed method comprises removal of photoresist from at least one surface of conducting layer with the help of the mix of chemical including first material of self-optimising monolayer and chemical to remove said photoresist. Thus self-optimising monolayer is deposited on at least one surface of said conducting ply. Semiconductor material is deposited on self-optimising monolayer applied on conducting layer without ozone cleaning of conducting layer.

EFFECT: simplified method.

15 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: method for manufacture of powerful SHF transistor includes application of a solder layer to the flange, shaping of pedestal, application of a sublayer fixing the transistor crystal to the pedestal, formation of p-type conductivity oriented at the plane (111) at the base substrate of single-crystalline silicon and auxiliary epitaxial layers, application of the basic layer and buffer layer for growing of epitaxial structure of a semiconductor device based on wide-gap III-nitrides, application of heat conductive layer of CVD polycrystalline diamond to the basic layer, removal of the basic substrate with auxiliary epitaxial layers up to the basic layer, growing of heteroepitaxial structure based on wide-gap III-nitrides on the basic layer and formation of the source, gate and drain. The heat conductive layer of CVD polycrystalline diamond is used as a pedestal; nickel is implanted to its surficial region and annealed. Before formation of the source, gate and drain an additional layer of insulating polycrystalline diamond and additional layers of hafnium dioxide and aluminium oxide are deposited on top of the transistor crystal; the total thickness of the above layers is 1.0-4.0 nm.

EFFECT: invention allows increased heat removal from the active part of SHF-transistor and minimisation of gate current losses.

6 cl, 4 dwg

FIELD: electronic equipment.

SUBSTANCE: invention is intended to create discrete devices and microwave integrated circuits with the help of field-effect transistors. Method of making field-effect transistor, including creation of drain and source contacts on the contact layer of semiconductor structure and extraction of active region, metal or metal and dielectric mask is applied directly on the surface of contact layer, formation of submicron slot in the mask for further etching operations of contact layer etching and application of T-shaped gate metal through resist mask, after application of the first metal mask lithography for opening windows is carried out when one of the edges coincides with location of Schottky gates in manufactured transistor, and after opening windows the second metal or dielectric mask is applied on the whole surface, remove resist and by lithography create window in resist surrounding slits formed between two metals or between metal and dielectric, perform selective etching of contact layer, after which spray metal films to form T-shaped gates. As a result, edges of T-shaped gate heads on both sides resting on metal or metal and dielectric masks. Then, via selective etching the mask is removed from under the "wings" of T-shaped gate and from the surface of transistor active area. After that, the surface of transistor active area, containing drain, source contacts and Schottky gates, is coated with a passivating layer of dielectric so that under "wings" of T-shaped gate cavities are formed filled with vacuum or gas medium.

EFFECT: technical result is production of gated with length less than 100 nm, as well as reduced thickness of the metal mask and elimination of intermediate layer of dielectric placed between the active region surface and mask.

1 cl, 1 dwg

Up!