Method for filed transistor manufacturing

FIELD: electricity.

SUBSTANCE: field transistor manufacturing method includes creation of source and drain contacts, active area identification, application of a dielectric film onto the contact layer surface, formation of a submicron chink in the dielectric film for the needs of subsequent operations of contact layer etching and application of gate metal through the resistance mask; immediately after the dielectric film application one performs lithography for opening windows in the dielectric at least one edge whereof coincides with the Schottky gates location in the transistor being manufactured; after the window opening a second dielectric layer is applied onto the whole of the surface with the resistance removed; then, by way of repeated lithography, windows in the resistance are created, surrounding the chinks formed between the two dielectrics; selective etching of the contact layer is performed with metal films sprayed on to form the gates.

EFFECT: simplification of formation of under-gate chinks sized below 100 nm in the dielectric.

6 dwg

 

The invention relates to electronic devices, and is intended to create a discrete devices or microwave integrated circuit for field-effect transistors.

There are ways to create a heterostructure field effect transistors (pseudomorphs or metamorphic) include the following set of processes: the formation of the ohmic contacts of sinks and sources on the surface of the contact layer, the allocation of the active region by etching or ion implantation, conducting electronic lithography layered mask resists for forming the gate Schottky T-shaped etching of gate slots in the contact layer, the deposition of metal films to create closures, removal of resists [1].

The disadvantage of this method is that upon receipt of the gates of the T-shaped with the length of the narrow part of the bolt smaller than 100 nm can be a separation of the gate from the semiconductor surface during the operation of removal of resists coated with the metal films.

Known methods, which addressed this shortcoming. So the known method [2] create transistors with long shutter 40 nm, with a T-shape. In a specified way at first make the selection transistor by chemical etching through a mask of the resist, and then allocated by etching the region the ti on the surface of the contact layer to form ohmic contacts of sinks and sources, then put the first layer of dielectric. With the help of electronic lithography and subsequent reactive-ion etching the dielectric layer to form gate gap of submicron size. To reduce the gate slit put the second dielectric layer, and spend another process is reactive ion etching. Conduct electronic lithography for forming the gate, through the crack in the insulator is etched groove in the contact layer, sprayed metal, and removing the resist. After deposition, the metal shutter is partially surrounded by a dielectric, which prevents its separation from the semiconductor during removal of the resist.

The closest analogue (prototype) is a method of manufacturing a heterostructure field-effect transistor, considered in [3].

In a known way to produce the selection transistor by chemical etching through a mask of the resist, and then allocated by the etching area on the surface of the contact layer to form ohmic contacts of sinks and sources, and then put the first layer of dielectric. With the help of electronic lithography and subsequent reactive-ion etching (RIT) in the dielectric layer form a gate gap submicron sizes of trapezoidal form, which must be applied only in special mode dry etching IER is ektrica. Conduct electronic lithography, through the crack in the insulator is etched groove in the contact layer, sprayed metal, and removing the resist.

The disadvantage of this method is the difficulty of obtaining slit size smaller 100 nm using reactive-ion etching dielectric after the electronic lithography.

The aim of the invention is to eliminate this drawback. The goal is due to the fact that in the known method introduce new operations and eliminates the process of reactive ion etching the first dielectric layer. The technical result is achieved by the fact that in the known method, including creating contacts the drain and the source on the contact layer of the semiconductor structure (heterostructures), highlighting the active area by etching or ion implantation), application of a film of a dielectric on the surface of the contact layer, the formation of submicron cracks in the dielectric film for the subsequent etching of the contact layer and deposition of the metal gate through a mask of the resist, after application of the first dielectric film are lithography for opening Windows in the dielectric, in which at least one of the edges coincides with the location of the Schottky gates in visitors transistor, and after opening the Windows on the entire surface is applied a second dielectric film, removing the resi is t and lithographs created by the Windows in the resist, surrounding the slit formed between the two dielectrics, carry out selective etching of the contact layer, and then sprayed film of the metals for forming the gates.

The choice of the layer thicknesses of the dielectric and the time of etching the first dielectric film, you can get the size of a gap between the first and second films of dielectrics less than 100 nm.

1 schematically shows the key moments of one of the possible variants of the proposed method of fabrication of the transistor.

In figure 1,and shows a heterostructure containing politology substrate 1 on which the grown semiconductor layers 2, necessary for the creation of the transistor, and a contact layer 3 of high-alloyed semiconductor.

In figure 1,b shows the structure after the selection transistor by etching, creating ohmic contacts of the source 4 and drain 5 and the deposition of the first dielectric layer 6.

Figure 1,shows the structure after etching Windows 7 in the first dielectric layer 6 through a mask of the resist 8.

In figure 1,g shows the structure after deposition of the second dielectric layer 9 and the removal of the resist 8.

Figure 1 d shows the structure after carrying out lithography for formation of the gate, here 10 resist.

Figure 1 e shows the structure after the selective etching of the contact layer 3, the deposition of the metal shutter 11 and removal of the resist.

Example. And sotavlyali field pseudomorphs transistor with high electron mobility (MEMT) based heterostructure AlGaAs/InGaAs. Epitaxial layers 2 and 3 were grown by molecular beam epitaxy on politology substrate of gallium arsenide 1. Contact alloyed layer 3 of gallium arsenide was grown on top of layer 2, forming the heterojunction AlGaAs/InGaAs. First conducted the selection transistor by chemical etching after an appropriate photolithography. Using standard optical lithography methods, processes, vacuum deposition and annealing was created ohmic contacts of the source 4 and drain 5 on the surface of the contact layer 3. Then the whole structure was applied film of the first dielectric layer 6 of a thickness of 0.15 μm. As a layer 6 was applied a layer of silicon dioxide (SiO2). Then there was the lithography and chemical etching has formed a window 7 in the first dielectric layer. While etching layer 6 was equal to t=1.1 h/v. Where h is the layer thickness of the first dielectric, v is the speed of etching of the dielectric. And one of the edges of the Windows 7 corresponded to the location of Schottky they are manufactured in the transistor. Without removing the resist, magnetron sputtering of silicon in the mixture of argon and oxygen was applied a second layer of SiO29 of a thickness of 0.15 μm. After removal of the resist, one part of the surface of the structure was closed layer of the first dielectric 6 and the second layer of the second dielectric 9. Between these dielectrics produces the uh slit trapezoidal shape with a minimum window size of 90 nm. Then there was the lithography for forming a gate and through a mask of the resist, in the gap between the insulators 6 and 9 is selectively etched contact layer, deposited a metal shutter 11 and removing the resist 10. Next we opened the window in the insulator 6 for galvanic increase of gold on the contacts.

Thus was achieved the goal, and the result was obtained RNENT transistor with the length of the shutter is equal to 90 nm without the use of special modes reactive ion etching through the dielectric window of the resist less than 100 nm.

Sources of information

1. Kang-Sung Lee, Young-Su Kim, Yun-Ki Hong and Yoon-Ha Jeong. IEEE ELECTRON DEVICE LETTERS, VOL.28, NO.8, AUGUST 2007, P.672-675. 35-nm Zigzag T-Gate. In0,52Al0·48As/In0·53Ga0·47As Metamorphic GaAs HEMTs With an Ultrahigh fmaxof 520 GHz.

2. Dae-Hyun Kim, Suk-Jin Kim, Young-Ho Kim, Sung-Wong Kim and Kwang-Seok Seo. 40 nm InGaAs HEMT's with 65% Strained Channel Fabricated with Damage-Free SiO2/SiNx Side-wall GateProcess // JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.3, NO.1, MARCH, 2003, P.27-32.

3. Neatorama Westenskow, VA..kraśnik Wpinegar. Patent 2390875 EN, the METHOD of MANUFACTURING of microwave TRANSISTOR WITH a control ELECTRODE of the T-SHAPED CONFIGURATION SUBMICRON LENGTH.

A method of manufacturing a field-effect transistor, which includes the creation of drain contacts and the source on the contact layer of the semiconductor structure (heterostructures), highlighting the active area by etching or ion implantation), the deposition of the dielectric film on arnosti contact layer, the formation of submicron cracks in the dielectric film for the subsequent etching of the contact layer and deposition of the metal gate through a mask of the resist, characterized in that after deposition of a dielectric film are lithography for opening in the dielectric window, in which at least one of the edges coincides with the location of the Schottky gates in visitors transistor, and after opening these Windows on the entire surface put the second dielectric layer, removing the resist and lithographs created by the Windows in the resist surrounding the slit formed between the two dielectrics, carry out selective etching of the contact layer, and then sprayed film of the metals for forming gates.



 

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