Semiconductor device and display device

FIELD: electricity.

SUBSTANCE: semiconductor device comprises multiple transistors with a channel of n-type, at the same time the circuit comprises the following: from multiple transistors, a transistor (T1), including a contact outlet of a drain to receive voltage VDD, a contact outlet of a source and a contact outlet of a gate to receive an inlet signal (IN); from multiple transistors, a transistor (T2), comprising a contact outlet of a drain to receive voltage VDD, a contact outlet of a source connected to an exit contact outlet (OUT), and a contact outlet of a gate connected to a contact outlet of a transistor (T1) source; and a capacitor (C1), represented between a unit (n1) and a contact outlet (CK) of a sync signal to receive a sync signal. A sync signal introduced into a contact outlet (CK) of a sync signal has a frequency higher than frequency of an outlet signal taken out of an exit contact outlet.

EFFECT: prevention of a lower level of signal electric potential.

11 cl, 47 dwg

 

The technical field to which the invention relates

The present invention relates to a semiconductor device that includes transistors of the same type conductivity.

The level of technology

The liquid crystal display device includes the exciting circuit line signal scan and the exciting circuit of the line of data signals, each of which includes an impedance shift to signal for sequential excitation of the pixels in the layout matrix. Additionally, the liquid crystal display device includes: a module level shift to convert the voltage level of the power supply and buffer, which has a low output impedance, and outputs the signal amplification in a broad sense, for example, amplification circuitry to output the signal, which has a 100% gain relative to the input signal. In the case where a CMOS transistor is used to create a semiconductor device such as an impedance shift or buffer, processes for forming the channel of the p-type and n-type channel, respectively, shall be required, thereby complicating the manufacturing process of the semiconductor device. Therefore, in order to simplify the manufacturing process of the semiconductor device preferably is to use a transistor of one type conductivity, such as a transistor with unipolar type conductivity channel (for example, a transistor with channel p-type). For example, patent literature 1 discloses a semiconductor device composed of such unipolar transistors.

Fig is a schematic diagram illustrating a layout of a semiconductor device disclosed in patent literature 1. This semiconductor device is composed of MOS transistors are n-type.

In particular, the semiconductor device 100 includes four MOS transistor T101-T104 n-type and a capacitor C101. The transistor T101 is located so that its contact pin drain connected to the source of the VDD supply and its contact output gate connected to the input contact to the output IN. The transistor T103 is located so that its pin output source connected to the source of the VSS power supply, and contact output of gate receives the STOP signal (stop) (control signal). The transistor T102 is located so that its contact pin drain is connected to the terminal of the clock φ, and the contact output of the gate is connected to (i) contact output source transistor T101 and (ii) contact output drain of the transistor T103. The transistor T104 is such that (i) contact output drain is connected to the terminal of the source of the transistor T102, (ii) the contact in the water source connected to the source of the VSS power supply, and (iii) contact output gate is connected to the terminal of the transistor T103. The connection point between the transistors T101, T102 and T103 is a node N1, and the connection point between the transistors T102 and T104 is the node N2. The capacitor C101 is provided between nodes N1 and N2. The node N2 is connected to the output contact output OUT.

Next, the following description explains the operation of semiconductor device 100. Fig is a timing chart showing the forms of various signals of the semiconductor device 100.

When the input signal IN switches to the high level, the transistor T101 is turned on and the electric potential at the node N1 is increased to "VDD-Vth (where Vth is the threshold voltage of the transistor T101)" (pre-charging). Because the electric potential at the node N1 increases, the transistor T102 is included. Here, if the synchronization signal φ is at a low level, the signal having a low level is output from the output contact output OUT. After the electric charge is pre-charged, the electric potential at the node N1 is kept up until the STOP signal does not enter the active state (high level) (high-impedance state). If the synchronization signal φ is switched to a high level in this high impedance state, the electric potential at the node N1 manufacture is concentrated in the electric potential of α up to "VDD-Vth+α" as a result of the capacitor C101 (operation compensatory feedback). During the time period in which the electric potential exceeds the "VDD+Vth, the signal having the level electric potential VDD outputted from the output contact output OUT.

Then, when the STOP signal is switched to high level, the electric potential at the node N1 is discharged to VSS through transistor T103, so that the transistor T102 is turned off. The transistor T104 is included, so that a signal having a level of the electric potential VSS is output from the output contact output OUT.

Thus, when the layout of the conventional semiconductor device can output a signal having a high electric potential, using a simple schematic layout through the use of the advantages of the operation of the compensation feedback. Consequently, it is possible to use such a semiconductor device properly in the nodes of the liquid crystal display device.

The list of bibliographic references

Patent literature 1

The Japan patent number 3092506 B (date of registration: 28 July 2000)

The invention

However, the conventional semiconductor device, comprising transistors of the same type conductivity, for example, as described above, has such a problem that the electric potential of the output signal gradually ponijao the camping due to leakage current in off state (low current, seeping from the transistor at the time when the transistor is in the off state), etc. Additionally, the decrease of the electric potential causes the output signal to have a high impedance so that the output signal is subject to noise. This leads to a false positive in the subsequent circuit that receives an output signal. In particular, for example, if the semiconductor device is used as a circuit line selection signals to the scanning module, the sliding resistance provided in the liquid crystal display device, there is a risk that the output signal is subject to noise, thereby causing such false positive that the subsequent operation of the selection signal lines of the scanning is not performed accurately.

Here, the following description explains how the output signal is subject to noise due to lower electrical potential in the conventional semiconductor device. Fig shows the waveform for the output signal that is affected by the leakage current in the off state and the like, whose waveform is shown by dashed lines.

For example, in the semiconductor device 100 electric charge, pre-charge the node N1 is discharged through the impact of leakage current in off status is anii transistor T103 and the like, so the electric potential at the node N1 is gradually reduced (see the dotted line of the node N1 at Fig). Then, if the electric potential at the node N1 is reduced to "VDD+Vth" at a time when the synchronization signal φ is at a high level (VDD), the transistor T102 is turned off. This causes the output signal of the transistor T102 to have a high impedance so that the output signal OUT becomes susceptible to noise.

In addition, if the electric potential at the node N1 additionally drops below VDD, since the transistor T102 is in the off state, the level of electric potential of the output signal OUT is reduced due to, for example, the leakage current in the off state of the transistor T104 and the like, as shown by dotted lines in Fig. This may result in false positive in the following schema.

As described above, the electric potential at the node N1 decreases due to leakage current in the off state, etc. For this reason, for example, if the synchronization signal φ is low in frequency, or if the period of time to save (hold) electric charge at the node N1 is long, the electric potential at the node N1 is decreased even more. Consequently, the output signal has a high impedance, thereby becoming susceptible to noise.

The present invention is the implementation of the Leno taking into account the problems. The purpose of the present invention is to provide a semiconductor device composed of transistors of one type conductivity, and the semiconductor device can output a stable signal by preventing reduction of the level of electric potential signal; and a display device that includes a semiconductor device.

In order to achieve the objective, the semiconductor device of the present invention is composed of a set of transistors of one type conductivity, and the semiconductor device includes: multiple transistors, the first transistor including first terminals for receiving a voltage switching, the second terminals and the control terminals for receiving input signals from a variety of transistors, the second transistor including first terminals for receiving a voltage switching, the second contact pin connected to the output terminal output, and control terminals connected to the second contact to the conclusion of the first transistor; and a capacitor provided between the connection point between the first transistor and the second transistor, and the contact output clock for the reception of the synchronization signal and the synchronization signal has a frequency above the frequency of the output of the second signal, the output from the output contact output.

The transistor is a circuit that includes a first contact pin, a second contact pin and control pin output. When the control pin output control signal, the first terminals and the second terminals are electrically connected to each other. Therefore, the circuit outputs a signal having a desired level of electric potential through the first and second contact pins. The control signal is a voltage (signal level: VDD) to turn on the transistor when the control signal is entered to the control terminals, and the voltage level signal VSS) to turn off the transistor when the control signal is entered into the control pin output.

Here, as described above, in the conventional semiconductor device, the electric potential at the node connected to the control contact output transistor output signal having the desired level of electrical potential, in General, gradually decreases due to the leakage current in the off state, etc.

Given this problem, the semiconductor device of the present invention has such an arrangement that the synchronization signal having a frequency higher than the frequency of the output signal, is introduced through the capacitor node connected to operated is interested contact output transistor output signal, having the desired level of electric potential, i.e. the connection point (node) between the first and second transistors.

With this arrangement, the electric potential at the node increases the electric potential of α by means of the synchronization signal and a capacitor, and then, for example, is reduced by the electric potential of β up to "VDD-Vth+α-β (where Vth is the threshold voltage of the first transistor)due to leakage current in the off state, etc. After that, when the synchronization signal is switched to the low level (VSS), the electric potential at the node is reduced to "VDD-Vth-β". However, here, if the input signal is at a high level (VDD), the electric potential at the node is charged up to "VDD-Vth". Then, when the synchronization signal is switched to high level again, the electric potential at the node increases again to "VDD-Vth+α".

Thus, in the layout of semiconductor devices the operation of increasing is performed in accordance with the cycle clock having a frequency higher than the frequency of the output signal. Therefore, even if the electric potential at the node decreases due to leakage current in the off state and the like, the electric potential can be charged back through promotion. This gives the possibility of increasing electric potential with a period less period for Trad the traditional layout. Consequently, it is possible to stabilize the level of electric potential of the output signal and the subsequent work circuit which receives an output signal.

Additionally, by setting the amplitude of the synchronization signal and the capacitor so that the increased electric potential (VDD-Vth+α) in the node is not less than VDD+Vth (where Vth is the threshold voltage of the second transistor)", it becomes possible to maintain the electrical output signal level on VDD.

In addition, since a signal having a high electric potential is introduced to the control terminals of the second transistor, the output signal may have a low impedance and can be stable against noise.

The semiconductor device of the present invention preferably additionally includes many transistors, the third transistor comprising a first contact pin connected to the connection point, the second contact pin for receiving the voltage-off and control terminals for receiving the control signal.

With this arrangement, when the third transistor is switched by the control signal, the electric potential at the node can be successfully reduced to VSS.

The semiconductor device of the present invention preferably additionally includes: sets the transistors of the fourth transistor, includes first terminals connected to the output contact output, the second contact pin for receiving the voltage-off and control terminals for receiving the control signal.

With this arrangement, if the third and fourth transistors are enabled by the control signal, the electric potential at the node can be successfully reduced to VSS and the level of electric potential of the output signal can be stabilized at a low level (voltage off-VSS).

The semiconductor device of the present invention preferably additionally includes many transistors, the fifth transistor including first terminals for receiving a voltage switching, the second contact pin connected to the connection point, and a control terminals connected to the output terminal output.

This layout output signal is introduced to the control terminals of the fifth transistor. Therefore, even if the electric potential at the node decreases due to leakage current in the off state and the like, provided that the input signal is at a low level and the first transistor is in the off state, the electric potential at the node can be charged again up to "VDD-Vth" during the period of time, in which the output signal is at the high level switching voltage-VDD).

Consequently, the electric potential at the node may be increased up to "VDD-Vth+α" during the time period in which the synchronization signal is at a high level. Therefore, it becomes possible to more successfully to stabilize the level of electric potential of the output signal.

The semiconductor device of the present invention preferably additionally includes many transistors sixth transistor that outputs the input signal, while the sixth transistor includes a first contact pin connected to the input contact to the output; a second contact pin connected to the control pin to the output of the first transistor and the output terminal output, and control terminals for reception of the permission signal.

With this arrangement, once the enable signal is switched to high level, regardless of switches or not the enable signal to the low level later, you can save the input signal being at a high level, the control terminals of the first transistor during a time period in which the output signal is at a high level. Consequently, it is possible to stably maintain the active state of the semiconductor device is STV.

The semiconductor device of the present invention preferably additionally includes many transistors seventh transistor comprising a first contact pin connected to the connection point, the second contact pin for receiving the voltage-off and control terminals for receiving the initialization signal for the stabilization of the initial state of the semiconductor device.

With this arrangement, the initialization signal being at a high level, is introduced into the seventh transistor in the initial state, so that the electric potential at the node can be stabilized at VSS. Consequently, it is possible to stabilize the initial state.

The semiconductor device of the present invention preferably additionally includes many transistors eighth transistor comprising a first contact pin connected to the terminal of the synchronization signal, the second contact pin connected to the end of the capacitor, and a control terminals for receiving the input signal.

With this arrangement, by controlling the on/off state of the eighth transistor can be electrically separate contact output clock and a capacitor connected to the node, from each other. This may cause the load con the akt output clock to be only the parasitic capacitance of the eighth transistor. Consequently, it is possible to reduce power consumption by reducing the required driving ability of the circuit to the excitation contact of the output clock and reduce capacity.

In order to achieve the objective, the semiconductor device of the present invention is composed of a set of transistors of one type conductivity, and the semiconductor device includes: multiple transistors, the first transistor including first terminals for receiving a voltage switching, the second terminals and the control terminals for receiving input signals from a variety of transistors, the second transistor including first terminals for receiving a voltage switching, the second contact pin connected to the output terminal output, and control terminals connected to the second contact to the conclusion of the first transistor; a capacitor provided between a connection point between the first transistor and the second transistor, and the contact output clock reception clock; many transistors tenth transistor comprising a first contact pin connected to the connection point of the second terminals and the control terminals for receiving a voltage; and from a variety of transistor t the th transistor, includes the first contact pin connected to the second contact to the conclusion of the tenth transistor, the second contact pin for receiving the voltage-off and control terminals for receiving the control signal and the synchronization signal has a frequency higher than the frequency of the output signal output from the output contact output.

The electric potential at the node by increasing clock so that a high voltage is applied to each of the transistors connected to the node. Therefore, there is a risk that this transistor is broken due to a higher voltage than its withstand voltage.

The semiconductor device described above, includes a tenth transistor between the node and the third transistor. This can reduce the electric potential, for example, in the third transistor (details of this effect are described below). Consequently, it is possible to create reliable scheme.

In the semiconductor device of the present invention the synchronization signal preferably shows such a waveform that the high level and low level are repeated alternately and periodically, and the synchronization signal is set so that the time period of the low level in one cycle is equivalent to the period of time from the time when the synchronization signal switch which differs from the high level to the low level, until the time when the electric potential at the connection point is saturated.

This can reduce the impedance of the output signal while maintaining the active state of the semiconductor device.

Display device of the present invention includes any one of the semiconductor devices described above.

Consequently, it is possible to provide a display device which can output a stable signal by preventing reduction of the level of electric potential.

It should be noted that the display device of the present invention preferably is a liquid crystal display device.

Additional objectives, features and effects of the present invention should become apparent through the following description. Additionally, the advantages of the present invention will be apparent from the following explanation with reference to the drawings.

Brief description of drawings

Figure 1 is a schematic diagram illustrating the layout of the circuit in accordance with embodiment 1 of the present invention.

Figure 2 is a time chart showing the forms of various signals of the circuit illustrated in figure 1.

3 is a timing chart showing the forms of various signals of the circuit illustrated in figure 1, if the J. influence of the leakage current in the off state, etc.

Figure 4 is a timing chart showing the forms of various signals of the traditional scheme if the scheme is affected by the leakage current in the off state, etc.

5 is a timing chart showing the forms of various signals of the circuit illustrated in figure 1, if the synchronization signal φ is introduced into the contact pin drain of the transistor T2.

6 is a schematic diagram illustrating the layout of the circuit in accordance with embodiment 2 of the present invention.

7 is a timing chart showing the forms of various signals of the circuit shown in Fig.6.

Fig is a schematic diagram illustrating the layout of the circuit in accordance with embodiment 3 of the present invention.

Fig.9 is a schematic diagram illustrating the layout of the circuit in accordance with embodiment 4 of the present invention.

Figure 10 is a time chart showing the forms of various signals of the circuit shown in Fig.9.

11 is a schematic diagram illustrating another arrangement of the transistor T6 in the scheme illustrated in Fig.9.

Fig is a schematic diagram illustrating another alternate arrangement of the transistor T6 in the scheme illustrated in Fig.9.

Fig is a schematic diagram, illustrious the layout of the circuit in accordance with embodiment 5 of the present invention.

Fig is a schematic diagram illustrating the layout of the circuit in accordance with embodiment 6 of the present invention.

Fig is a schematic diagram illustrating another layout of the circuit illustrated in Fig.

Fig is a schematic diagram illustrating the layout of the circuit in accordance with embodiment 7 of the present invention.

Fig is a schematic diagram illustrating another layout of the circuit in accordance with embodiment 7 of the present invention.

Fig is a schematic diagram illustrating a layout that transistor T1 is diode inclusion in the scheme illustrated in figure 1.

Fig is a schematic diagram illustrating a layout that transistor T1 is diode inclusion in the scheme illustrated in Fig.6.

Fig is a schematic diagram illustrating a layout that transistor T1 is diode inclusion in the scheme illustrated in Fig.

Fig is a schematic diagram illustrating a layout that transistor T1 is diode inclusion in the scheme illustrated in Fig.9.

Fig is a schematic diagram illustrating a layout that transistor T1 is diode inclusion in the scheme illustrated in Fig.

Fig is principled the Hema, illustrating this arrangement, the transistor T1 is diode inclusion in the scheme illustrated in Fig.

Fig is a schematic diagram illustrating a layout that transistor T1 is diode inclusion in the scheme illustrated in Fig.

Fig is a timing chart showing the forms of the various signals illustrated in Fig.

Fig is a view showing the shape of the clock CK of each of the embodiments of the present invention.

Fig is a block diagram illustrating a complete layout of the liquid crystal display device in accordance with one embodiment of the present invention.

Fig is a block diagram illustrating the layout of a memory circuit in accordance with example 1 of the present invention, and a memory circuit is provided in CS-shaper.

Fig is a schematic diagram illustrating the layout of the memory circuit illustrated in Fig.

Fig is a timing chart showing the forms of various signals of the memory circuit illustrated in Fig.

Fig is a schematic diagram illustrating the layout of the inverter for the formation of the inverted signal INB based on the input signal in a storage scheme is illustrated in Fig.

Fig is a schematic diagram, illustrating another layout of the inverter for the formation of the inverted signal INB based on the input signal in a storage scheme is illustrated in Fig.

Fig is a block diagram illustrating the layout of a buffer circuit in accordance with example 2 of the present invention.

Fig is a schematic diagram illustrating the arrangement of the buffer circuit illustrated in Fig.

Fig is a block diagram illustrating a layout that the inverter composed of a compensation scheme feedback buffer circuit illustrated in Fig.

Fig is a schematic diagram illustrating the arrangement of the buffer circuit illustrated in Fig.

Fig is a block diagram illustrating the layout of a buffer circuit in accordance with example 3 of the present invention.

Fig is a schematic diagram illustrating a layout that the inverter composed of a compensation scheme feedback buffer circuit illustrated in Fig.

Fig is a block diagram illustrating the layout of a buffer circuit in accordance with example 4 of the present invention.

Fig is a schematic diagram illustrating the arrangement of the buffer circuit illustrated in Fig.

Fig is a block diagram illustrating the layout of a modular scheme in accordance with approx the rum 4 of the present invention, the modular scheme module is resistance to shear.

Fig is a block diagram illustrating another layout of the modular scheme, illustrated in Fig, and modular scheme module is resistance to shear.

Fig is a block diagram illustrating one another layout modular scheme, illustrated in Fig, and modular scheme module is resistance to shear.

Fig is a schematic diagram illustrating a layout that the scheme is illustrated in Fig composed of transistors with a channel of p-type.

Fig is a timing chart showing the forms of the various signals illustrated in Fig: (a) on Fig shows a waveform if VSS is introduced into the terminals of the source of the transistor T2'; and (b) on Fig shows waveforms in the case of the dot clock φ is introduced into the terminals of the source of the transistor T2'.

Fig is a schematic diagram illustrating a layout of the conventional semiconductor device.

Fig is a timing chart showing the forms of various signals in the semiconductor device illustrated in Fig.

List of links

1 - storage scheme

2, 3, 4 - buffer scheme

5 - modular scheme module (resistance to shear)

10, 20, 30, 40, 50, 60, 70 - circuit (semiconductor device)

11, 21, 31, 41, 51, 61, 71 - circuit (semiconductor device)

T1 - transistor (first transistor)

T2 - transistor (second transistor)

T3 - transistor (third transistor)

T4 - transistor (fourth transistor)

T5 - transistor (fifth transistor)

T6 - transistor (sixth transistor)

T7 - transistor (seventh transistor)

T8 - transistor (eighth transistor)

T9 - transistor (ninth transistor)

T10 - transistor (tenth transistor)

151 - liquid crystal display device (display device)

n1, n2, n3, n4, n5, n6 node

100 - semiconductor device

Description of embodiments

Embodiments of the present invention are described below with reference to Figure 1-45.

Preservation scheme (retention) active signal (hereinafter in this document, this scheme is referred to as a "scheme" for ease of explanation, the corresponding semiconductor device of the present invention, consists of transistors of one type conductivity, i.e. transistors with unipolar type channel transistor with a channel of n-type or p-type). In each of the embodiments described below, the transistors are n-type channel is used as an example. Layout using transistors with a channel of p-type is mentioned only at the end of the description of embodiments, the detailed explanation of such a configuration is omitted in the present description of the invention. The unipolar transistor with a channel type may be a TFT or field-effect transistor in the form of a silicon wafer.

(The first version of the implementation)

The following description explains the layout of the circuit 10 of this variant implementation. Figure 1 is a schematic diagram illustrating the layout of the circuit 10, and Figure 2 is a time chart showing the forms of various signals of the circuit 10.

The circuit 10 includes a transistor T1 (the first transistor), a transistor T2 (a second transistor), the transistor T3 (third transistor) and a capacitor C1. At one end of the capacitor C1 is injected signal CK having a frequency higher than the frequency of the output signal OUT of the circuit 10. Later in this document, a voltage (signal level), which includes a transistor, when applied to the terminal gate (Manager contact output), referred to as "voltage turn on (enable)and a voltage (signal level), which turns off the transistor when applied to the terminal gate, referred to as "voltage turn off (disable)". For a transistor with a channel of n-type turn-on voltage is a high voltage level of the enable is high level), and the voltage shutdown - low voltage (off level is low). On the other hand, for a transistor with channel p-type napauneley - it is low voltage, and voltage disconnect is high voltage.

As illustrated in figure 1, the transistor T1 is set so that its contact output drain (first terminals) is connected to the source of the VDD supply and its contact pin shutter (control terminals) is connected to the input contact to the output IN. The transistor T2 is such that (i) contact output drain (first terminals) is connected to the source of the VDD supply, (ii) contact output gate (control terminals) is connected to the terminal of the source of the transistor T1 and (iii) contact output source (second terminals) connected to the output contact output OUT.

The transistor T3 is set so that its contact output drain (first terminals) is connected to the terminal of the source of the transistor T1, the terminal of the transistor T2 and the terminal CK of the clock through the capacitor C1. The connection point between the transistors T1, T2 and T3 and the capacitor C1 is node n1.

Thus, unlike the conventional circuit (semiconductor circuit 100), illustrated in Fig, the circuit 10 of this variant implementation has such a layout that the synchronization signal CK having a frequency higher than the frequency of the output signal OUT, is introduced into one end of the capacitor C1, and the other the second end of the capacitor C1 is connected to the node n1, which holds the signal with a high level in the high impedance state. With this arrangement, it becomes possible to maintain the level of electric potential, so as to output a stable signal, which is almost not affected by the noise. The following description specifically explains this effect along with the operation of the circuit 10 with reference to Figure 2. It should be noted that the signals in the circuit 10, the input signal and the output signal have the electric potential VDD, when they are at a high level, and have the electric potential VSS (zero)when they are at a low level, unless otherwise noted.

When the input signal IN switches to the high level (VDD), the transistor T1 turns on and the electric potential at the node n1 is increased to "VDD-Vth (where Vth is the threshold voltage of the transistor T1)" (pre-charging). When the electric potential at the node n1 increases, the transistor T2 turns on. When the input signal IN switches from the high level to the low level (VSS), the node n1 becomes high-impedance state while maintaining the electric charge high level. In this state, if the synchronization signal CK switches to high level, the electric potential at the node n1 rises to an electric potential of α up to "VDD-Vth+α" due to the clock CK. If this electrical potential exceeds the "VDD+Vth", transisto the T2 outputs VDD to the output terminals OUT.

As described above, the signal having a high electric potential, is introduced into the contact pin of the transistor T2 at a time when the electric potential at the node n1 is increased by clock CK. Therefore, the transistor T2 outputs a signal having a level electric potential VDD, to the output terminals OUT, and at the same time, the output impedance decreases (period t in figure 2).

After that, when the STOP signal is switched to high level, the transistor T3 turns on, the electric charge of the node n1 is discharged. As a result, the transistor T2 is turned off. This causes the output terminals OUT to be in the high impedance state (see the area indicated by oblique lines in figure 2).

Thus, during the period of time up until the STOP signal is not switched to the high level, the output terminals OUT normally outputs to VDD until the electric potential at the node n1 is increased by clock CK, not fall below VDD+Vth", due to leakage current in the off state of the transistor T3, etc.

Additionally, as shown in figure 2, the electric potential at the node n1 increases through promotion by clock CK when the input signal IN, which is at a high level, is introduced, and the node n1 is pre-charged. sledovatelno, the output signal is rising rapidly (see the area surrounded by the dashed line), thereby leading to a greater rate of excitation.

Here, the following description explains the operation of the circuit 10 if the circuit 10 is affected by the leakage current in the off state and the like, compared with the layout of the traditional scheme. 3 is a timing chart showing the forms of various signals of the circuit 10, when the circuit 10 is affected by the leakage current in the off state, etc. 4 is a timing chart showing the forms of various signals of the conventional circuit illustrated in Fig, if in the traditional scheme is affected by the leakage current in the off state, etc.

In the traditional scheme, illustrated in Fig, if the node N1 has a leakage pathway, the electric potential at the node N1 gradually decreases during the time period in which the synchronization signal φ is at a high level. Here, if the electric potential at the node N1 is reduced to "VDD-Vth" or less due to the leak, the electric potential at the node N1 is charged only up to "VDD-Vth" (see the area surrounded by the dashed line in figure 4), even if the input signal IN switches to the high level again. Therefore, the output signal has a high impedance, thereby becoming susceptible to noise. Addi is entrusted, if the output signal has a leak, the electric potential at the node N2 increases only up to "VDD-2×Vth, even if the node N2 recharged. For this reason, the allowable operating margin of a subsequent circuit connected to the output contact output OUT falls.

On the other hand, in the circuit 10 of this variant implementation, if the electric potential at the node n1 is increased by clock CK and then lowered electric potential of β due to leakage, the electric potential at the node n1 becomes "VDD-Vth+α-β". Then, when the synchronization signal CK switches to the low level, the electric potential at the node n1 is reduced to "VDD-Vth-β". However, at this stage, if the input signal IN is at high level, the electric potential of the node n1 is charged up to "VDD-Vth". Therefore, when the synchronization signal CK switches to a high level again, the electric potential at the node n1 rises to "VDD-Vth+α" (see the area surrounded by the dotted line in figure 3). Consequently, it is possible to maintain a stable electric potential VDD, even if the output signal has a leak, etc. Accordingly, a subsequent circuit connected to the output signal can stably be controlled. Additionally, since the signal having a high electric potential, is introduced into the contact pin of the transistor T2, the output signal is al OUT can maintain a low impedance and can be stable against noise.

Thus, in the layout of the circuit 10 of this variant implementation can charge electric potential at the node n1 to "VDD-Vth" again, even if the output signal OUT has a leak, etc. Because the sampling clock CK is set to be higher than the frequency of the output signal can be increased again by operations increased by clock CK, the electric potential at the node n1 to "VDD+Vth or more before the STOP signal is switched to high level. Based on this, you can ensure longer than in the traditional scheme, (i) the period of time in which VDD can be displayed, and (ii) the period of time of low impedance.

Here the amplitude of the clock CK and the capacitor CI are set so that the increased electric potential (VDD-Vth+α) at the node n1 is "VDD+Vth or more.

The layout of the circuit 10 illustrated in figure 1, the contact output of the drain of the transistor T2 is connected to the source of the VDD supply. It should be noted that the present invention is not limited to this arrangement. For example, the synchronization signal φ can be entered in the contact output flow. 5 is a timing chart showing the forms of various signals of the circuit 10, having a layout in which the synchronization signal φ is introduced into the contact pin drain of the transistor T2. In this arrangement it is also possible to output the signal input to the transistor T2, with the injury level of the electric potential of the signal way similar to the layout of the circuit 10 illustrated in figure 1. Therefore, when the transistor T2 is switched on, the level of electric potential equivalent to that of the clock φ output.

(The second variant implementation)

The following description explains the layout of the circuit 20 of this variant implementation. 6 is a schematic diagram illustrating a layout of 20, and 7 is a timing chart showing the forms of various signals of the circuit 20. It should be noted that with respect to the elements having functions identical with the functions of the elements described in the embodiment 1, are identical reference numbers, and explanations of these elements are omitted herein for simplicity of explanation. Additionally, the terms defined in embodiment 1, also used in the present embodiment, as specified in embodiment 1, if not specified otherwise.

Here in the layout (see Figure 1) circuit 10 described in embodiment 1, during the time when the STOP signal is switched to high level and the electric potential at the node n1 becomes a low level, the output contact output OUT becomes high-impedance state (see the area indicated by oblique lines in figure 2). This causes the effect of noise on the output signal.

To avoid this the high-impedance state, the circuit 20 of this variant implementation has such a layout that the circuit 10 includes a transistor T4 (fourth transistor). As illustrated in Fig.6, the transistor T4 is such that (i) contact output drain (first terminals) is connected to the terminal of the source of the transistor T2 and the output contact output OUT, (ii) contact output source (second terminals) is connected to the source of the VSS power supply, and (iii) contact output gate (control terminals) is connected to the terminal of the transistor T3. The contact terminals of the gates of the transistors T3 and T4 are connected to the input contact output IN2. The input signal IN2 to control the enabled/disabled state of each of the transistors T3 and T4 is introduced into each of the contact pins of the shutter. The connection point between the transistor T2, the transistor T4 and the output contact output OUT is the node n2.

This layout, as shown in Fig.7, at the time when the electric potential at the node n1 becomes a low level, the input signal IN2 having a high level is entered so that the transistors T3 and T4 are included. Therefore, the electric charge at the node n1 can be successfully discharged, and simultaneously, the level of electric potential of the output signal can be stabilized at a low level (VS).

It should be noted that the input to the in terminals of the transistor T4, is not limited specifically and may be another control signal as long as the signal can stabilize the level of electric potential of the output signal OUT at a low level (VSS).

(A third option exercise)

The following description explains the layout of the circuit 30 of this variant implementation. Fig is a schematic diagram illustrating the layout of the circuit 30. It should be noted that with respect to the elements having functions identical with the functions of the elements described in the embodiments, the implementation of 1 and 2 are identical reference numbers, and their explanations are omitted herein for simplicity of explanation. Additionally, the terms defined in the implementation options 1 and 2 are also used in the present embodiment, as defined in the implementation options 1 and 2, unless otherwise noted.

The circuit 30 of this variant implementation has such a layout that the circuit 20 illustrated in Fig.6, additionally includes a transistor T5 (fifth transistor), which plays the role of the update function. As illustrated in Fig, the transistor T5 is such that (i) contact output drain (first terminals) is connected to the source of the VDD supply, (ii) the contact is the output of the source (second terminals) connected to the node n1, and (iii) contact output gate (control terminals) connected to the node n2.

With this arrangement, the output signal OUT is introduced into the contact pin of the transistor T5. Therefore, even if the electric potential at the node n1 decreases due to leakage current in the off state and the like, provided that the input signal IN1 is at a low level and the transistor T1 is in the off state, the electric potential at the node n1 can be charged again up to "VDD-Vth" during the time period in which the output signal OUT is at a high level (refresh operation). Consequently, during the time period in which the synchronization signal CK is at a high level, the electric potential at the node n1 can be increased up to "VDD-Vth+α". Therefore, the output signal OUT can stably output VDD and can drive normally and without false alarms during operation in the low-frequency mode.

(A fourth option exercise)

The following description explains the layout of the circuit 40 of the present variant implementation. Fig.9 is a schematic diagram illustrating the layout of 40, and Figure 10 is a time chart showing the forms of various signals of the circuit 40. It should be noted that with respect to the elements having functions identical with the functions of the elements described in the embodiments, the implementation of 1-3, use identical reference numbers, and their explanations are omitted is this document for ease of explanation. Additionally, the terms defined in the implementation options 1-3, are also used in the present embodiment, as defined in the implementation options 1 through 3, unless otherwise noted.

The circuit 40 of the present variant implementation has such a layout that the circuit 20 illustrated in Fig.6, additionally includes a transistor T6 (sixth transistor) between the input contact output IN1 and the transistor T1. As illustrated in Fig.9, the transistor T6 is such that (i) contact output drain (first terminals) is connected to the input contact output IN1, (ii) contact output source (second terminals) is connected to the terminal of the transistor T1 and (iii) contact output gate (control terminals) receives the signal EN permission. Additionally, the contact output of the source of the transistor T6 is also connected to the connection point (a node n2 between the transistors T2 and T4.

With this arrangement, after the signal EN, the resolution switches to a high level, regardless of switches or no signal EN permissions to the low level later, you can save the input signal having a high level, the contact output of the transistor T1 during the time period in which the output signal OUT has a high level. This allows you to save when it's 40 in the active state.

Additionally, the output terminals OUT and contact output of the transistor T1 are connected to each other. Therefore, if the electric potential at the node n1 is reduced to "VDD-Vth" or less period of time in which the output signal OUT has a high level, the transistor T1 turns on. It should be noted that when the electric potential at the node n1 is increased to "VDD-Vth or more, the transistor T1 is turned off and the node n1 becomes high-impedance state.

Consequently, even if the electric potential at the node n1 decreases due to leakage current in the off state and the like, the electric potential at the node n1 can be charged again up to "VDD-Vth" through transistor T1 during the time period in which the output signal OUT has a high level (refresh operation). Accordingly, during the time period in which the synchronization signal CK is high, the electric potential at the node n1 can be increased up to "VDD-Vth+α". Therefore, the output signal OUT can stably output VDD and can drive normally and without false alarms during operation in the low-frequency mode.

Here, the transistor T6 is not limited to the above arrangement, illustrated in Fig.9. For example, the transistor T6 may be located so that its pin output source switch is in high-impedance state, when the input signal IN1 has the electric potential to the low level. 11 and 12 specifically illustrate examples of such a configuration. In the arrangement illustrated in figure 11, the contact output of the drain of the transistor T6 is connected to the source of the VDD power supply and the input signal IN1 is introduced into the contact pin of the transistor T6. Additionally, in the arrangement illustrated in Fig, the input signal IN1 is introduced into the terminals of the drain terminals of the transistor T6. These layouts are suitable for the composition without the use of another signal (e.g. signal EN permission), in which, after the input signal IN1 becomes active (high level), the active state is maintained regardless switches whether or not the input signal IN1 to the low level at a later date.

(The fifth option exercise)

The following description explains the layout of the circuit 50 of this variant implementation. Fig is a schematic diagram illustrating the layout of the circuit 50. It should be noted that with respect to the elements having functions identical with the functions of the elements described in the embodiments, the implementation of 1-4, use identical reference numbers, and their explanations are omitted herein for simplicity of explanation. Additionally, the terms defined in the implementation options 1-4, also uses the light is used in the present embodiment, thus, as defined in the implementation options 1-4, unless otherwise noted.

Here, the layouts of the circuits described in embodiments implementing 1-4, if the input signal IN has the low level in the initial state, the amount of electric charge charged in the capacitor C1 is not detected, and the electric potential at the node n1 is unstable. Therefore, these layouts are unstable in the initial state.

In order to realize a stable initial state, the circuit 50 of this variant implementation has a layout that any composition in accordance with the variants of the implementation 1-4 optionally includes a transistor T7 (seventh transistor). Circuit 50 illustrated in Fig has such a layout that the circuit 10 illustrated in figure 1, includes a transistor T7. The transistor T7 is such that (i) contact output gate (control terminals) receives the signal INI initialization, (ii) contact output source (second terminals) is connected to the source of the VSS power supply, and (iii) contact output drain (first terminals) connected to the node n1.

With this arrangement, the signal INI initialization, having a high level is entered in the initial state, so that the electric potential of the node n1 can be stabilized at VSS. Followed the Sabbath.) it is possible to stabilize the initial state.

It should be noted that it is possible to stabilize the initial state of any of the schemes in accordance with the variants of the implementation of 2-4 by providing in the circuit of the transistor T7 in the same manner as described above.

(Sixth variant implementation)

The following description explains the layout of the circuit 60 of this variant implementation. Fig is a schematic diagram illustrating the layout of 60. It should be noted that with respect to the elements having functions identical with the functions of the elements described in the embodiments, the implementation of 1-5, used identical reference numbers, and their explanations are omitted herein for simplicity of explanation. Additionally, the terms defined in the implementation options 1-5, also used in the present embodiment, as defined in the implementation options 1-5, unless otherwise noted.

Here any of the layouts of the circuits in accordance with the variants of the implementation of 1-5 has such a problem that requires a large capacity contact output CK of the clock. The following description specifically explains the load synchronization using circuit 10, illustrated in figure 1, as an example.

If the electric potential at the node n1 has a high level (VDD-Vth or more), i.e. the period of time the Yeni, in which the node n1 is in a high impedance state, the capacitance contact output CK of the clock can be expressed by the following equality:

1/capacity contact output CK clock=1/C1+1/Ctr (where Ctr is the sum of the parasitic capacitances of the transistors T1, T2 and T3) (1).

It should be noted that the wire load, etc. is omitted in equality for ease of explanation.

Here to significantly increase the electric potential at the node n1 requires "C1>Ctr". For example, to increase the voltage of the node n1 is at "2×Vp/3" relative to the amplitude Vp of the clock CK is required "C1:Ctr=2:1". By substituting this equality in the equality (1) the following equation can be obtained:

capacity contact output CK clock=1/3×C1.

Then, if the electric potential at the node n1 has a low level (VSS), i.e. the time period in which the node n1 is not in the high impedance state, the capacitance contact output CK of the clock can be expressed by the following equality:

capacity contact output CK clock=C1.

Thus, it is found that the capacity of the contact output CK of the clock is large at the time when the node n1 is not in the high impedance state. In particular, if many circuits, connected in series, take the same singlesign the l CK through its contact pin CK of the clock, capacity contact output CK of the clock becomes very large.

To reduce this burden synchronization circuit 60 of this variant implementation has a layout that any scheme in accordance with the variants of the implementation of 1-5 optionally includes a transistor T8 (eighth transistor). Scheme 60, illustrated in Fig has such a layout that the circuit 10 illustrated in figure 1, includes a transistor T8. The transistor T8 is such that (i) contact output gate (control terminals) is connected to the input pin IN conclusion, (ii) contact output drain (first terminals) is connected to the terminal CK of the clock, and (iii) contact output source (second terminals) connected to the node n1 through the capacitor C1.

In the circuit 60 due to transistor T8 you can disable terminals CK of the clock and the capacitor C1 from each other during the period of time in which the node n1 does not go into high-impedance state, and the load contact output CK of the clock becomes very large.

In particular, if the electric potential at the node n1 is stabilized at VSS, the node n1 does not require to increase by clock CK. Hence, by means of electric Department contact output CK of the clock and is condensator C1 from each other by use of the transistor T8 in the period of time in which the electric potential of the node n1 is stabilized at VSS, the load contact output CK of the clock becomes only the parasitic capacitance of the transistor T8, which is very small.

Accordingly, reducing the required driving ability of the circuit to the excitation contact of the output CK of the clock and the reduction of capacity contact output CK of the clock, it is possible to reduce the power consumption.

Here, in order to stabilize the electric potential at the node n3 is provided between the transistor T8 and the capacitor C1 during the time period in which the transistor T8 is in the off state, the circuit 60 may further include a transistor T9 and the inverter 6 includes a resistance R1 and the transistor T11, as illustrated in Fig. In this arrangement, the transistor T9 is such that (i) contact output drain connected to the node n3, (ii) contact output source connected to the source of the VSS power supply, and (iii) contact output gate connected to the input pin IN terminal, which is connected to the inverter 6. With this arrangement, when the transistors T1 and T8 are turned off, the transistors T3 and T9 are included, so that the electric potential at the node n1 and the node n3 can be stabilized at VSS.

Additionally, the contact output gate transistor is T8, illustrated Fig, is connected to the input contact to the output IN. The input contact output gate of the transistor T8, is not limited specifically. You can enter in the time period in which the electric potential at the node n1 is stabilized at VSS, or during part of this period of time, another control signal to control the transistor T8, which must be switched off.

Additionally, Fig, the inverse signal input contact output IN generated by the inverter 6 and displayed in the input terminals INB. However, if you have another control signal as an inverted signal of the signal input to the input terminals IN, the control signal may be injected into the input terminals INB as the inverse of the signal.

In addition, the circuit 60 provides the reducing power consumed by a capacitor. Nevertheless, it is possible to have, through the operation external synchronization, (i) the arrangement in which the synchronization signal CK stable at a certain DC level during the time period in which the electric potential at the node n1 is stabilized at VSS, or (ii) a layout, in which the sampling clock CK is slowed down in order to reduce power consumption during the time period in which the electric potential at the node n1 with abilitarian on VSS.

It should be noted that the above arrangement of the present variant implementation to reduce the load synchronization through the use of transistor T8 may be properly applicable to any of the schemes in accordance with the variants of the implementation of 1-5 in a manner analogous to the present variant implementation.

(Seventh variant implementation)

The following description explains the layout of the circuit 70 of this variant implementation. Fig is a schematic diagram illustrating the layout of the circuit 70. It should be noted that with respect to the elements having functions identical with the functions of the elements described in the embodiments, the implementation of 1-6, use identical reference numbers, and their explanations are omitted herein for simplicity of explanation. Additionally, the terms defined in the implementation options 1-6 are also used in the present embodiment, as defined in the implementation options 1-6, unless otherwise noted.

Here for any of the circuitry in accordance with the variants of the implementation of 1-6 operation increase by clock CK causes the node n1 to have a high electrical potential "VDD-Vth+α". Hence, there is a risk that the high voltage is applied to the transistor connected to the node n1, in particular, (i) between the gate and history the Ohm, (ii) between the gate and the drain, and (iii) between source and drain, so that the transistor may be damaged due to high voltage exceeding the withstand voltage of the transistor.

Namely, in the circuit 10, a high voltage is applied, in particular, (i) between the gate and drain of the transistor T3 and (ii) between the source and drain of the transistor T3. If the input signal IN is at VSS and the electric potential at the node n1 rises, the electric potential at the node n1 is increased to "VDD-Vth+α". Therefore, as the voltage between the gate and drain of the transistor T3, and the voltage between the source and drain of the transistor T3 becomes "VDD-Vth+α-VSS". Here can get the following equation:

"VDD-Vth+α-VSS=35V-Vth (where VDD=10V, VSS=-10V=15V)".

On the other hand, to other nodes is applied an electric potential difference of 20V between VDD and VSS. Thus, the high voltage is applied to the transistor connected to the node n1.

Therefore, in order to protect the transistor from such a high voltage, the circuit 70 of this variant implementation has a layout that any of the schemes in accordance with the variants of the implementation of 1-6 optionally includes a transistor T10 (tenth transistor). Scheme 70, illustrated in Fig has such a layout that the circuit 10 illustrated in figure 1, includes transisto the T10. The transistor T10 is such that (i) contact output gate (control terminals) is connected to the source of the VDD supply, (ii) contact output drain (first terminals) connected to the node n1, and (iii) contact output source (second terminals) is connected to the terminal of the drain of the transistor T3. The connection point between the transistors T3 and T10 is the node n4.

With this arrangement, when the input signal IN is at VSS, the electric potential at the node n1 is increased to "VDD-Vth+α", and the electric potential at the node n4 increases only up to "VDD-Vth". Therefore, as the voltage between the gate and drain of the transistor T3, and the voltage between the source and drain of the transistor T3 becomes "VDD-Vth-VSS=20V-Vth", which is lower than the electric potential of α than the voltage in the circuit 10.

Additionally, the transistor T10 has such low voltage that the electric potential between the gate and the drain is "α-Vth=15V-Vth", the electric potential between the gate and the source is Vth, and the electric potential between source and drain is "α=15V".

Therefore, even if the electric potential at the node n1, which is in the high impedance state, is increased due to clock CK, you can reduce the load on the voltage applied to the transistor connected to the node n1. Followed the Sabbath.) you can create a highly reliable circuit.

The above arrangement of the present variant implementation, to protect the transistor from high voltage, is applicable to any scheme in accordance with the variants of the implementation of 1-6 in a manner analogous to the present variant implementation. Fig illustrates an example in which the layout of this variant implementation is applied to the circuit in accordance with embodiment 6, and this scheme is illustrated in Fig.

Here any of the schemes in accordance with the variants of the implementation 1-7 has a layout in which the contact pin drain of the transistor T1 is connected to the source of the VDD supply. However, the schematic layout of the present invention is not limited to this arrangement. For example, you can connect the terminals of the drain terminals of the transistor T1 to each other, i.e. to have a diode is switched on. Fig-24 are concepts that illustrate schematic layout 11, 21, 31, 41, 51, 61 and 71 respectively. Schematic layout 11-71 correspond to the layout diagrams 10, 20, 30, 40, 50, 60 and 70, respectively, in each of these configurations of the transistor T1 is diode is switched on. For example, in the case when the transistor T1 is set as in the circuit 10, if the noise is generated with respect to the input signal at the time when the transistor T3 is included in the m condition, and the input signal input in the input terminals IN, has a low level, the transistor T1 turns on instantly. From this it follows that a through current flows from the source VDD to the power source VSS supply through transistors T1 and T3, thereby causing an increase in consumed current or a false alarm. Considering this problem, in the layout using diode enable contact output gate and a contact output drain of the transistor T1 are connected to each other so that even if the formation of noise with respect to the input contact output IN causes the transistor T1, the electric potential difference between the source and the drain is only the electric potential of the noise. Therefore, compared with the case where the contact pin drain connected to the source of the VDD power supply, the electric potential difference between the source and drain less, so that the through current is less. Additionally, since the transistor T3 is in the on state, even if the transistor T1 is switched on due to noise, electric potential, fluctuating due to noise generated with respect to the input contact IN conclusion, it is discharged in the direction of source VSS power supply through the transistor T3. Thus, the transistor T1 is such an influence to turn it off. Therefore, you can predator is to defend the false triggering of transistor T1 due to the influence of noise.

Fig is a timing chart showing the forms of various signals of the circuit 11 illustrated in Fig, from the schemes described above, in each of which the transistor T1 is diode is switched on. As shown in Fig in a manner analogous to the layout of the circuit 10 illustrated in figure 1, you can output the signal while maintaining the level of electric potential of the signal input contact output drain of the transistor T2. Therefore, when the transistor T2 is switched on, VDD is output.

Additionally, the arrangement explained in the embodiment 1 described above, and in the layout of the dot clock φ is introduced into the contact pin drain of the transistor T2, is also applicable to any of the schemes in accordance with the variants of the implementation described above. In this case, when the transistor T2 is switched on, the output level of the electric potential of the clock φ.

Meanwhile, dot clock CK entered in the scheme of saving the active signal present invention shows such a waveform that the high level and low level are repeated alternately and periodically, as shown in Fig. As described above, the output signal OUT schemes maintain active signal has a low impedance, in particular, at the time when the synchronization signal CK is high level (period T). Therefore, during the period of time is, in which the fill factor of the clock CK is, for example, 50%, as shown in Fig, the output signal OUT has a low impedance. Thus, by adjusting the fill factor of the clock CK becomes possible to adjust the period of time during which the output signal OUT has a low impedance.

Here, the following description explains the preferred value of the duty cycle of the clock CK by reference to the arrangement illustrated in figure 1. As described above, when the synchronization signal CK switches to the low level, the electric potential at the node n1 is reduced to "VDD-Vth-β due to leakage current in the off state, etc. are ideal fill factor is "the period of high level:low level=T1-tβ:tβ (where tβ is the period of time required to recharge the electric potential at the node n1 to "VDD-Vth", and T1 is one cycle)". Additionally, the time period required for clock CK to switch from high level to low level, determined in accordance with the time constant of the load (capacitance and resistance) contact output CK of the clock. The period of time required for the clock CK to switch from high level to low level (or Vice versa), referred to as "tc". If tck is not provided as pulse width, it is impossible to obtain the desired boost voltage α to increase in the node n1. Therefore, taking into account the time constant, the ideal fill factor is "the period of high level:low level=T1 tck:tck".

In practice, the recharge to compensate for the decrease due to leakage current in the off state, etc. and shift clock CK from the high level to the low level is performed at the same time. Therefore, taking into account both of these factors, the ideal fill factor is "the period of high level:low level=T1-tβ':tβ' (where tβ' is the period of time needed to recharge the electric potential at the node n1 to "VDD-Vth")". When the fill factor becomes possible to lower the output impedance of the transistor T2 while maintaining the active state of the circuit under normal conditions.

According to the explanation described above, it is preferable to set the fill factor of the clock so that the time period of the low level in one cycle of the clock CK is equivalent to the period of time from the time when the synchronization signal CK switches from high level to low level, until the time when the electric potential at the node n1 is saturated.

Additionally, it is preferable to set coefficientsfor so, that period of time in which the transistor T2 exhibits a low impedance, is longer.

It should be noted that if the period of time for switching of the clock CK is greater than 50%, the synchronization signal CK switches to the next higher level before fully switching to the low level. Therefore, to get the voltage α bootstrap, you must call (regulating) of the capacitor C1, so that he was more. This leads to the scheme of a larger size or to increase the load capacitor, thereby requiring a longer period of time to switch. To avoid this, in General, the period of time for switching is set to be within 50%, by slowing down the frequency of the clock or by specifying that the load induced by clock CK was less. Therefore, preferably, the fill factor was 50% or more, to cause the period of time in which the transistor T2 exhibits a low impedance, to be as far as possible more long.

Fig shows the synchronization signal CK_H, which is an example of a waveform set so that the period T of the high level is longer (the fill factor is set to be larger). This allows for a longer period of time in which the output signal OUT schemes maintain active signal has a low impedance. Due to the longer period of time low impedance output signal can be more stable against noise and the load can be raised more quickly. Thus, it is preferable that the synchronization signal CK had a frequency higher than the frequency of the output signal OUT and at the same time was at a high level (electric potential on the active side) over a period of time longer than the low level.

It should be noted that if the transistor with channel p-type is used, the logic is completely reversed. Therefore, in this case, it is preferable that the synchronization signal CK had a low level during a time period longer than had a high level, for reasons similar to those described above.

Each of the schemes (schemes maintain active signal) in accordance with the variants of the implementation 1-7 described above, may properly be used, in particular, in the liquid crystal display device (display device). Fig is a block diagram illustrating the full layout of liquid crystal display devices.

The liquid crystal display device 151 includes a panel 152, on which the liquid crystal display device 151 additionally includes: a pixel region 153; shaper 154 East is ka; shaper 155 shutter/CS; schema 156 BUFF/module level shift; circuit 157 of the power supply; and a contact pin 158.... Shaper 154 source includes an output circuit 154a and outputs the data signal to each of the bus lines of the source pixel region 153. Shaper 155 shutter/CS includes an output circuit 155a and outputs (i) a select signal in the bus line of the shutter in order to record, in each pixel of the pixel region 153, the data signal output from the imaging unit 154 source, and (ii) a CS signal in the bus line CS in order to raise the recording of electrical potential with respect to each pixel of the pixel region 153. Each of the output circuits 154a and 155a consists of a buffer, which is a gain circuit for generating a data signal with a 100 percent gain in accordance with an input signal, the gain circuit has a low output impedance. The circuit 156 BUFF/module level shifting includes a buffer, which is a gain circuit having a low output impedance, such as the scheme of a 100% gain to compensate for signal attenuation inverter and the like, and the module circuit of the level shift conversion level of the power source signal. The circuit 156 BUFF/module level shift provides shaper 154 source and the imaging unit 155 shutter signal subjected to the process of this buffer. Scheme 157 switching-mode power is Tania forms the power supply for logic circuit, the reference voltage of the data signal, a counter voltage of the data signal, the voltage of the auxiliary capacitance and the like, Each of the contact pins 158... is a contact output to signal input and power supply in each of the above schemes, provided on the panel 152. It should be noted that the liquid crystal display device may include a demultiplexer instead of the driver source.

Each of the circuits in accordance with the variants of the implementation 1-7 is applicable to any part of the liquid crystal display device 151. In particular, each of the schemes is properly applicable to the switch provided in CS-shaper, buffer circuit, the circuit module level shift and impedance shift provided by each driver source (exciting diagram line data signals) and the shaper shutter (exciting diagram of the line scanning signals). The following description explains examples of such applications: example 1 in which the scheme is applied to a storage scheme provided in CS-shaper; examples 2-4, in each of which the scheme is applied to the buffer circuit and the circuit module of level shift; and example 5 in which the scheme is applied to the module resistance to shear.

Example 1

Fig is a block diagram that illustrates to what Panovko storage scheme 1, provided in CS-shaper of the present example, and Fig is a schematic diagram of a memory circuit 1. Fig is a timing chart showing the forms of various signals of the memory circuit 1. The memory circuit 1 includes two schemes (schemes maintain active signal)corresponding to any of the circuits described in the embodiments, the implementation described above. In particular, for example, the memory circuit 1 has such a layout that the contact pin STOP one of the circuits 10 (which is referred to as "the scheme 10b"), illustrated in figure 1, and the output terminals OUT of the other one of the circuits 10 (which is referred to as "the scheme 10a") are connected to each other. It should be noted that the storage scheme should only have, at least, the layout of the circuit 10 illustrated in figure 1. The memory circuit 1 of the present example has such a layout that the circuit 10 includes a transistor T4 (Fig transistors Ta4 and Tb4), which is a layout of the circuit 20, illustrated in Fig.6.

Then the following describes the operation of the memory circuit 1. Here, the following explanation is directed to an example in which the input signal IN has the high level, is introduced into the circuit 10a and the input signal INB (inverted signal of the input signal IN has the low level, is introduced into the circuit 10b at the time when the signal EN razresheniem high level.

When a signal having a high level, is introduced into the circuit 10a, the circuit 10a enters the active state. Electric charge stored in the node na1 at the time when the synchronization signal is entered. Therefore, as described in each of the above embodiments, the output signal OUT VDD is output from the circuit 10a. This output signal OUT is introduced into the contact pin STOP (see Fig) another circuit 10b.

When receiving a signal VDD circuit 10b becomes inactive and displays VSS through the transistor Tb4. The polarity of the input signals IN and INB are opposite to each other so that one of the circuits outputs VDD at a time when the other of the circuits outputs VSS. Therefore, during the period of time in which you enter the dot clock CK, the electric potential of the circuits 10a and 10b are stored up until the next signal EN permission will not be switched to the high level.

It should be noted that the memory circuit 1 illustrated in Fig has a layout in which the inverse signal INB input signal IN is introduced externally, but the present invention is not limited to this arrangement. For example, as another layout, you can create a diagram of the inverter in the memory circuit 1 to generate the inverse signal INB based on the input signal IN, as illustrated in Fig and 32. Fig illustrates the inverter consisting of resistance is ellenia R1 and transistor T11, and Fig illustrates an inverter consisting of a scheme of compensatory feedback. Under these arrangements, the signal having the low level (VSS)is output as the inverse signal INB at the time when the input signal IN has the high level (VDD), while the signal having the high level (VDD), is output as the inverse signal INB at the time when the input signal IN has the low level (VSS).

Additionally, in order to stabilize the initial state of the memory circuit 1 illustrated in Fig additionally may include transistors T7 (see Fig)described in embodiment 5, for example, in the respective circuits 10a and 10b. Transistor Ta7 circuit 10a and the transistor Tb7 circuit 10b are arranged so that (i) the signal INI initialization is entered in their contact output gate, (ii) their contact pin drain connected to the node na1 and the node nb1, respectively, and (iii) their contact terminals of the source connected to the source VSS of the power source VDD of the power supply respectively. With this arrangement, it becomes possible to stabilize the initial state by entering, in the initial state, the signal INI initialization, having a high level.

It should be noted that the memory circuit 1 has the function of the update that is described in the above embodiments, the implementation, in order to be able to store the value in the norms of the selected conditions, even if exposed to low-frequency stimulation.

In the present example, the memory circuit 1 includes a circuit 20 in accordance with embodiment 2, but the present invention is not limited to this. The memory circuit 1 may include any of the schemes (for example, the circuit 30, the circuit 40 or scheme 50) in accordance with other variants of implementation. Layout using this scheme can realize effects similar to the effects of this example.

Example 2

Fig is a block diagram illustrating the arrangement of the buffer circuit 2 of the present example, and Fig is a schematic diagram of the buffer circuit 2. The buffer circuit 2 includes any one of the schemes (schemes maintain active signal) in accordance with the variants of the implementation described above. In particular, the buffer circuit 2 should only have, at least, the layout of the circuit 10 illustrated in figure 1. The buffer circuit 2 of the present example has such a layout that the circuit 10 includes a transistor T4, which is the layout of the circuit 20, illustrated in Fig.6.

Here the inverter for signal INB, which must be entered in figure 10, consists of a resistor R1 and transistor T11. Therefore, if the input signal IN the inverter has a high level, the constant current (end-to-end that is) flows from source VDD to the power source VSS power thereby increasing the power consumption. In order to reduce power consumption, the resistance R may have a higher resistance value. However, in this case there are other new issues, such as the reduction of the driving ability and increase of noise exposure.

Given the problems the buffer circuit 2 of the present example has such a layout that the output terminals INB inverter is connected only to the terminal of the transistor T1 of the circuit 10. With this arrangement, the load becomes very small. Therefore, even if the drive capability of the inverter is reduced (even if the resistance R1 has a higher resistance), the load of the contact output of the transistor T1 can immediately aroused. Consequently, it is possible (i) to perform high-speed operation and at the same time (ii) to increase the stimulating ability of the buffer circuit 2 through the operation of the circuit 10. Accordingly, in this arrangement, it is possible to create a buffer circuit, having an exciting high capacity with low power consumption.

It should be noted that in the present example, the buffer circuit 2 includes a circuit 20 in accordance with embodiment 2, but the present invention is not limited to this. The buffer circuit 2 may include any one of the schemes (EmOC is emer, the circuit 30, the circuit 40 or scheme 50) in accordance with the other options in the implementation described above. Layout using this scheme can realize effects similar to the effects of this example.

Additionally, if the input signal IN has a voltage other than VDD/VSS (for example, high voltage below VDD/low voltage VSS), the buffer circuit 2 of the present example functions as a circuit module of level shift.

In addition, each of the buffer schema and schema module level shift, described above, may be arranged in such a way that the inverter consists of a scheme of compensatory feedback, as illustrated in Fig and 36. In such an arrangement, when the input signal IN has the high level, the current of a constant value (a through current) flows from the source VDD to the power source VSS supply through transistors T12 and T13, thereby increasing the power consumption. In order to reduce power consumption, transistors T12 and T13 can be reduced in size. In this case, however, other problems arise, such as the reduction of the driving ability and increase of noise exposure, in the same way as in the inverter with the use of resistance.

Given the problems in the buffer circuit and the circuit module of level shift, illustrated in Fig and 36, the output con the akt INB output of the inverter is connected only to the terminal of the transistor T1 of the circuit 10, so it is possible to realize effects similar to the buffer, consisting of an inverter using resistance described above.

Example 3

Next, the following description explains an example of another arrangement of the buffer circuit. Fig is a schematic diagram illustrating the arrangement of the buffer circuit 3 of the present example. The buffer circuit 3 includes an inverter illustrated in Fig, and the circuit 20 illustrated in Fig.6, the layout of which is modified. In particular, the buffer circuit 3 has such a layout that the circuit 20 illustrated in Fig.6, (i) the transistor T3 is omitted, (ii) contact output gate of the transistor T1 is connected to the source of the VDD supply, and (iii) contact output drain of the transistor T1 is connected to the output terminal of the output inverter INB. Additionally, the contact output of the transistor T3 is connected to the input contact output IN inverter.

Here, the following description explains the operation of the buffer circuit 3 of the present example.

First, if the input signal IN the inverter has a low level, the inverted signal INB is VDD. When the inverse signal INB VDD is introduced into the transistor T1, the electric potential at the node n1 is charged up to "VDD-Vth", and then increases up to "VDD-Vth+α" through promotion by clock CK. Node n1 is connected to the contact of the th output of the transistor T2, so that the electric potential of the output signal OUTB is VDD, i.e. the electric potential is not reduced to the threshold value.

Then, if the input signal IN the inverter switches to a high level, the inverted signal INB becomes VSS and the electric potential at the node n1 is discharged to VSS. Here the input signal IN has the high level, so that the transistor T3 is turned on and the electric potential of the output signal OUTB becomes VSS.

With this arrangement, the transistor T2 exhibits a low impedance at the time when the electric potential at the node n1 is high due to promotion by clock CK. Consequently, it is possible (i) output signal, which is stable against noise, and (ii) to initiate the load quickly.

Additionally, even if the node n1 loses its electric charge due to leakage, transistor T1 turns on and the electric potential at the node n1 recharged when the electric potential at the node n1 drops below the "VDD-Vth". Accordingly, it is possible to provide valid stock relative to false positives during operation in the low-frequency mode.

Additionally, even if the resistance R1 has a high resistance, since this contact output energizes load only the parasitic capacitances of the transistors T1 and T2 and the capacity to which danzatore C1, it is possible (i) to perform high-speed agitation and simultaneously (ii) to have lower consumption of electricity.

Additionally, compared with the arrangement of the buffer circuit 2 in accordance with example 2, the buffer circuit 3 can be reduced in size, because the layout of the buffer circuit 3 does not require a transistor T3 to discharge the node n1.

It should be noted that the buffer circuit 3 of the present example also functions as a circuit module shift level if the input signal IN has a voltage other than VDD/VSS (for example, high voltage below VDD/low voltage equivalent to VSS).

Additionally, each of the buffer schema and schema module level shift, described above, may be arranged in such a way that the inverter consists of a scheme of compensatory feedback in the same manner as in example 2. Fig is a schematic diagram illustrating a buffer circuit including an inverter consisting of a scheme of compensatory feedback.

It should be noted that the buffer scheme 2 of example 2 can work normally even if the input signal IN is a DC signal.

Additionally, in the buffer circuit 3 of example 3, if the input signal IN is a DC-signal contact output gate of the transistor T12 has a voltage of "VDD-Vth" due to leakage current in off state. Therefore, the output to the stroke output of the inverter has a voltage of "VDD-2×Vth", so the electric potential at the node n1 becomes "VDD-2×Vth". The electric potential at the node n1 is increased to "VDD-2×Vth+α" through promotion by clock CK. By setting the capacitor C1 so that the "VDD-2×Vth+α" is greater than VDD+Vth", the buffer circuit 3 can work normally even if the input signal IN is a DC signal.

Example 4

Additionally, the following description explains an example of still another layout of the buffer circuit. Fig is a block diagram illustrating the arrangement of the buffer circuit, 4 of this example, and Fig is a schematic diagram of a buffer circuit 4. The buffer circuit 4 includes an inverter illustrated in Fig, and chart 10, is illustrated in figure 1. In particular, as illustrated in Fig, the buffer circuit 4 is arranged such that (i) the output contact output inverter INB is connected to the terminal of the transistor T1 and the output contact output OUTB of the buffer circuit 4, and (ii) terminals of the transistor T3 is connected to the input contact output IN inverter.

In accordance with the buffer circuit 4 of the present example, if the input signal IN the inverter has a low level, the inverted signal INB is derived from the high resistance R1. Therefore, the inverse signal INB is high-impedance signal having the voltage is of VDD. However, due to the output signal (output signal of the transistor T2) circuit 10, the output signal OUTB can be a low-impedance signal having a voltage VDD.

It should be noted that in the buffer circuit 4 output contact output INB and the output terminals OUTB are connected to each other, so that even if the synchronization signal CK is stopped, you can output the signal having the electric potential VDD, i.e. the electric potential is not reduced to the threshold value.

Additionally, the buffer circuit 3 may include any of the schemes in accordance with the other options in the implementation instead of the circuit 10. When linking using this scheme it is also possible to realize effects similar to the effects of this example.

It should be noted that the buffer circuit 4 of the present example also functions as a circuit module shift level if the input signal IN has a voltage other than VDD/VSS (for example, high voltage below VDD/low voltage equivalent to VSS).

Additionally, the buffer circuit 4 of the present example can work normally even if the input signal IN is a DC signal, in a manner analogous to buffer circuit 2 of example 2 and the buffer circuit 3 of example 3.

Here, the buffer circuits of examples 1-4, the input signal IN and the inverted signal INB can be replaced each other.

Example 5

F. g - this block diagram illustrating the layout of a modular circuit 5 constituting an impedance shift in accordance with the present example. Module create resistance to shear so that the modular circuit 5 illustrated in Fig, are connected in cascade. Modular circuit 5 includes a schema (schema maintain active signal) 10 in accordance with embodiment 1. It should be noted that in addition to scheme 10 modular scheme 5 can fit the traditional layout.

Here, the layout of the modular scheme of traditional impedance shift, if both the input signal ON-1 and ON+1" have a low level, the node n5 becomes high-impedance state. Hence, there is the problem of reducing the maximum allowable relative leakage and noise.

With regard to this issue modular scheme 5 module resistance to shear in accordance with this example has an arrangement in which the output signal of the circuit 10 is fed back to the input side of the circuit 10. This allows the node n5 is maintained at a high level (Aviakompania state), so that you can save the state of the deactivation module resistance to shear. Consequently, it is possible to resolve the problem relating to leakage and noise.

It should be noted that the module resistance to shear, in which the modular scheme 5 cascade connected oceny, arranged such that (i) of the signals CK1 and CK2, which is not switched to the high level at the same time, the synchronization signal CK1 is introduced into the contact pin CK of the clock unit circuits in the even-numbered stages, and the synchronization signal CK2 is introduced into the contact pin CK clock modular circuits 5 in odd-numbered stages, and (ii) the input signal ON-1 is the output signal of the unit circuit 5 in the previous stage and the input signal ON+1 is the output signal of the unit circuit 5 in the subsequent stage.

With this arrangement, if the input signal ON-1" is switched to high level, the electric charge charged in the capacitor C2 of the compensation feedback through the transistor T14, and the node n6 continues to be in high level state even after the input signal ON-1" switched to the low level. Additionally, the transistor T16 is switched on so that the node n5 is changed to be at a low level. When the synchronization signal CK switches to high level, the synchronization signal CK is output from the output contact output ON due to the effect of compensatory feedback. Additionally, when the input signal ON+1" is switched to high level, the node n5 is changed to be at a high level through the transistor T15, and the output signal ON is switched to the low level by the inclusion of the transistor T17.

p> Additionally, the input signal IN circuit 10 is switched to the high level so that the transistor T1 is turned on, and electric charge charged in the capacitor C1. After these operations, the electric potential of the output signal OUT increases to VDD through transistor T2 each input clock CK, so that the electric potential at the node n5 is not reduced due to leakage current in the off state, etc. in Addition, the output signal OUT VDD is fed back to the input terminals IN, so that the electric potential at the node n5 is maintained at VDD until next time, when the input signal ON-1" switched to the high level.

As described above, by applying the scheme, saving the active signal) in accordance with the embodiment 1 to a traditional module, the sliding resistance becomes possible to successfully maintain the electric potential at the node n5 is at VDD, and the electric potential decreases to the threshold value or falls due to leakage etc. in the traditional layout of the module resistance to shear.

In this example, the module resistance to shear includes a circuit 10 in accordance with embodiment 1 described above. However, the impedance shift may include any of the schemes in accordance with other variants of implementation, the description of the parameters above, instead of the circuit 10. When linking using this scheme it is also possible to realize effects similar to the effects of this example.

Additionally, the arrangement of the module the shear to which the scheme each of the embodiments is applicable, not limited to a particular manner. For example, as illustrated in Fig and 43, the other layout module, the sliding resistance may be such that the modular scheme in each cascade module the shear does not use the output signal of the unit circuit in the subsequent stage, i.e. each modular circuit generates a reset signal within each modular scheme. With this layout you can save the state deactivation in a manner analogous to this example. It should be noted that each modular circuit is arranged such that (i) of the signals CK1 and CK2, which is not switched to the high level at the same time, the synchronization signal CK1 is introduced into the contact pin CK of the clock unit circuits in the even-numbered stages and the synchronization signal CK2 is introduced into the contact pin clock CKB modular circuits in even-numbered stages, (ii) the synchronization signal CK2 is introduced into the contact pin CK of the clock unit circuits in odd-numbered stages, the synchronization signal CK1 is introduced into the contact pin clock CKB modular circuits in odd-numbered stages and (iii) the input signal ON-1 is the output signal modular scheme 5, located in the previous stage.

In the modular scheme 5, is illustrated in Fig, electric charge charged in the capacitor C2 of the compensation feedback via the output signal ON-1" modular circuit 5, which in the previous stage. Then, if the synchronization signal CKB is switched to the high level after the signal CK is output to the output terminals ON the transistor T20 is included so that the electric potential at the node n5 is changed to be at a high level, through the resistance R2.

In the modular scheme 5, is illustrated in Fig, electric charge charged in the capacitor C2 of the compensation feedback via the output signal ON-1" modular circuit 5, which in the previous stage. Then, after the synchronization signal CK is output from the output contact output ON, the electric charge of the capacitor C3 is transferred to the capacitor C4 each input signals CK and CKB, so that the electric potential at the node n5 is changed to be at a high level.

Additionally, each unit circuit 5 illustrated in Fig, and modular scheme 5, is illustrated in Fig, similar to the above example, the circuit 10 maintains the electric potential at the node n5 is at VDD until next time, when the input signal ON-1" perekluchaet the high level.

Finally, the following description is directed to an example in which any of the schemes in accordance with the variants of the implementation described above is composed of transistors with a channel of p-type. To implement, through the use of transistors with a channel of p-type composition according to any one of embodiments 1-7 and examples 1-5, all logic should be completely changed to the opposite. Thus, for example, the source of the VDD supply is replaced by a source VSS power source VSS power supply is replaced by a source VDD power supply, and a high level is replaced by a low. Fig is a schematic diagram of a circuit 10'having such a layout that the circuit 10 consists of a transistor with channel p-type. Additionally, Fig is a timing chart showing the forms of various signals of the circuit 10': (a) on Fig shows a waveform if VSS is put into contact output drain of the transistor T2', and (b) on Fig shows waveforms in the case of the dot clock φ is introduced into the contact pin drain of the transistor T2'. This layout can also have the effect of stabilizing the output signal in a manner analogous to the above scheme, consisting of transistors with n-type channel.

As described above, the semiconductor device of the present invention includes a capacitor between the connection point IU the remote control the first and second transistors and the contact output clock for the reception of the synchronization signal, moreover, the synchronization signal has a frequency higher than the frequency of the output signal output from the output contact output.

Additionally, the display device of the present invention includes a semiconductor device.

Consequently, it is possible to provide: a semiconductor device comprising transistors of the same type conductivity, and a semiconductor device can output a stable signal by preventing reduction of the level of electric potential; and a display device that includes a semiconductor device.

Options for implementation and specific examples of implementation, explained in the above detailed description, serve solely to illustrate the technical details of the present invention, which should not be narrowly interpreted within the limits of such embodiments and concrete examples, but rather may be applied in many variations within the essence of the present invention, provided that such variations do not exceed the scope of the claims set forth below.

Industrial applicability

The present invention provides a circuit that can output a stable signal by preventing reduction of the level of electric potential of the input signal. Therefore the present invention is appropriately applicable, in particular, to the display device.

1. A semiconductor device made in the form of schemes of saving the active signal composed of multiple transistors of one type conductivity, in this semiconductor device includes:
from many transistors, the first transistor including first terminals for receiving a voltage switching, the second terminals and the control terminals for receiving the input signal;
- from a variety of transistors, the second transistor including first terminals for receiving a voltage switching, the second contact pin connected to the output terminal output, and control terminals connected to the second contact to the conclusion of the first transistor; and
a capacitor provided between a connection point between the first transistor and the second transistor, and the contact output clock for the reception of the synchronization signal and the synchronization signal has a frequency higher than the frequency of the output signal output from the output contact output,
moreover, the input signal is such that the time period in which the input signal is at a high level longer than the cycle of the clock.

2. The semiconductor device according to claim 1, additionally containing:
from many TRANS which stores the third transistor, includes first terminals connected to the connection point, the second contact pin for receiving the voltage-off and control terminals for receiving the control signal.

3. The semiconductor device according to claim 2, additionally containing:
from many of the transistors of the fourth transistor, comprising a first contact pin, is connected to the output contact output, the second contact pin for receiving the voltage-off and control terminals for receiving the control signal.

4. The semiconductor device according to any one of claims 1 to 3, further containing:
- from a variety of transistors, the fifth transistor including first terminals for receiving a voltage switching, the second contact pin connected to the connection point, and a control terminals connected to the output terminal output.

5. The semiconductor device according to claim 1, additionally containing:
from many transistors sixth transistor that outputs the input signal, while the sixth transistor includes a first contact pin connected to the input contact to the output; a second contact pin connected to the control pin to the output of the first transistor and the output contact output; and control terminals for receiving the of igala permissions.

6. The semiconductor device according to claim 1, additionally containing:
from many transistors seventh transistor comprising a first contact pin connected to the connection point, the second contact pin for receiving the voltage-off and control terminals for receiving the initialization signal for the stabilization of the initial state of the semiconductor device.

7. The semiconductor device according to claim 1, additionally containing:
from many transistors eighth transistor comprising a first contact pin connected to the terminal of the synchronization signal, the second contact pin connected to the end of the capacitor, and a control terminals for receiving the input signal.

8. The semiconductor device according to claim 1, in which:
- the synchronization signal has such a waveform that the high level and low level are repeated alternately and periodically, and the synchronization signal is set so that the time period of the low level in one cycle is equivalent to the period of time from the time when the synchronization signal is switched from high level to low level, until the time when the electric potential at the connection point of the saturated

9. A semiconductor device made in the form of schemes of saving the active signal, composed of a set of transistor the same type of conductivity, when this semiconductor device includes:
from many transistors, the first transistor including first terminals for receiving a voltage switching, the second terminals and the control terminals for receiving the input signal;
- from a variety of transistors, the second transistor including first terminals for receiving a voltage switching, the second contact pin connected to the output terminal output, and control terminals connected to the second contact to the conclusion of the first transistor;
a capacitor provided between a connection point between the first transistor and the second transistor, and the contact output clock reception clock;
from many transistors tenth transistor comprising a first contact pin connected to the connection point of the second terminals and the control terminals for receiving a voltage on and
from many transistors, the third transistor comprising a first contact pin connected to the second contact to the conclusion of the tenth transistor, the second contact pin for receiving the voltage-off and control terminals for receiving the control signal, when this signal has a frequency higher than the frequency of the output signal, the output and the output contact output,
moreover, the input signal is such that the time period in which the input signal is at a high level longer than the cycle of the clock.

10. The semiconductor device of claim 8, in which:
- the synchronization signal has such a waveform that the high level and low level are repeated alternately and periodically, and the synchronization signal is set so that the time period of the low level in one cycle is equivalent to the period of time from the time when the synchronization signal is switched from high level to low level, until the time when the electric potential at the connection point is saturated.

11. Display device containing the semiconductor device according to claim 1.



 

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14 cl, 24 dwg

FIELD: information technologies.

SUBSTANCE: in one or more examples of realisation new game downloading or deletion from game machine is described, when all existing critical data in NV-RAM memory remain undamaged. In one example of invention realisation method and device are developed for dynamic distribution and release of memory area, which make it possible to provide for both permanent and temporary storage of data in NV-RAM. Method and device are suggested for monitoring of available memory area and dynamic change of memory size in NV-RAM. In one example of realisation method is developed for control of NV-RAM integrity and determination of error in critical data. In one or more examples of realisation methods are described for compaction and transfer of NV-RAM content, which make it possible to combine available memory area or to prevent unauthorised access to NV-RAM memory.

EFFECT: saving of critical data even in case of malfunction in game machine.

15 cl, 12 dwg

FIELD: information technologies.

SUBSTANCE: device comprises two CMDS inverters, two recording transistors of n-type, two transistors for reading of n-type and reading transistor of p-type. Output of the first CMDS inverter is connected to input of the second CMDS inverter, to gate of the first reading transistor of n-type and via the first recording transistor is connected to direct data bus. Output of the second CMDS inverter is connected to input of the first CMDS inverter, to gate of reading transistor of n-type and via the second recording transistor of n-type is connected to complementary data bus. Gates of recording transistors of n-type are connected to address recording bus. The first and second reading transistors of n-type are connected serially between shift bus and reading bus. Reading transistor of p-type is connected parallel to the first reading transistor of n-type, and gate of the second reading transistor of n-type is connected to address reading bus.

EFFECT: improved efficiency of device.

1 dwg

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to micro- and nanotechnology and can be used in designing dynamic memory, two-dimensional control matrices for liquid-crystal displays, high-speed and high-precision scanners, two-dimensional sensors, delay lines etc. The device uses a chain series-connected active functionally integrated cells which can control technologically compatible electric devices. Each cell of the chain is a simple electric circuit consisting of a MOS transistor, resistors and a capacitor. The time used is the delay time for switching off the MOS transistor relative the end of the output signal.

EFFECT: invention speeds up operation of the functional device, simplifies its manufacturing technology, reduces its size and improves its integration.

16 dwg

FIELD: information technologies.

SUBSTANCE: pseudo-dual-port memory contains the first port, the second port and array of memory cells with six transistors. The first call to memory is initiated by means of anterior front of the first synchronising signal (ACLK) received along the first port. The second call to memory is initiated in response to anterior front of the second synchronising signal (BCLK) received along the second port. If anterior front of the second synchronising signal occurs in the first period of time, than the second call to memory is initiated immediately after completion of the first call to memory by pseudo-dual-port method. If anterior front of the second synchronising signal occurs later in the second period of time, than the second call to memory is delayed till the time after the second anterior front of the first synchronising signal. Duration of the first and second calls to memory does not depend on beats of synchronising signals.

EFFECT: possibility to control ordering of two operations with memory having two separate ports, every of which has its own input synchronising pulse.

37 cl, 16 dwg

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