Integral logical and-not element based on layered three dimensional nanostructure

FIELD: electricity.

SUBSTANCE: in the integral logical AND-NOT element based on a layered three dimensional nanostructure (the element containing the first and the second logical transistors, the first and the second injecting transistors and a substrate) the logical structure is designed to be nanosized with a stepped profile.

EFFECT: increased response speed and reduced power consumption.

18 dwg

 

The utility model relates to a semiconductor microelectronics and nanoelectronics and can be used to create logic integrated circuits with elements of nanometer size.

Known complementary bipolar scheme AND NOT containing the first and second logic transistor of the first conductivity type and first and second injects transistors of the second conductivity type and the substrate of the second conductivity type (Patent RF №2094910, IPC H01L 27/04, publ. 27.10.1997).

The disadvantages of the known devices are:

1. Poor performance due to the implementation of the scheme with bipolar planar technology, suggesting the technological implementation of the internal collector and the emitter of transitions to implement transistor effects.

2. Low information density due to the formation of transistor effects in the surface layer of the semiconductor crystal.

3. Increased power consumption due to the use of transitions of the diffusion type, having a greater surface area than the surface transitions, which consumes additional power.

The technical problem to be solved by directed offer a useful model is to create integrated logical element AND-NOT on the basis of the layered three-dimensional nanos is out, with increased speed and information density and reduced power consumption.

The technical problem is solved by the integral of the logical element AND-NOT on the basis of a layered three-dimensional nanostructures containing the first and second logic transistors, the first and second injects transistors and the substrate, according to the proposed utility model logical structure made of nanoscale with stepped profile, the area of the I-type conductivity, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor is formed in the form of a nanolayer of a height not less than 3 nm on the substrate by a height of not less than 15 nm II-type conductivity, which is the emitter of the first transistor injects and emitter of the second transistor injects, region II-type conductivity, which is the collector of the second transistor injects and base of the second logic transistor is formed in the form of a nanolayer of a height not less than 3 nm in the region of the first type conductivity, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor, the area of the I-type conductivity, which is the collector of the second logical implemented the Torah, formed in the form of a nanolayer of a height of not less than 10 nm in region II type conductivity, which is a manifold injects the second transistor and the base of the first logic transistor region II type conductivity, which is the collector of the first transistor injects and the base of the first logic transistor is formed in the form of a nanolayer of a height of not less than 10 nm on the field I type conductivity, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor, the area of the I-type conductivity, which is the collector of the first logic transistor is formed in the form of a nanolayer of a height of not less than 10 nm in region II conduction type, which is the collector of the first transistor injects and the base of the first logic transistor, the input region of the first type conductivity, each of which is the emitter of the first logic transistor is formed in the form of a nanolayer of a height of not less than 10 nm in region II type conductivity, which is the collector of the first transistor injects and the base of the first logic transistor.

The technical result achieved by providing implementations of all of the declared essential features, is that you created a new tonkel any integral logical element AND-NOT on the basis of a layered three-dimensional nanostructures with vertically oriented layers, in which work transitions "base-emitter and base-collector surface are transitions that have low power consumption and minimal surfaces of transitions that provides reduced power consumption and improve performance by reducing the stray capacitance of the transitions.

The essence of the claimed utility model is illustrated by the figures, where

figure 1 shows the principal generalized diagram of the inventive integrated logical element AND-NOT on the basis of the layered three-dimensional nanostructures (front),

figure 2 shows the principal generalized diagram of the inventive integrated logical element AND-NOT on the basis of the layered three-dimensional nanostructures (right side view),

figure 3 shows the principal generalized diagram of the inventive integrated logical element AND-NOT on the basis of the layered three-dimensional nanostructures (rear view),

figure 4 shows the principal generalized diagram of the inventive integrated logical element AND-NOT on the basis of the layered three-dimensional nanostructures (left side view),

figure 5, 6, 7 shows diagrams explaining the operation of the device,

on Fig presents equivalent transistor diagram illustrating the operation of the device,

figure 9 shows the transfer function of the integral of the logical element AND-NOT on the basis of Kostyrchenko nanostructures (1), when the input voltage (2), which demonstrates the implementation of a nanostructure enabled by the scheme (figure 5, 6, 7), the implementation of the reverse function, which speaks to its performance.

figure 10 schedule provided the total current through the power contact E,

figure 11 schedule provided the total current through the contact zero potential,

on Fig provided a graph of the total current through the contact of the first sign,

on Fig provided a graph of the total current through the output pin,

on Fig the results of the integrated logical element AND-NOT on the basis of the layered three-dimensional nanostructures included in the scheme (figure 5, 6, 7) in two modes: when the input voltage logical zero (uin=u0), and when the input voltage logical units (uin=u1for the following parameter:

a) the electron density distribution;

on Fig the results of the integrated logical element AND-NOT on the basis of the layered three-dimensional nanostructures included in the scheme (figure 5, 6, 7) in two modes: when the input voltage logical zero (uin=u0), and when the input voltage logical units (uin=u1for the following parameter:

b) the density distribution holes;

on Fig the results of the work integralov the logical element AND-NOT on the basis of the layered three-dimensional nanostructures, included in the scheme (figure 5, 6, 7) in two modes: when the input voltage logical zero (uin=u0and when the input voltage logical units (uin=u1for the following parameter:

in) - absolute value of the total current in the nanostructure;

on Fig the results of the integrated logical element AND-NOT on the basis of the layered three-dimensional nanostructures included in the scheme (figure 5, 6, 7) in two modes: when the input voltage logical zero (uin=u0and when the input voltage logical units (uin=u1for the following parameter:

d) the spatial distribution of charge;

on Fig the results of the integrated logic element

And NOT on the basis of the layered three-dimensional nanostructures included in the scheme (figure 5, 6, 7) in two modes: when the input voltage logical zero (uin=u0), and when the input voltage logical units (uin=u1for the following parameter:

d) is the electrostatic potential.

In figures 1-4, illustrating the description of the utility model presents the following positions:

1 - substrate of the second conductivity type (P II), which is the emitter of the first transistor injects and emitter of the second injects transit the RA;

2 - dielectric isolation between transistors;

3 - region of the first conductivity type (P I), which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor;

4 - contact region, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor;

5 - dielectric insulation between the contact region, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor, and a contact region, which is the collector of the second transistor injects and the base of the first logic transistor;

6 - contact region, which is the collector of the second transistor injects and base of the second logic transistor;

7 - dielectric insulation between the contact region, which is the collector of the second transistor injects and the base of the first logic transistor, and the area, which is the collector of the second logic transistor;

8 - contact region, which is the collector of the second logic transistor;

9 - region of the first conductivity type (P I), which is the collector of the second logical the second transistor;

10 - region of the second conductivity type (P II), which is the collector of the second transistor injects and base of the second logic transistor;

11 - dielectric isolation between transistors;

12 - surface transition between the area, which is the collector of the second logic transistor, and the area, which is the collector of the second transistor injects and base of the second logic transistor;

13 - surface transition between the area, which is the collector of the second transistor injects and base of the second logic transistor, and the area, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor;

14 - surface transition between the area, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor, and the area, which is the emitter of the first transistor injects and emitter of the second transistor injects;

15 - contact power;

16 - dielectric isolation between transistors;

17 - dielectric insulation between the contact region, which is the collector of the second logic transistor, and a contact region, which is what I emitter of the first logic transistor;

18 - contact region, which is the first emitter of the first logic transistor;

19 - dielectric insulation between the first and second emitters of the first logic transistor;

20 - contact region, which is the second emitter of the first logic transistor;

21 - dielectric isolation between transistors;

22 - region of the first conductivity type (P I), which is the first emitter of the first logic transistor;

23 - the region of the first conduction type (P I), which is the second emitter of the first logic transistor;

24 - region of the second conductivity type (P II), which is the collector of the first transistor injects and the base of the first logic transistor;

25 - surface junction between the region, which is the second emitter of the first logic transistor, and the area, which is the collector of the first transistor injects and the base of the first logic transistor;

26 - surface transition between the area, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor, and the area, which is the collector of the first transistor injects and the base of the first logic transistor;

27 - surface transition between the area which is the first emitter of the first logic transistor, and the area, which is the collector of the first transistor injects and the base of the first logic transistor;

28 - dielectric insulation between the area that is the second emitter of the first logic transistor, and the area, which is the collector of the first logic transistor;

29 - region of the first conductivity type (P I), which is the collector of the first logic transistor;

30 - dielectric insulation between area, which is the collector of the first logic transistor, and a contact region, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor;

31 - surface transition between the area, which is the collector of the first logic transistor, and the area, which is the collector of the first transistor injects and the base of the first logic transistor;

32 - dielectric insulation.

Integrated logical element AND-NOT on the basis of a layered three-dimensional nanostructures (figure 1, 2, 3, 4) includes: a substrate of a second conductivity type (P II), which is the emitter of the first transistor injects and emitter of the second transistor injects (1), dialect the systematic isolation between transistors (2), region of the first conductivity type (P I), which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor (3), the contact area, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor (4), the dielectric insulation between the contact region, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor, and a contact region, which is the collector of the second transistor injects and the base of the first logic transistor (5), the contact area, which is the collector the second injects transistor and the base of the second logic transistor (6), the dielectric insulation between the contact region, which is the collector of the second transistor injects and the base of the first logic transistor, and the area, which is the collector of the second logic transistor (7), the contact area, which is the collector of the second logic transistor (8), the region of the first conduction type (P I), which is the collector of the second logic transistor (9), the region of the second conductivity type (P II), which is the collector is m injects the second transistor and the base of the second logic transistor (10), dielectric isolation between transistors (11), the surface transition between the area, which is the collector of the second logic transistor, and the area, which is the collector of the second transistor injects and base of the second logic transistor (12), the surface transition between the area, which is the collector of the second transistor injects and base of the second logic transistor, and the area, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor (13), the surface transition between the area, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor, and the area, which is the emitter of the first transistor injects and emitter of the second transistor injects (14), the power contact (15), dielectric isolation between transistors (16), the dielectric insulation between the contact region, which is the collector of the second logic transistor, and a contact region, which is the emitter of the first logic transistor (17), the contact area, which is the first emitter of the first logic transistor (18), a dielectric isolation between the first and second em what Terumi first logic transistor (19), the contact area, which is the second emitter of the first logic transistor (20), a dielectric isolation between transistors (21), the region of the first conduction type (P I), which is the first emitter of the first logic transistor (22), a region of the first conduction type (P I), which is the second emitter of the first logic transistor (23), the region of the second conductivity type (P II), which is the collector of the first transistor injects and the base of the first logic transistor (24), surface transition between a region, which is the second emitter of the first logic transistor, and the area, which is the collector of the first transistor injects and the base of the first logic transistor (25), the surface transition between the area, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor, and the area, which is the collector of the first transistor injects and the base of the first logic transistor (26), the surface transition between the region, which is the first emitter of the first logic transistor, and the area, which is the collector of the first transistor injects and the base of the first logic transistor (27), the dielectric insulation between the at region, which is the second emitter of the first logic transistor, and the area, which is the collector of the first logic transistor (28), the region of the first conduction type (P I), which is the collector of the first logic transistor (29), dielectric isolation between area, which is the collector of the first logic transistor, and a contact region, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor (30), the surface transition between the area, which is the collector of the first logic transistor, and the area, which is the collector of the first transistor injects and the base of the first logic transistor (31), a dielectric isolation (32).

Integrated logical element AND-NOT on the basis of a layered three-dimensional nanostructures made of nanoscale with stepped profile.

The area of the I-type conductivity, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor is formed in the form of a nanolayer of a height not less than 3 nm on the substrate by a height of not less than 15 nm II-type conductivity, which is the emitter of the first transistor injects and emitter of the second injects t is ancestor.

Region II-type conductivity, which is the collector of the second transistor injects and base of the second logic transistor is formed in the form of a nanolayer of a height not less than 3 nm in the region of the first type conductivity, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor.

The area of the I-type conductivity, which is the collector of the second logic transistor is formed in the form of a nanolayer of a height of not less than 10 nm in region II type conductivity, which is a manifold injects the second transistor and the base of the first logic transistor.

Region II-type conductivity, which is the collector of the first transistor injects and the base of the first logic transistor is formed in the form of a nanolayer of a height of not less than 10 nm on the field I type conductivity, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor.

The area of the I-type conductivity, which is the collector of the first logic transistor is formed in the form of a nanolayer of a height of not less than 10 nm in region II type conductivity, which is the collector of the first transistor injects and the base of the first logical implemented the Torah.

The input region of the first type conductivity, each of which is the emitter of the first logic transistor is formed in the form of a nanolayer of a height of not less than 10 nm in region II type conductivity, which is the collector of the first transistor injects and the base of the first logic transistor.

The collector contact, the base contact and the emitter contact are contact pads.

The nanolayers can be formed using any known techniques of forming a surface semiconductor nanolayers, such as molecular breeding.

The proposed scheme can be used as part of performing the function.

For n-p-n transistor to eliminate the effect of the parasitic transistor formed by the p-substrate p-substrate can be replaced by an insulating, for example, from the technical sapphire.

Operation of the proposed scheme is illustrated on the example of the circuit operation AND IS NOT, including:

area (3), which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor is formed in the form of a nanolayer of n-type (Si n-type) height not less than 3 nm on the substrate (1) p-type Si p-type) height not less than 15 nm, which is the emitter of the first transistor injects and emitter of the second injector the subsequent transistor

area (10), which is the collector of the second transistor injects and base of the second logic transistor is formed in the form of a nanolayer of p-type Si p-type) height not less than 3 nm in the region of n-type (S1 n-type) (3), which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor

area (9), which is the collector of the second logic transistor is formed in the form of a nanolayer of n-type (Si n-type) height not less than 10 nm on the field of p-type Si p-type) (10), which is the collector of the second transistor injects and base of the second logic transistor

area (24), which is the collector of the first transistor injects and the base of the first logic transistor is formed in the form of a nanolayer of p-type Si p-type) height not less than 10 nm in the region of n-type Si n-type) (3), which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor

area (29), which is the collector of the first logic transistor is formed in the form of a nanolayer of n-type (Si n-type) height not less than 10 nm on the field of p-type Si p-type) (24), which is the collector of the first transistor injects and the base of the first logic transistor

two of the regions (22, 23), each of which is the emitter of the first logic transistor is formed in the form of a nanolayer of n-type (Si n-type) height not less than 10 nm on the field of p-type Si p-type) (24), which is the collector of the first transistor injects and the base of the first logic transistor.

The device operates as follows.

To test the operation of nanostructures AND NOT include it as shown in figure 5, 6, 7.

At the first input (pin (18)) is linearly varying input voltage from 0 V to 0.9 Century To the second input (pin (20)) is the voltage of 0.9 Century

The output (pin (8)) is the transfer function (Fig.9) with two stable States, which correspond to two modes of circuit operation:

mode 1 is when the first input (pin (18)) voltage logical zero u0 (low voltage level (0.1 to 0.2 In))and the second (contact (20)) the voltage of the logic unit u1 (0.9 In),

- mode 2 - when the first input (pin (18)) the voltage of the logic unit u1 (high level voltage (0.9 V)) and second (contact (20)) the voltage of the logic unit u1 (0.9 In).

Consider the integral of the logical element AND-NOT on the basis of a layered three-dimensional nanostructures for both modes.

Mode 1. When applying to the first input (pin (18)) voltage logical zero u0 the first surface junction base-emitter voltage is, I can pay tithing logic transistor nanostructures is open, the second surface junction base-emitter voltage of the first logic transistor is closed. The emitter of the first transistor injects injects into the base of the first logic transistor media, and then the current passes through the first open transition base-emitter voltage in the drive circuit. Part patterns corresponding to the second logic transistor(9)-(10)-(3), closed, the output (pin (8)) the voltage of the logic unit.

Mode 2. When applying for all inputs (contacts (18)(20)) logical unit u1 surface transitions ((25) and (27)are closed, current from injector (region (1)) is supplied to the base region (region (10)) of the second logic transistor opens and fills it. As a result, output area (area (9)), which is the collector of the second logic transistor, a low voltage level.

Analysis of nanostructures AND IS NOT generated by the nanolayers 1, 3, 9, 10, 22, 23, 24, 29, proves its performance and function.

The proposed integrated logical element AND-NOT on the basis of a layered three-dimensional nanostructures provides high information density (due to the use of nano-layered structure (surface p-n junctions) and three-dimensional implementation of the element) and improved performance (by minimizing stray capacitance due to the three-dimensional element is a and the use of surface transitions) at low power consumption (due to the use of surface transitions).

Integrated logical element AND-NOT on the basis of a layered three-dimensional nanostructures containing the first and second logic transistors, the first and second injects transistors and the substrate, wherein the logical structure of the element AND IS NOT made of nanoscale with stepped profile, the area of the I-type conductivity, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor is formed in the form of a nanolayer of a height not less than 3 nm on the substrate by a height of not less than 15 nm II-type conductivity, which is the emitter of the first transistor injects and emitter of the second transistor injects, region II type conductivity, which is the collector of the second transistor injects and base of the second logic transistor is formed in the form of a nanolayer of a height not less than 3 nm in the region of the first type conductivity, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor, the area of the I-type conductivity, which is the collector of the second logic transistor is formed in the form of a nanolayer of a height of not less than 10 nm in region II type conductivity, which is the collector of the second transistor injects and basic the second logic transistor, region II-type conductivity, which is the collector of the first transistor injects and the base of the first logic transistor is formed in the form of a nanolayer of a height of not less than 10 nm on the field I type conductivity, which is the base of the first transistor injects, base injects the second transistor and the emitter of the second logic transistor, the area of the I-type conductivity, which is the collector of the first logic transistor is formed in the form of a nanolayer of a height of not less than 10 nm in region II type conductivity, which is the collector of the first transistor injects and the base of the first logic transistor, the input region of the first type conductivity, each of which is the emitter of the first logic transistor is formed in the form of a nanolayer of a height of not less than 10 nm in region II type conductivity, which is the collector of the first transistor injects and the base of the first logic transistor.



 

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FIELD: medicine, pharmaceutics.

SUBSTANCE: this invention represents a composition and methods for production of stable docetaxel pharmaceutical compositions. In one implementation version the invention represents a pharmaceutical composition containing docetaxel nano-particles, dry form docetaxel used for the composition production. The average size of the nano-particles is no more than 200 nm. The composition additionally includes a biocompatible polymer representing the carrier protein which is albumin. In the second version the pharmaceutical composition includes docetaxel nano-particles and additionally contains a citrate. According to the invention, the compositions are physically stable and show no signs of sedimentation or precipitation during at least 8 hours after repeated recovery or repeated hydration.

EFFECT: composition is used for production of a medication for cancer treatment.

116 cl, 7 dwg, 6 tbl, 39 ex

FIELD: medicine, pharmaceutics.

SUBSTANCE: invention relates to medicine and deals with an anti-tumour preparation representing stable nano-particles and including a cytostatic, a bio-degrading polymer, a surfactant, a cryoprotectant and a vector molecule for precise delivery of the particles to the affected organs and tissues. The cytostatic is represented by paclitoxel with the vector molecule for precise delivery of the particles to the affected organs and tissues is represented by C-end domain of alpha-fetoprotein.

EFFECT: invention provides for the preparation effectiveness improvement.

1 cl, 6 ex, 3 dwg

FIELD: chemistry.

SUBSTANCE: method involves dissolving 15-20 pts.wt polyvinyl alcohol in an aqueous suspension of carbon fulleroid nanomodifier in amount of 0.01-1.0 pts.wt per 100 pts.wt water.

EFFECT: high adhesion strength of carbon rods to a carbon matrix in a carbon-carbon composite material.

1 dwg, 1 tbl, 13 ex

FIELD: chemistry.

SUBSTANCE: method of producing silicon dioxide-based thin nanostructured single-layer coatings involves a silicon tretraalkoxide sol gel process in the presence of an additive of hydrochloric acid and yttrium chloride, in the presence of which, after heating, a transparent silicon dioxide-based film having an antireflection effect is formed. A film-forming solution is prepared with the following ratio of components, wt %: tetraethoxysilane 4.37-5.81, yttrium chloride crystalline hydrate 6.65-8.67, hydrochloric acid - 0.01, 96 wt % ethyl alcohol being the balance. After maturation, the film-forming solution is deposited onto a glass substrate and subjected to thermal treatment in steps. The sample is heated in an air atmosphere at 500-700°C for one hour.

EFFECT: shorter time for obtaining an antireflection nanoporous coating.

3 ex

FIELD: physics.

SUBSTANCE: when investigating the magnetic-noncollinear state of a nanolayer, the investigated nanolayer is placed inside a three-layer polarised neutron resonator, wherein the middle layer of the resonator is non-uniform and neutrons scattered on these non-uniformities are picked up at sliding angles of the scattered bream which exceed the sliding angle of neutron total reflection.

EFFECT: possibility of measuring magnetic-noncollinear power of a nanolayer with high sensitivity.

2 dwg

Magnetic materials // 2244971

FIELD: magnetic materials whose axial symmetry is used for imparting magnetic properties to materials.

SUBSTANCE: memory element has nanomagnetic materials whose axial symmetry is chosen to obtain high residual magnetic induction and respective coercive force. This enlarges body of information stored on information media.

EFFECT: enhanced speed of nonvolatile memory integrated circuits for computers of low power requirement.

4 cl, 8 dwg

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