Homogeneous computing environment cell and homogeneous computing environment cell based binary vector compression device

FIELD: information technology.

SUBSTANCE: device has a matrix of homogeneous computing environment cells, having m-1 rows and m-1 columns, where m is the number of bits of the input signal, wherein a cell contains an OR element, an AND element and two flip-flops.

EFFECT: high reliability of a homogeneous computing environment owing to fewer connections between homogeneous computing environment cells and faster operation owing to use of faster homogeneous computing environment cells.

3 dwg, 1 tbl

 

The invention relates to computing and is designed to build homogeneous computing environments, performing compression of binary vectors.

Homogeneous computing environment is called a regular structure consisting of interconnected identical cells that perform a specific function. Cell homogeneous computing environment is an element of a regular structure. The bits of the vector are coded status signal and correspond to the values of the logical unit or logical zero on the inputs and outputs of a cell of a homogeneous computing environment.

Known technical solution cell homogeneous computing environment, patented as an invention - patent RU 2284568 C2, which contains two data and one control inputs, two outputs, the four elements And two of the item, the item OR the relevant links. The disadvantage is that the device is not implemented conveyor principle of information processing, which significantly reduces the operating speed of the device.

Closest to the claimed technical solution is the solution cell of a homogeneous computing environment, inventor's certificate SU # 1513471 A1, which contains the synchronization input 1, the first 2 and second 3 informational inputs, logic inputs 4-6, the first 7 and second 8 function outputs, triggers, 9, 11, electricity, water, the coefficients are NOT 10, 13, 19, elements And 14, 16-18, items, OR 12, 15 with the relevant contacts.

The disadvantage is the relatively low performance of the cell, which is 4t, where t is the delay time of the signal of one logic element in the proposed decision, the delay time is reduced four times.

The technical result of the proposed solutions: the present invention aims at improving the performance of the cell by reducing the number of elements in the chain of distribution of the information signal and relationships: a first information input cell connected to the first input element OR the second input element OR is connected to a second information input cell, the first and second information inputs of the cell are connected respectively to the first and second input element And the output of which is connected to the information input of the second trigger.

Description of the technical solution of the cell: the cell is homogeneous computing environment consists of one two-input And gates, one input of the OR element and two triggers, the trigger input of the cell is connected to the inputs of the synchronization of the first and second trigger, the output element OR connected to the information input of the first trigger, the first information input of the cell connected to the first input element OR the second input element OR is connected to a second information input I the side, the output of which is connected to the information input of the first trigger, the first and second information inputs of the cell are connected respectively to the first and second input element And the output of which is connected to the information input of the second trigger, the information outputs of the first and second trigger is the first and the second information outputs of the cell.

An example of building cells can serve as its schema created by programming programmable logic integrated circuits (FPGA).

Figure 1 shows a functional diagram of a cell of a homogeneous structure, where 1, 2 and information input, 3 - input synchronization, 4, 5 and information outputs, 6 - element, OR 7 - item, 8, 9 triggers.

The homogeneous cell structure implements the following logical functions:

Q1(t)=a∨b

Q2(t)=a·b

where a, b, respectively, the state of signals on inputs 1 and 2 cells;

Q1(t), Q2(t), respectively the state of the signals at the outputs 4 and 5 of the cell.

The cell operates as follows.

Input aEntrance bQ1(t)Q2(t)
0000
0101
1001
1111

The second proposed solution is a device for compression of binary vectors based cells homogeneous computing environment of the considered type.

Known technical solution of the homogeneous computing environment, patented as an invention - patent RU 2284568 C2. The device comprises: a cell is a homogeneous computing environment 1,1-1,m, 2,1-2,m,..., n,1-n,m, informational inputs a0-anb0-bminformation outputs p0-pnc0-cmthe control input M, connected to the control inputs m, each cell in a homogeneous computing environment.. the Disadvantage is that the device is not implemented conveyor principle of information processing, which significantly reduces the operating speed of the device.

Closest to the claimed solution of the technical solution of a homogeneous computing environment, inventor's certificate SU # 1513471 A1. The device is constructed on the basis of cells. In the process, the device information is vector applied to the inputs 2 and 3 cells in the first column, moreover, the i-th bit of the vector is supplied to the input 2 (i, 1) cells and input 3 (i+1, 1) cell. Logical vector applied to the inputs 4-6 cells of the first column and i-th bit of the vector is input 6 (i, 1) cells and input 4 (i-1, 1) cell. The disadvantage is that the device works not only with the information vector, but with the logic that leads to the increase of connections between cells in a homogeneous environment, which in turn leads to a decrease in reliability.

The technical result of the proposed solutions: the present invention aims to improve the reliability of homogeneous computing environment by reducing the number of connections between cells in a homogeneous computing environment and improve performance through the use of faster cell homogeneous computing environment: the first and second information inputs (m/2) cells of the first column of homogeneous computing environment even when the value of m is connected with the corresponding bits of m-bit vector, with the odd value of m m-bit vector is connected with the respective information inputs ((m+1)/2) cells of the first column, and the remaining unused inputs of the cells of the first column are connected with a value of logical zero, the first information output each (i, j)-th cell is connected to a second information entry (i, j+1)-th cell, the second information in the course of each (i, j)-th cell is connected to the first information input of the (1+1, j+1)th cells, except the cells of the first row, starting from the second column, the first information input of which is connected with the value of the logical unit.

Description technical solutions device for compression of binary vectors based cells homogeneous computing environment.

Homogeneous computing environment of the cells examined type, providing compression of binary vectors is a matrix: the number of columns of homogeneous computing environment is equal to m-1, the number of rows homogeneous computing environment is equal to m-1. The first and second information inputs (m/2) cells of the first column of homogeneous computing environment even when the value of m serves the corresponding bits of m-bit vector, with the odd value of m m-bit vector is connected with the respective information inputs ((m+1)/2) of the first column of the matrix is homogeneous computing environment, and the remaining unused inputs of the cells of the first column submitted value is a logical zero, the first information output each (i, j)-th cell is connected to a second information entry (i, j+1)-th cell, the second information output each (i, j)-th cell is connected to the first information input (i+1, j+1)th cells, except the cells of the first row, starting from the second column on the first information the input of which is filed logical units.

Description of the operation of the device: in each step of the inputs of the synchronization trigger signal synchronization. As a result, the vector is transferred to a neighboring right column transformed. The value of the i-th bit of the vector in the j-th column is determined by the value of the (i-1)-th bit of vector b (j-1)-th column. As a result, after (m-1) cycle of the device is compressed m-dimensional binary vector. The first and second information outputs of the last (m/2) cells of the last column of homogeneous computing environment even when the value of m and the first and second information outputs ((m+1)/2) cells of the last column of homogeneous computing environment with the odd value of m are the outputs of the circuit to be the result. The outputs of the remaining cells will be present in the logical unit. Since at each step of operation of the device vector is transmitted in the adjacent right column of matrix cells, the input device on each step can be served the next vector. Thus, the device implements a conveyor principle of information processing.

As in the cell both chain propagation have one logical element, the delay time of signal propagation in is t, where t is the delay time of the signal of one logic element means, the operating time of the entire homogeneous computing environment is (m-1)*t, is smaller than four times compared with the original version on author. St. No. 1513471 A1, is equal to (m-1)*4t.

An example of building a homogeneous computing environment can serve as its schema created by programming the FPGA.

Figure 2 presents a structural diagram of a homogeneous computing environment in General on the basis of homogeneous cell structure, designed to compress the m-dimensional binary vectors with an even value of m, where CELL - cell homogeneous structure, information inputs X1-Xminformation outputs Y1-Ym.

Figure 3 shows an example of the operation of the compression of the binary vector X=101000 with the bit width m=6, filed for informational inputs X1-X6homogeneous computing environment. While figure 3 shows the data transfer from the outputs of the j-th column to corresponding inputs of a (j+1)-th column. After five cycles of operation the compression Y=000011 available at the outputs Y1-Y6homogeneous computing environment.

1. Cell homogeneous computing environment containing the first and second information inputs, input synchronization, two information outputs, two-element OR two-element And the first trigger information with one input and one trigger input, the second trigger information with one input and one input of the synchronization, the synchronization input of the cell is connected to the inputs of the synchronization of the first and W is the art of triggers, the output element OR connected to the information input of the first trigger, the information outputs of the first and second triggers are connected respectively to the first and second data outputs of the cell, characterized in that the first information input of the cell connected to the first input element OR the second input element OR is connected to a second information input cell, the first and second information inputs of the cell are connected respectively to first and second inputs of the element And whose output is connected to the information input of the second trigger.

2. Device for compression of binary vectors based cells homogeneous computing environment, consisting of a matrix of cells, the number of columns of the matrix a homogeneous computing environment is equal to m-1, where the number of rows of the matrix a homogeneous computing environment is equal to m-1, wherein the first and second information inputs m/2 cells in the first column of the matrix is homogeneous computing environment even when the value of m, where m is the number of bits of the input signal, connected to respective bits of the m-bit input signal, an odd value of m m-bit input signal is connected to the appropriate information inputs (m+1)/2 of the first column of the matrix a homogeneous computing environment, and the remaining unused inputs of the cells of the first column connect the us with a value of logical zero, the first information output each (i, j)-th cell is connected to a second information entry (i, j+1)-th cell, the second information output each (i, j)-th cell is connected to the first information input (i+1, j+1)th cells, except the cells of the first row, starting from the second column, the first information input of which is connected with the value of the logical units, the first and second information outputs of the last m/2 cells in the last column of the matrix a homogeneous computing environment even when the value of m and the first and the second information outputs (m+1)/2 cells in the last column of the matrix a homogeneous computing environment with the odd value of m are the outputs of the circuit to be the result, the cell homogeneous computing environment is made of a two-input And gates, one input of the OR element and two triggers, the trigger input of the cell is connected to the inputs of the synchronization of the first and second triggers, the output element OR connected to the information input of the first trigger, the first information input of the cell connected to the first input element OR the second input element OR is connected to the second information input of the cell, the output of which is connected to the information input of the first trigger, the first and second information inputs of the cell are connected respectively to first and second inputs of the element And, the output of which is connected to the information input of the second trigger, the information outputs of the first and second triggers are the first and the second information outputs of the cell.



 

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