Semiconductor structure of logical element and-not

FIELD: electricity.

SUBSTANCE: semiconductor structure of the logical element AND-NOT comprising the first and second logical transistors, the first and second injecting transistors and a substrate is made as nanosized with a stepped profile and comprises four collectors, four bases and at least four emitters on the substrate of the first type of conductivity.

EFFECT: reduced consumed power and increased efficiency.

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The invention relates to a semiconductor microelectronics and nanoelectronics and can be used to create logic integrated circuits with elements of nanometer size.

Known complementary bipolar scheme AND NOT containing the first and second logic transistor of the first conductivity type and first and second injects transistors of the second conductivity type and the substrate of the first conductivity type (Patent RF №2073935, IPC H01L 27/04, published 20.02.1997).

The disadvantages of the known devices are:

1. Poor performance due to the implementation of the scheme using epitaxial-planar technology and with the use of transistor circuitry involving the technological realization of the presence of the isolating manifold pockets for transistors.

2. Low information density, due to the formation of a transistor effects in insulating the collector pockets.

3. Increased power consumption due to the use of a semiconductor substrate, which leads to extra power consumption of the parasitic p-n-p transistor formed by the substrate - collector and base of transistors.

The technical task to be solved by the invention, is to create a logical structure AND nanometer size have what she increased speed and information density.

The technical problem is solved in that the semiconductor structure of the logical element AND-NOT containing first and second logic transistors, the first and second injects transistors and the substrate, according to the invention is made of nano, with stepped profile contains four collector, four bases and at least four of the emitter on the substrate of the first conductivity type, which is the collector of the second logic transistor and height not less than 15 nm, formed the base region of the second logic transistor of the second conductivity type, which is the collector of the second injectibles transistor in the form of a nanolayer of a height not less than 3 nm, which the formed emitter region of the second logic transistor of the first conductivity type, which is also the base of the second transistor injects, in the form of a nanolayer of a height not less than 3 nm, is connected to zero potential, which formed the area of the emitter injects the second transistor of the second conductivity type, which is also the emitter of the first transistor injects, in the form of a nanolayer of a height of not less than 10 nm, connected to power, it formed the collector region of the first logic transistor of the first conductivity type, which is also the base of the first injectisome the camping transistor, in the form of a nanolayer of a height not less than 3 nm, which formed the base region of the first logic transistor of the second conductivity type, which is also the collector of the first injectibles transistor in the form of a nanolayer of a height not less than 3 nm, which formed the area of the first and second emitters of the first logic transistor of the first conductivity type, in the form of a nanolayer of a height of not less than 10 nm.

The technical result achieved by providing implementations of all of the declared essential features, is that you created a new thin-layer logical structure AND-HE nanometer size with vertically oriented layers, which work transitions "base-emitter and base-collector of the first and second logical and of the first and second logical injects transistors are surface transitions, which have low power consumption and minimal surfaces of transitions that provides reduced power consumption and improve performance by reducing the stray capacitance of the transitions.

Optional: if the substrate is to use a dielectric substrate, the power consumption will decrease even by eliminating the parasitic transistor, comprising a semiconductor substrate of the second conductivity type, the region is the first conductivity type, which is the collector of the second logic transistor region of the second conductivity type, which is the base of the second logic transistor and a collector of the second injectibles transistor.

The essence of the invention is illustrated by drawings, where

figure 1 shows the principal generalized diagram of the inventive logical structure AND NOT (front);

figure 2 shows the principal generalized diagram of the inventive logical structure AND IS NOT (top view);

figure 3 shows the principal generalized diagram of the inventive logical structure AND NOT (side view);

figure 4 is a diagram explaining the operation of the device,

figure 5 shows the equivalent transistor diagram illustrating the operation of the device;

figure 6 shows the transfer characteristic of the logical structure AND IS NOT (1) when the input voltage (2), which demonstrates the implementation of nanostructure AND IS NOT included in the diagram (figure 4, figure 5), the implementation of the reverse function, which indicates its serviceability;

7 given a graph of the total current through the power contact E,

on Fig provided a graph of the total current through the contact zero potential;

figure 9 schedule provided the total current through the contact of the first input;

figure 10 schedule provided the total current through the output contact;

figure 11 p is Evegeny the results of the logical structure AND IS NOT, included in the diagram (figure 4) in two modes: when the input voltage logical zero (uin=u0and when the input voltage logical units (uin=u1for the following options:

a) the electron density distribution; b) the density distribution holes;

on Fig presents the results of the logical structure AND IS NOT included in the diagram (figure 3) in two modes: when the input voltage logical zero (uin=u0and when the input voltage logical units (uin=u1for the following options:

C) the absolute value of the total current in the nanostructure of a bipolar transistor; g) the distribution of space charge;

on Fig presents the results of the logical structure AND IS NOT included in the diagram (figure 3) in two modes: when the input voltage logical zero (uin=u0and when the input voltage logical units (uin=u1for the following options:

d) electrostatic potential.

In figures 1-3, illustrating the invention, presents the following positions:

1 - substrate of the first conductivity type, which is also the collector of the second logic transistor

2 - contact collector of the second logic transistor

3 - the base region of the second logical TRANS is Stora second conductivity type, which is also the collector of the second injectibles transistor

4 - surface junction base-emitter voltage of the second logic transistor, which is also the surface transition "base-collector of the second transistor injects,

5 - region of the emitter of the second logic transistor of the first conductivity type, which is also the base of the second transistor injects,

6 - contact area of the emitter of the second logic transistor, which is also the base of the second transistor injects,

7 - area emitter injects the second transistor of the second conductivity type, which is also the emitter of the first transistor injects,

8 - contact emitter injects the second transistor, which is also the emitter of the first transistor injects,

9 - collector region of the first logic transistor of the first conductivity type, which is also the base of the first transistor injects,

10 - surface junction base-collector of the first logic transistor, which is also the surface transition "base-collector of the first transistor injects,

11 - the base region of the first logic transistor of the second conductivity type, which is also the collector of the first injectibles transistor

12 - surface transition "base-em is tter" the first emitter of the first logic transistor

14 - the region of the first emitter of the first logic transistor of the first conductivity type,

15 - pin of the first emitter of the first logic transistor

16 - the area of the second emitter of the first logic transistor of the first conductivity type,

17 - contact of the second emitter of the first logic transistor

18 - dielectric insulation between the collector contact of the second logic transistor and the contacts of the first and second emitters of the first logic transistor of the first conductivity type,

19 - dielectric isolation between transistors

20 - dielectric insulation between the emitter contact of the second logic transistor, which is also the base of the second transistor injects, and the contact of the emitter injects the second transistor of the second conductivity type, which is also the emitter of the first transistor injects,

21 - dielectric insulation between the contact of the emitter injects the second transistor of the second conductivity type, which is also the emitter of the first transistor injects, and contacts the first and second emitters of the first logic transistor of the first conductivity type.

22 - dielectric insulation between areas of the first and second emitters of the first logic transistor.

The semiconductor structure of l is the logical element AND-NOT (figure 1) includes: a substrate of the first conductivity type, which is the collector of the second logic transistor (1), the collector contact of the second logic transistor (2), the base region of the second logic transistor of the second conductivity type, which is also the collector of the second injectibles transistor (3), the surface transition base-emitter voltage of the second logic transistor, which is also the surface transition "base-collector of the second transistor injects (4), the area of the emitter of the second logic transistor of the first conductivity type, which is also the base of the second transistor injects (5), the contact area of the emitter of the second logic transistor, which is also the base of the second transistor injects (6), the area of the emitter injects the second transistor of the second conductivity type, which is also the emitter of the first transistor injects (7), the contact of the emitter injects the second transistor, which is also the emitter of the first transistor injects (8), the collector region of the first logic transistor of the first conductivity type, which is the base of the first transistor injects (9), surface junction base-collector of the first logic transistor, which is also the surface junction base-collector of the first transistor injects (10), the base region of the first logical t is ancestor second conductivity type, which is also the collector of the first injectibles transistor (11), surface junction base-emitter voltage of the first emitter of the first logic transistor (12), surface junction base-emitter voltage of the second emitter of the first logic transistor (13), the region of the first emitter of the first logic transistor of the first conductivity type (14), the contact of the first emitter of the first logic transistor (15), the area of the second emitter of the first logic transistor of the first conductivity type (16), the contact of the second emitter of the first logic transistor (17), dielectric isolation between the collector contact of the second logic transistor and the contacts of the first and the second emitters of the first logic transistor of the first conductivity type (18), a dielectric isolation between transistors (19), dielectric isolation between the emitter contact of the second logic transistor, which is also the base of the second transistor injects, and the contact of the emitter injects the second transistor of the second conductivity type, which is also the emitter of the first transistor injects (20), a dielectric isolation between the contact of the emitter injects the second transistor of the second conductivity type, which is also the emitter of the first transistor injects, and contacts the first and vtoro what about the emitters of the first logic transistor of the first conductivity type (21), dielectric isolation between areas of the first and second emitters of the first logic transistor (22).

Logical structure AND IS NOT made of nanoscale with stepped profile.

On the substrate of the first conductivity type, which is the collector of the second logic transistor, a height of not less than 15 nm, formed the base region of the second logic transistor of the second conductivity type, which is the collector of the second injectibles transistor in the form of a nanolayer of a height not less than 3 nm,

which formed the area of the emitter of the second logic transistor of the first conductivity type, which is also the base of the second transistor injects, in the form of a nanolayer of a height not less than 3 nm, is connected to zero potential,

which formed the area of the emitter injects the second transistor of the second conductivity type, which is also the emitter of the first transistor injects, in the form of a nanolayer of a height of not less than 10 nm, connected to power,

on which are formed the collector region of the first logic transistor of the first conductivity type, which is also the base of the first injectibles transistor in the form of a nanolayer of a height not less than 3 nm,

which formed the base region of the first logic transistor of the second conductivity type, which is also the collector of the first injectibles transistor, in the form of a nanolayer of a height not less than 3 nm,

which formed the area of the first and second emitters of the first logic transistor of the first conductivity type in the form of a nanolayer of a height of not less than 10 nm.

The collector contact, the base contact and the emitter contact are contact pads.

The nanolayers can be formed using any known techniques of forming a surface semiconductor nanolayers, for example, epitaxial growth.

The proposed scheme can be used as an element that performs a function AND IS NOT for VLSI with high information density.

To eliminate the effect of the parasitic transistor formed by the p-substrate and the second logic transistor, the p-substrate can be replaced by an insulating, for example from technical sapphire.

Operation of the proposed scheme is illustrated on the example of the scheme AND NOT comprising on a substrate (1) of the first conduction type, which is also the collector of the second logic transistor n-type (Si n-type) height not less than 15 nm, formed region (3) of the second logic transistor of the second conductivity type, which is also the collector of the second injectibles transistor in the form of a nanolayer of p-type Si p-type) height not less than 3 nm, on which is formed a region (5) of the emitter of the second logs the definition of the transistor of the first conductivity type, which is also the base of the second transistor injects, in the form of a nanolayer of n-type (Si n-type) height not less than 3 nm, is connected to zero potential, on which is formed a region (7) of the emitter injects the second transistor of the second conductivity type, which is also the emitter of the first transistor injects, in the form of a nanolayer of n-type Si p-type) height not less than 10 nm, is connected to the power on which is formed a region (9) of the collector of the first logic transistor of the first conductivity type, which is also the base of the first injectibles transistor, in the form of the nanolayer of n-type (Si n-type) height not less than 3 nm, on which is formed a region (11) of the base of the first logic transistor of the second conductivity type, which is also the collector of the first injectibles transistor in the form of a nanolayer of p-type Si p-type) height not less than 3 nm, which formed region (14) and (16) of the first and second emitters of the first logic transistor of the first conductivity type, respectively, in the form of a nanolayer of n-type (Si n-type) height not less than 10 nm.

The device operates as follows.

To test the operation of nanostructures AND NOT include it, as shown in figure 4.

At the first input (pin (15)) is linearly varying input voltage from 0 V to 1.1 Century To the second input (pin (17)is served strain is 1,1 Century

The output (pin (2)) is the transfer function (6) with two stable States, which correspond to two modes of circuit operation:

mode 1 is when the first input (pin (15)) voltage logical zero u0 (low voltage level (0.1 to 0.2 In))and the second (contact (17)) the voltage of the logic unit u1 (0.9 In),

- mode 2 - when the first input (pin (15)) the voltage of the logic unit u1 (high level voltage (1,1)) and second (contact (17)) the voltage of the logic unit u1.

Consider the work of nanostructures AND NOT for both modes.

Mode 1. When applying to the first input (pin (15)) voltage logical zero u0 the first surface junction base-emitter voltage of the first logic transistor nanostructures is open, the second surface junction base-emitter voltage of the first logic transistor is closed. The current of the first transistor injects injects into the base of the first logic transistor media, and then the current passes through the first open transition "base-emmiter" in the drive circuit. Part patterns corresponding to the second logic transistor(1)-(3)-(5), closed, the output (pin (2)), the voltage of the logic unit.

Mode 2. When applying for all inputs (contacts (15) (17)) the logical unit u1, the surface transitions ((12) and (13)) are closed, current from injector (region (7)) post which becomes the base region (region (5)) of the second logic transistor, opens and fills it. As a result, the output region (region (1)), which is the collector of the second logic transistor, a low voltage level.

Analysis of nanostructures AND IS NOT generated by the nanolayers 1, 3, 5, 7, 9, 11, 14, 16, proves its performance and function.

The proposed logical structure AND does NOT provide high information density (due to the use of nano) and improved performance (by reducing the surface area of the navigation structure AND IS NOT and, as a consequence, reduction of parasitic capacitance) at low power consumption.

The semiconductor structure of the logical element AND-NOT containing first and second logic transistors, the first and second injects transistors and the substrate, characterized in that the nanoscale with stepped profile contains four collector, four bases and at least four of the emitter on the substrate of the first conductivity type, which is the collector of the second logic transistor and height not less than 15 nm, formed the base region of the second logic transistor of the second conductivity type, which is the collector of the second injectibles transistor in the form of a nanolayer of a height not less than 3 nm, which formed the area of the emitter of the second logical transisto the and the first conductivity type, which is also the base of the second transistor injects, in the form of a nanolayer of a height not less than 3 nm, is connected to zero potential, which formed the area of the emitter injects the second transistor of the second conductivity type, which is also the emitter of the first transistor injects, in the form of a nanolayer of a height of not less than 10 nm, connected to power, it formed the collector region of the first logic transistor of the first conductivity type, which is also the base of the first injectibles transistor in the form of a nanolayer of a height not less than 3 nm, which formed the base region of the first logic transistor of the second conductivity type, which is also the collector of the first injectibles transistor in the form of a nanolayer of a height not less than 3 nm, which formed the area of the first and second emitters of the first logic transistor of the first conductivity type, in the form of a nanolayer of a height of not less than 10 nm.



 

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