Improving memory read stability using selective precharge

FIELD: information technology.

SUBSTANCE: method of managing a memory device, having a bit line comprising a first section and a second section, involving precharging the first section of the bit line to a first voltage; precharging the second section of the bit line to a second voltage different from the first voltage; and distributing charge between the first section of the bit line and the second section of the bit line to obtain a final voltage between the first voltage and the second voltage.

EFFECT: high read stability owing lower voltage of the bit line.

25 cl, 10 dwg

 

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority on provisional application U.S. No. 61/014038, filed December 15, 2007.

The technical FIELD TO WHICH the INVENTION RELATES

The present invention generally relates to integrated circuits (IC, IC). More precisely, this invention relates to memory devices.

The LEVEL of TECHNOLOGY

The device memory or memory in General can be described as hardware that can store data for later sampling. Some memory devices include a set of transistors used for storing data (for example, presents electric charge), and a set of transistors that are used to control access to the data store. The size of transistors has been reduced to 45 nm, and soon will reach 32 nm. As the size decreased, decreased the relative amount of error is acceptable during production. As a result, the transistors of industrial production show a greater instability during operation.

The large increase of instability in transistor technology had a negative impact on the memory device and the sustainability of their reading. The resistance reading is the ability of the memory device to retain the correct data, when exposed on the stupa in the presence of noise. Typically, the resistance reading is measured using the static margin of noise immunity (SNM). Large variations of the characteristics of the transistors of industrial production cause a reduction in static stability margin of the memory device. This reduction of the static margin of noise immunity reduces the reliability of the bit cells and resistance to noise, and hence, reduces the yield of memory due to higher bounce.

A slight decrease of the voltage of bit lines of the memory device is compared with the voltage significantly improves static supply noise immunity of the memory device. However, in the construction of the memory bit line is typically pre-charged to the supply voltage before accessing memory. There have been several attempts to reduce the voltage of the bit line to improve the stability of the reading. Previous attempts have shown greater sensitivity to changes in process, temperature and voltage during production, which may limit its effectiveness to improve the stability of the reading. Some of these attempts include a pulse diagram of the bit line, dual voltage and dynamic displacement of the cell.

In the pulse circuit bit line discharge device is residenee to the bit line. After pre-charging bit lines to the supply voltage short pulse is sent to a discharge device, which lowers the voltage of the bit line and improves the stability of the reading. This technology is very sensitive to the formation of this short pulse, especially because the pulse duration will vary depending on changes in process, voltage and temperature during production of transistors and external environment changes.

Another attempt uses two supply voltages, one for bit cell, and the other for bit lines, where the voltage of the bit line is lower than the voltage of the bit cell. Adding additional supply voltage is difficult and complicates the design at the physical level and the test chip.

Still one other attempt to reduce the voltage of the bit line includes the use of NMOS devices for pre-charging bit line to reduce the voltage of the bit line, a threshold voltage of the NMOS device. In this case, is used NMOS device with low threshold voltage, which increases the complexity of the technological process and cost, for example, requiring additional masks. In addition, the threshold voltage has a strong dependence on the change in the response process, voltage and temperature.

These three attempts to improve the stability of the read memory is sensitive to changes of the production process and, in fact, difficult to implement and costly to implement. This cost can be further enhanced when the multiple voltage supply unit or implemented in NMOS circuits pre-charging. Thus, there is a need for improved sustainability read into the memory structures, which reduces the sensitivity to changes in the production process, without incurring the additional costs.

A BRIEF summary of the INVENTION

In accordance with one aspect of this disclosure, a memory device includes a bit line having a first section and a second section. The memory device also includes a distribution charge, selectively attachable to the first area and the second area in which the scheme of distribution of charge is configured to attach and detach the first section from the second section.

In accordance with another aspect of this disclosure, a method of controlling the memory device includes a pre-charging the first section bit line to a first voltage and a pre-charging the second section bit line to the second voltage. Vtoro the voltage is different from the first voltage. The method also includes the distribution of charge between the first section bit line and the second section bit line.

In accordance with one other aspect of this disclosure, a memory device includes a means for pre-charging the first section bit line to the first voltage. The memory device also includes means for pre-charging the second section bit line to the second voltage. The memory device additionally includes means for distributing charge between the first section bit line and the second section bit line.

In accordance with an additional aspect of the disclosure, a method of controlling a memory device having a bit line comprising a first section and a second section, includes pre-charging the first section bit line to the first voltage. The method additionally includes the stage of pre-charging the second section bit line to a second voltage that is different from the first voltage. The method also includes the step distribution of the charge between the first section bit line and the second section bit line for receiving a voltage level between the first voltage and the second voltage.

Above, in General terms, describes the characteristics and technical is the cue advantages of the present disclosure, in order to be better understood by the detailed description which follows. Additional characteristics and advantages of the disclosure will be described below. Specialists in this field of technology should be taken into account that this disclosure can easily be used as a basis for modifying or designing other structures for performing identical or similar purposes of the present disclosure. Specialists in this field of technology should also be understood that such equivalent constructions do not depart from the principles set forth in the accompanying claims. New signs, which are assumed characteristics of the disclosure, both in terms of its organization and method of operation, together with additional objectives and advantages will be better understood from the following description when considered in connection with the attached figures. However, it should be clearly understood that each of the figures is given solely for the purpose of illustration and description and is not intended as a definition of the boundaries of the present disclosure.

BRIEF DESCRIPTION of DRAWINGS

For a more complete understanding of the disclosure in this application the following is a detailed description of the invention with reference to the accompanying drawings, on which:

Fig. 1 illustrates an exemplary wireless communication system, which which mainly can be used variant of implementation of the disclosure;

Fig. 2A is a diagram, schematically illustrating a conventional pulse diagram of the bit lines for improved stability of the SRAM;

Fig. 2B is a timing diagram illustrating the conventional pulse diagram of the bit lines for improved stability of the SRAM;

Fig. 3 is a schematic diagram illustrating the operation of the initial pre-charging in an exemplary technology selective pre-charging according to one of embodiments of the disclosure;

Fig. 4 is a schematic diagram illustrating the operation of the charge distribution in the sample of election technology pre-charging according to one of embodiments of the disclosure;

Fig. 5 is a schematic diagram illustrating the sampling of the bit cell for reading or writing according to one of embodiments of the disclosure;

Fig. 6 is a schematic diagram illustrating a pre-charging bit lines to different voltages in the approximate technologies electoral pre-charging according to one of embodiments of the disclosure;

Fig. 7 is a timing diagram illustrating exemplary operation of the electoral pre-charging according to one of embodiments of the disclosure;

Fig. 8 is a schematic diagram for implementing an exemplary technology election the seat reservation charge according to one of embodiments of the disclosure;

Fig. 9 is a structural diagram illustrating the arm designer used to design the schema, layout and logic of the disclosed semiconductor integrated circuit.

DETAILED DESCRIPTION

Fig. 1 shows an exemplary system 100 for wireless communication, which may preferably be used a variant of implementation of the disclosure. For illustration purposes, Fig. 1 shows three remote node 120, 130, and 150 and two base stations 140. It should be noted that a typical wireless communication systems may have much more remote units and base stations. Remote nodes 120, 130, and 150 include devices 125A, 125B and 125C memory, created according to a variant implementation of the disclosure. Fig. 1 shows the signals 180 a direct line of communication with the base stations 140 to remote nodes 120, 130 and 150, and the signals 190 return line connection from remote nodes 120, 130 and 150 on the base station 140.

In Fig. 1 remote node 120 is shown as a mobile phone, the remote node 130 is shown as a portable computer, and the remote node 150 is shown as a remote node stationary installation of wireless subscriber loop. For example, remote sites can be cell phones, handheld devices, personal communications systems (PCS), portable digital devices such as personal digital secret and, or digital devices fixed installations, such as equipment readings of measuring devices. Although Fig. 1 illustrates the remote nodes according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. Disclosure may properly be used in any device that includes a memory device made in accordance with the doctrines of revelation.

Fig. 2A is a diagram, schematically illustrating a conventional pulse diagram of the bit lines for improved sustainability memory. The circuit 20 includes a bit cell 21, configured to store data and is connected to additional circuits to control the read and write circuit 20. Bit cell 21 can be testiclesstories the memory cell. The pre-charging signal, PCH, schema-bound 22 pre-charging. Scheme 22 pre-charging includes the transistor 221 connected to bit line BL, a transistor 222 connected to the inverted bit line BLB, and the transistor 223, connected to both bit lines BL and inverted bit line BLB. Pulse signal, PULSE, tied to the circuit 23 is reset. Scheme 23 reset includes the transistor 231 connected to bit line BL, a transistor 232 connected to the inverse discharge the line, BLB, and the transistor 233 connected to both bit lines BL and inverted bit line BLB.

For illustrative purposes hereinafter will be described the operation of traditional pulse circuit bit lines. Fig. 2B is a timing diagram illustrating the conventional pulse diagram of the bit lines for improved sustainability memory. Circuit 20 starts at the time 251 time when the pre-charging signal, PCH, is low, and the transistor 221 tightens bit line BL, the voltage VDDand the transistor 222 tightens inverted bit line BLB to the supply voltage, VDD. At the moment 252 time signal pre-charging, PCH, is turning off the excitation of the transistor 221, transistor 222 and transistor 223 to disconnect the bit line BL and inverted bit line BLB from the supply voltage VDD. At the moment 252 short time a positive pulse is generated in the pulse signal PULSE. Pulse signal, PULSE, includes a transistor 231 and the transistor 232 to attach the bit line BL and inverted bit line BLB, the potential 206 of the earth. Transistor 233 is turned off to disconnect the bit line BL from the inverted bit line BLB. The decrease in voltage occurs on the bit line BL and inverted bit line BLB. At the moment 253 time pulse signal, PULSE, returns to low, the state, so that bit line BL and inverted bit line BLB, stop the decrease of the voltage. Although this technology reduces the voltage of the bit line to improve the sustainability of reading, this technology is very sensitive to the formation of a short pulse, especially because the pulse width will change greatly depending on changes in process, voltage and temperature during production of transistors.

Next, with reference to Fig. 3, Fig. 4 and Fig. 5, will now be described improved technology selective pre-charging. The technology of selective pre-charging lowers the voltage of the bit line to improve the sustainability of reading, not being so sensitive to changes in process, voltage and temperature. The voltage of the bit line is reduced by the charge distribution between areas of the bit line which is selectively connected to enable distribution during operations read and write. Although will be described memory device SRAM (static memory device, random access), the technology of selective pre-charging can be applied to any design memory, including, but not as a limitation, SRAM, DRAM or MRAM.

Different parts of the bit is the second line pre-charged to different voltages (for example, VDDand GND) and using the distribution of charge is achieved to the desired final value of the voltage of the bit line. In one of the embodiments, the operation of the charge distribution is divided into three parts. First of all, as illustrated in Fig. 3, the upper part of the bit line is pre-charged to VDDalong with the fact that the lower part of the bit line is pre-charged to GND (ground potential). Then, as illustrated in Fig. 4, the key distribution charge off, to allow the charge distribution between the upper from the lower parts of the bit lines. Therefore, the final voltage of the bit line will be determined by the ratio of capacitances between CBLand C2. In conclusion, as illustrated in Fig. 5, the distribution of the charge off from work for all columns, along with the fact that the key is still enabled for the column that is selected for reading or writing.

Fig. 3 is a structural diagram illustrating the operation of the initial pre-charging in an exemplary technology selective pre-charging. Structural diagram 30 includes upper bit line 31 along with related associative capacity, illustrated by capacitor 311, with a value of CBL. The lower bit line 33 is associative associated capacity, Provillus the corresponding capacity 331, with a value of C2. The upper bit line 31 and the lower bit line 33 is attached to the key 32 multiplexing. In the structural diagram 30 key 32 multiplexing is open during the initial pre charge to provide the upper bit line 31 and the ability to pre-charged to voltage VDDand the bottom bit lines 33 to pre-charged to ground potential, GND. Additionally, the bit cell 34 is attached to the upper bit line 31. In yet another embodiment, the bit cell 34 can be attached to the lower bit line 33.

Fig. 4 is a structural diagram illustrating the operation of the charge distribution in the sample of election technology pre-charging. Structural diagram 40 includes upper bit line 31, the capacitance presented by the capacitor 311, the lower bit line 33, the capacitance presented by the capacitor 331 and the key 32 multiplexing. The operation of the charge distribution occurs through the circuit of the key 32 multiplexing to attach the upper bit line 31 to the lower bit line 33. The resulting voltage VBLon the combination of the upper bit line 31 and the lower bit line 33 is a function of the initial voltage on the upper bit line 31, the initial is atragene on the lower bit lines 33, capacitor 311 and capacitor 331, which is specified

where N is the number of pairs of bit lines connected to the key 32 multiplexing.

Fig. 5 is a structural diagram illustrating the switching off operation of the charge distribution in the sample of election technology pre-charging. Structural diagram 50 includes upper bit line 31, the capacitance presented by the capacitor 311, the lower bit line 33, the capacitance presented by the capacitor 331 and the key 32 multiplexing. The key 32 multiplexing is opened to disconnect the upper bit line 31 from the lower bit line 33 after completion of the charge distribution. This breaking off of the operation of the charge distribution, so the data can be read from or written into the bit cell 34. The key 52 multiplexing remains closed as bit cell 54 has been selected for reading or writing.

Fig. 6 is a structural diagram illustrating a pre-charging bit lines to different voltages in the approximate technologies electoral pre-charging according to another variant implementation of the disclosure. In this embodiment, not all of the upper bit lines are charged up to the supply voltage VDD. Structural diagram 60 on which includes the upper bit line 31, the capacitance presented by the capacitor 311, the lower bit line 33, the capacitance presented by the capacitor 331 and the key 32 multiplexing. The upper bit line 31 is pre-charged to a voltage VDDand the lower bit line 33 is pre-charged to ground potential, GND. In this embodiment, each of the upper bit line can be pre-charged to a different voltage. For example, the upper bit line 61 is pre-charged to ground potential, GND. Thus, when the charge distribution, the upper bit line and the inverse of the upper bit lines will have a lower terminal voltage, as compared with when all the upper bit line is pre-charged to voltage VDD. Additional bit line can be charged to ground potential, GND, power supply, VDDor other supply voltages (not shown) to obtain the proper final voltage.

Fig. 7 is a timing diagram illustrating the operation of the electoral pre-charging. The operation of the electoral pre-charging on the upper bit line BLUinverse of the upper bit lines BLBUlower bit line BLLand inverted bit lines BLBLthat is controlled by a signal before kiteley charging, PRECHG, signal multiplexing, MUX_STATE (multiplexing) and the signal charge distributions CH_SH. The numeric signal line, WL, gives access to the upper bit line BLUinverse of the upper bit lines BLBUlower bit line BLLand the inverse of the lower bit lines BLBL. The initial state of the circuit takes place at the moment 711 time when the pre-charging signal, PRECHG signal multiplexing, MUX_STATE, the signal charge distributions CH_SH, and the numeric signal lines WL are low. The lower bit line BLLand the inverse of the lower bit line BLBLpre-discharged to the ground potential, and the upper bit line BLUand the inverse of the upper bit line BLBUpre-charged to voltage VDD. The level of voltage is indicated in phantom line.

After pre-charging signal, PRECHG, who was in a high state (deactivation circuit pre-charging), the charge distribution is triggered when the signal multiplexing, MUX_STATE is low. As a result, at the moment 712 time, the signal charge distributions CH_SH, goes to a high state. The upper bit line BLUand the inverse of the upper bit line BLBUreduced voltage to potenziale land, GND in response to the charge distribution. Additionally, the lower bit line BLLand the inverse of the lower bit line BLBLincreasing the voltage to the supply voltage, VDD. The signal multiplexing, MUX_STATE, goes to a high state shortly before the moment 713 time, indicating completion of the operation of the charge distribution. As a result, the signal charge distributions CH_SH, is in a low state at the moment 713 time, the closing operation of the charge distribution. Voltage upper bit line BLUinverse of the upper bit lines BLBUlower bit line BLLand the inverse of the lower bit lines BLBLstabilizing at the moment 713 time when the operation of the charge distribution. The detensioning of the upper bit line BLUand the inverse of the upper bit lines BLBUincreases resistance reading memory.

At the moment 714-time numeric line, WL, goes to a high state, indicating that started the read operation. The voltage on the upper bit line BLUthe upper inverted bit lines BLBUlower bit line BLLand the lower inverted bit lines BLBL, is discharged to the ground potential, GND. At the moment 715 time after the read operation is completed, and the numerical line, WL, j who was in a low state, the pre-charging signal, PRECHG, is in a low state. As a result, the upper bit line BLUand the inverse of the upper bit line BLBU, charged to voltage VDDand the lower bit line BLLand the inverse of the lower bit line BLBLpre-discharged to the ground potential, GND. Shortly before the moment 716-time signal multiplexing, MUX_STATE, passed in the low state, returning all of the signals in their original state, at the moment 716 time.

Fig. 8 is a schematic diagram of the circuitry for implementing the exemplary technology selective pre-charging according to one of embodiments of the disclosure. The circuit 80 includes an upper bit line 85, BLUand the inverse of the upper bit line 87, BLBUconfigured to provide access to the bit cell 84. Additionally, the circuit 80 includes a bottom bit line 86, BLLand the inverse of the lower bit line 88, BLBL. Although the bit cell 84 is shown attached to the upper bit lines 85, 87, bit cell 84 can also be attached to the lower bit lines 86, 88. Scheme 81 permit the distribution of the charge, is configured to initiate the charge distribution, is tied to the signal multiplexing, MUX_STATE, and the signal will precede the school charging, PRECHRG, and outputs a signal charge distributions CH_SH. Scheme 81 permit the distribution charge includes inverter 812, tied to the signal multiplexing, MUX_STATE, and logical element 814 NAND attached to the output of the inverter 812 and the pre-charging signal, PRECHRG, and the inverter 816 connected to the output of logic element 814 NAND. Illustrated circuit 81 permit the distribution of charge is just one of the possible combinations of logic gates capable of activation of the charge distribution. Scheme 891 pre-charging is attached to the upper bit lines 85, 87 and emission scheme 892 attached to the lower bit lines 86, 88. Scheme 891 pre-charging and discharge circuit 892 can be controlled by pre-charging signal, PRECHRG.

The signal charge distributions CH_SH, and signal sampling, SELn, are entered in the logical element 82 NOR to control circuit 83 of the charge distribution. Scheme 83 distribution of charge is active when the signal charge distributions CH_SH, is in a high state. When the circuit 83 distribution of charge is active, the upper bit line 85 is attached to the lower bit line 86, and the upper bit line 87 is attached to the lower bit line 88. Signal sampling, SELn, used to fetch the bit cells for read or write. Although shown is only one signal sample, SELn, the upper bit line BLUinverse of the upper bit line BLBUlower bit line BLLand the inverse of the lower bit line BLBLmuch more than that can be included in the circuit 80. Additionally, a much larger number of bit cells may be included in the circuit 80.

The operation of the circuit 80 will be described hereinafter in connection with the time graph 70. At the moment 711-time signal pre-charging, PRECHG is low, and signal multiplexing, MUX_STATE is low. The output signal of the circuit 81 permit the distribution of charge, CH_SH will be low. The upper bit line 85, 87 pre-charged to voltage VDDand the bottom bit lines 86, 88 pre-charged to ground potential. At the moment 712 of time after the pre-charging signal, PRECHG, goes to the high state (deactivation of the circuit pre-charging), along with the fact that the signal multiplexing, MUX_STATE remains low, the output circuit 81 permit the distribution of charge, CH_SH, goes to a high state. It makes logical element 82 NOR control circuits 83 distribution charge for joining the upper bit lines 85, 87 to the lower bit lines 86, 88, lowering the voltage on the upper bit line BLUand inverted top the th bit line, BLBU. At the moment 713 of time after the signal multiplexing, MUX_STATE, goes to a high state, the output circuit 81 permit the distribution of charge, CH_SH, goes to a low state. This change makes the scheme 83 charge distributions disconnect the upper bit line 85, 87 of the lower bit lines 86, 88, to the charge distribution. At the moment 714-time bit cells 84 are access (in response to the signal lines records, WL), and the operation is read or write.

Technology charge distributions, as described in this disclosure, improves the stability of the read memory by reducing the voltage of the bit line from the supply voltage. The voltage of the bit line decreases pre-charging one portion of the bit line to the first voltage and the second section bit line to the second voltage. Diagram of the charge distribution is then selectively connects the two sections, in order to achieve voltage bit line between the first and second voltage. The final tension is partly dependent on the relative capacity of the two sites bit line, so any change to the production process in the devices does not affect the operation of the charge distribution. In one of the embodiments, the first section is the top of Otradnoe line, and the second plot is the lower bit line.

One of the advantages of this disclosure is an improved resistance reading by reducing the voltage of bit lines. The exact voltage level can be selected for the bit lines. As mentioned above, the decrease in voltage bit line improves static supply noise immunity (SNM) of the memory device. As exposed access bit cell and polybrene bit cell is improved, since all bit lines accept a lower voltage compared to the supply voltage of the discharge cell. Polybrene bit cells are cells selected approved numeric line, but not their selected bit lines.

The second advantage of this disclosure is the excellent reliability of the design. The disclosure does not depend on the threshold voltage of the transistor and the binding time of the decisive signal.

The third advantage of this disclosure is resistance to the change process. The proposed solution depends on the values of the relative capacity that does not change depending on changes in manufacturing process, voltage and temperature. The voltage of the bit line will depend on the process conditions.

The fourth advantage is that revealed the I is design flexibility. The voltage of bit line can be changed by selecting which portions of the bit lines should be pre-charged up to VDDand which areas of bit lines should be pre-charged to ground potential. For example, the pre-charging one bit line or more to ground potential can provide an opportunity for larger values of allowable error (shift bit line from VDD). For example, if the supply voltage has a value 1,125 volts, and the upper parts have value 1,125 volts, and the lower segments have a value 1,125 volts, the total voltage can be 1,125 volts, if all bit lines are pre-charged to VDD. Permissible error would be 0 mV in this case. However, in the same way, if one of the bit lines is pre-charged to the ground potential, the resulting voltage would be to 1.00 volts. Permissible error would be 125 mV in this case. Therefore, there is a high degree of flexibility regarding stress, which can be pre-charged areas of bit lines.

The fifth advantage of this disclosure is that there is only one supply voltage. This simplifies the high-level design at the physical level and a memory test.

The memory device, colorerase, can be attached to the microprocessor or other microelectronic device. The memory device may be placed in the housing with the microprocessor and, in the future, included in the communication device. For example, the memory may be embedded in a mobile phone or base station connection.

Fig. 9 is a structural diagram illustrating the arm designer used to design the schema, layout and logic of the disclosed semiconductor integrated circuit. Workstation (workstation) 900 designer includes a hard disk 901, which contains the software operating system, support files, and software CAD (computer aided design), such as Cadence or OrCAD. AWS 900 designer also includes a display to facilitate design of the circuitry 910. Schematic 910 may be circuit memory as described above. The storage medium 904 is provided for material storage circuitry 910. Schematic 910 may be stored on the storage medium 904 in a file format such as GDSII or GERBER. The storage medium 904 may be a CD-ROM on the CD-ROM), DVD (digital disc), hard disk, flash memory, or other appropriate device. Moreover, AWS 900 designer includes refraining from the STV 903 actuator for receiving the input data or the output data will be written to the storage medium 904.

The data recorded on the storage medium 904 can determine the configuration of the logical circuit, the template data for the photographic mask or template data mask tools for sequential write, such as electron-beam lithography. The data may further include data validation, such as flow charts or network diagrams, associative associated with logical simulations. Provision of data on the storage medium 904 facilitates the design of the circuitry 910, reducing the number of sequences of operations for designing semiconductor integrated circuits.

Although there have been described the present disclosure and its advantages, it should be clear that various changes, substitutions and alterations can be made in the materials of this application, without leaving the nature and scope of disclosure, which is defined by the attached claims. For example, although there have been described a memory device SRAM technology selective pre-charging can be applied to any design memory, including, but not as a limitation, SRAM, DRAM or MRAM. Furthermore, the scope of this application does not mean limited to a particular variants of the process, machine, manufacture, mixture of substances, including the government, methods and steps described in the description of the invention. As an ordinary specialist in the art can easily understand from the description of the present disclosure, processes, machines, manufacture, mixture of substances, means, methods, or steps, presently existing or due to be developed later, which perform essentially the same function or achieve essentially the same result as the corresponding embodiments of described in materials of this application can be used according to the present disclosure. Accordingly, the appended claims refers to include within their scope such processes, machines, manufacture, mixture of materials, means, methods or steps.

1. A memory device containing:
the first bit line having a first section and a second section; and
the distribution of charge is selectively attachable to the first area and the second area in which the scheme of distribution of charge is configured to attach and detach the first section from the second section.

2. The memory device according to claim 1, in which the first section of the first bit line is pre-charged to a first voltage, and the second section of the first bit line is pre-charged to a second voltage, different from the lane is wow voltage.

3. The memory device according to claim 2, in which the first section of the first bit line is pre-discharged to a voltage of the ground, and the second section of the first bit line is pre-charged to the supply voltage.

4. The memory device according to claim 2, additionally containing a second bit line having a first section and a second section in which the first section of the second bit line and the second section of the second bit line is pre-charged to the first voltage.

5. The memory device according to claim 1, additionally containing schema permissions charge distribution, is configured to initiate a scheme of allocation of charge when the circuit pre-charging is inactive, and the signal multiplexing indicates the distribution of the charge.

6. The memory device according to claim 1, additionally containing bit cell connected to the first section of the first bit line.

7. The memory device according to claim 1, additionally containing inverted bit line having a first section and a second section in which the pattern of charge is selectively attached to the first section of the inverted bit line and the second section of the inverted bit line and configured to attach and detach the first section inverted bit line from the second segment of the inverted bit line.

p> 8. The memory device according to claim 1, where the device memory connected to the microprocessor.

9. The memory device of claim 8, the memory device and the microprocessor integrated in the communication device.

10. The method of controlling the memory device having a bit line comprising a first section and a second section, consisting in the fact that:
pre-charge the first section bit line to the first voltage;
pre-charge the second section bit line to the second voltage, the second voltage different from the first voltage; and
distribute the charge between the first section bit line and the second section bit line to obtain the final voltage between the first voltage and the second voltage.

11. The method according to claim 10, in which the final voltage is determined, at least partially, of a capacity of the first section bit line and the capacitance of the second section bit line.

12. The method according to claim 10, in which pre-charging of the first area is that pre-charge the first section bit line to the supply voltage and the pre-charging the second plot is that pre-charge the second section bit line to a voltage of the earth.

13. The method according to claim 10, further comprising that:
pre-C is rahut the first section of the second bit line and the second section of the second bit line to the first voltage.

14. The method according to claim 10, in which the charge distribution is according to the status signal multiplexing, when the circuit pre-charging is inactive.

15. The method according to claim 10, further comprising that:
retain in the memory device data related to the connection.

16. A memory device containing:
means for pre-charging the first section bit line to the first voltage;
means for pre-charging the second section bit line to the second voltage; and
means for distributing charge between the first section bit line and the second section bit line.

17. The memory device according to clause 16, in which the first voltage is a supply voltage.

18. The memory device according to clause 16, in which the second voltage is a voltage of the earth.

19. The memory device according to clause 16, the memory device included in the cell phone.

20. The method of controlling the memory device having a bit line comprising a first section and a second section containing phases in which:
pre-charge the first section bit line to the first voltage;
pre-charge the second section bit line to a second voltage that is different from the first voltage; and
distribute the charge between the first section bit if the AI and the second section bit line for receiving a voltage level between the first voltage and the second voltage.

21. The method according to p, optionally containing phase in which the pre-charge the first section of the second bit line to the first voltage and the second section of the second bit line to the first voltage.

22. The method according to p, optionally containing phase in which the pre-charge the first section of inverted bit line and the second segment is inverted bit line and distribute the charge between the first plot of the inverse bit line and a second plot of the inverse bit line.

23. The method according to item 16, further comprising that:
retain in the memory device data received through the communication line.

24. Constructive memory structure, the material embodied on a machine-readable medium containing:
the first bit line having a first section and a second section; and
the distribution of charge is selectively attachable to the first area and the second area in which the scheme of distribution of charge is configured to attach and detach the first section from the second section.

25. The constructive structure of the memory according to paragraph 24, optionally containing a microprocessor, connected to the first bit line and the apportionment of the charge.



 

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SUBSTANCE: device for determining logical state of selected memory cells in memory device with passive matrix addressing is made with possible connection to ferroelectric memory device or forming its portion and contains reading amplifying contours, synchronous amplifier, combined source of shift voltage and signal, active control line driver, multiplexer, a set of routers. Other variant of aforementioned device is additionally equipped with second set of routers. Method describes operation of aforementioned devices.

EFFECT: higher efficiency, broader functional capabilities.

3 cl, 12 dwg

The invention relates to a method of recording, the control method and device for recording

FIELD: data carriers.

SUBSTANCE: device for determining logical state of selected memory cells in memory device with passive matrix addressing is made with possible connection to ferroelectric memory device or forming its portion and contains reading amplifying contours, synchronous amplifier, combined source of shift voltage and signal, active control line driver, multiplexer, a set of routers. Other variant of aforementioned device is additionally equipped with second set of routers. Method describes operation of aforementioned devices.

EFFECT: higher efficiency, broader functional capabilities.

3 cl, 12 dwg

FIELD: information technology.

SUBSTANCE: complete scanning memory matrix includes several local bit lines and a global bit line. The method of launching the global bit line involves a step for connecting several local bit lines with the global bit line through several tristate devices, generation of a global selection signal for allowing operation of one of the several tristate devices and selection of the corresponding local it line for launching output of the tristate device allowed to operate. That way, the global bit line is statically launched so that serial bit reading having the same value read on the global bit line does not lead to switching of the state of the global bit line.

EFFECT: reduced power when reading the said matrix.

13 cl, 9 dwg

FIELD: information technologies.

SUBSTANCE: device to delete recorded information comprises the following: a DC source, a switching element, an AC to DC voltage converter, an external supply slot, a de-energising device, a flash sensor, an AC voltage device, a switch, a voltage divider, two devices of energy accumulation, a control device arranged as a microprocessor, a contactor, an indication device, a shaper - limiter, a four-wire cable and a joined four-contact connector.

EFFECT: improved reliability and quality of information deletion without the possibility of its recovery, reduced power consumption, reduced dimensions and weight of the device.

2 cl, 7 dwg

FIELD: information technology.

SUBSTANCE: method of managing a memory device, having a bit line comprising a first section and a second section, involving precharging the first section of the bit line to a first voltage; precharging the second section of the bit line to a second voltage different from the first voltage; and distributing charge between the first section of the bit line and the second section of the bit line to obtain a final voltage between the first voltage and the second voltage.

EFFECT: high read stability owing lower voltage of the bit line.

25 cl, 10 dwg

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