Method to metallise elements in products of electronic engineering

FIELD: electricity.

SUBSTANCE: method to metallise elements in products of electronic engineering includes application of a sublayer of a metallising coating on one of substrate surfaces with previously formed topology of elements in an appropriate product, and this sublayer is a system of metals with the specified thickness, providing for adhesion of the main layer of the metallising coating, formation of topology - protective photoresistive mask of the main layer of metallising coating, local application of the main layer of the metallising coating, removal of protective mask, removal of a part of the sublayer arranged outside the topology of the main layer of the metallising coating. Application of the sublayer of the metallising coating is carried out with the total thickness of 0.1-0.5 mcm, directly onto the specified sublayer additionally a technological layer is applied from an easily oxidable metal with thickness of 0.1-0.5 mcm, and formation of the metallising coating topology is carried out on the technological layer from the easily oxidable metal. Prior to local application of the main layer of the metallising coating a part of the technological layer is removed from the easily oxidable metal via the specified protective mask, and removal of the remaining part of the technological layer from the easily oxidable metal is carried out prior to removal of a part of the sublayer of the metallising coating arranged outside the topology of the main layer of the metallising coating.

EFFECT: increased quality of the metallising coating and reliability of electronic engineering products, improved electrical characteristics, increased yield of good products.

6 cl, 3 dwg, 1 tbl

 

The invention relates to electronic devices and can be used for production of discrete semiconductor devices and integrated circuits, including a monolithic semiconductor integrated circuits microwave.

When the design and manufacture of discrete semiconductor devices and integrated circuits (hereinafter referred to electronic equipment) electrical and heat conducting properties of metallization coating elements of the product along with other technological and structural parameters determine the electrical characteristics of electronic devices.

There is a method of metallization elements of electronic devices, called method of "explosion", which consists in forming on the substrate surface with the topology of the elements of the product topology metallization coating by the method of photolithography, deposition of metallization coating metal or metals, the removal of the protective photoresistive mask in an appropriate solvent [1, 2].

When the "explosion" is the presence of gaps in the metallization coating applied directly to the surface of the substrate with the product topology and the surface protective photoresistive mask, due to the different thickness of their layers, low - metallization coating and big enough protection photoresistive the second mask.

Otherwise, the "explosion" is not implemented.

The disadvantages of this method are:

first, the low quality of the metallization coating and, accordingly, the low reliability of electronic devices,

secondly, in the low reproducibility of the method of "explosion" and, accordingly, the low percentage of yield of electronic devices,

thirdly, limiting metallization coating thickness, not more than 2 μm, and thus the low quality of the metallization coating and, accordingly, the low reliability of electronic devices,

fourth, is that true at all times - a significant loss of precious metal, usually gold in the process of "Bang", since the latter is one of the widely used materials for metallization of electronic devices.

There is a method of metallization elements of electronic devices, in order to increase the adhesion of the metallization coating on the surface of the substrate with the topology of the product in addition put - sprayed sublayer of system metals chromium-platinum-gold, followed by the application of the base layer metallization coating electrolytic method - metal layer with good electrical and heat conducting properties, usually of gold, with increased thickness over the entire pack is mentioned surface of the substrate, with the subsequent formation of a given topology metallization coating by the method of photolithography, removing the etching of the metallization coating through the protective photoresistive mask, removing the protective photoresistive mask in an appropriate solvent [3].

There is a method of metallization elements of electronic devices, including, as in the previous method, sputtering on the surface of the substrate with the topology of the elements of the product substrate metallization coating in the form of metals, the formation of a given topology metallization coating by the method of photolithography, deposition of the base layer metallization coating electrolytic method - metal layer with good electrical and heat conducting properties, with increased thickness. But unlike the previous application of the base layer metallization coating is carried out locally, removing the protective photoresistive mask in an appropriate solvent, and removing the etching part of the metal sublayer located outside the topology of metallization coating [4 - prototype].

This method, like the previous one, compared to the first analog provide:

first, by applying the above-mentioned metallization sublayer coating high adhesion of the base layer metal is sure of the cover, as a consequence, improving the quality of metallization coating and, accordingly, the reliability of electronic devices,

secondly, by using the electrolytic method of application of the base layer metallization coating and, accordingly, this method of removing the limitation on the thickness of the base layer metallization coating and, consequently, improving the quality of metallization coating and, accordingly, the reliability of electronic devices.

The drawback of these methods is:

first, in violation of - change of the geometrical dimensions of the metallization coating due to lateral protravlivanija and, as a consequence, the deterioration of the electric characteristics of the electronic devices;

and that along with the above advantages due to the use of the electrolytic method of application of the base layer metallization coating, which, for example acidic, heating to a temperature of 60-70°C (in the case of positive photoresist), imposes the most stringent requirements for protective photoresistive mask and which (as mentioned mode) leads to an increase in density of defects in the protective photoresistive mask, due to the initially processes the method of photolithography, such as:

- through holes, creating the analy conductivity, the so-called "false" schema elements,

- the Ghost zone surrounding free from protective photoresistive mask area on the surface of the substrate, which are formed as a result of protravlivanija protective photoresistive mask in the contact zone, and could lead in the long electrolytic process for the deposition of the respective deposited metal and thereby to the above violation of the geometric dimensions of the metallization coating and, consequently, deterioration of the electric characteristics of electronic devices.

Secondly, low adhesion photoresistive mask to the metal of the above-mentioned metallization sublayer coating, the result is:

- the violation of the geometric dimensions of the metallization coating because of its protravlivanija and, consequently, reduce its quality and, consequently, reduce the reliability and the deterioration of the electric characteristics of electronic devices,

- increased the percentage of defects and, consequently, low product yield.

Thirdly, in considerable loss of gold by etching. In the third analogue of the more significant losses of gold than in the fourth prototype.

The technical result of the invention is to improve the quality of metallization coating and, accordingly, improving the reliability of products ELEH the throne equipment, the improvement of the electric characteristics, the increase in output.

The specified technical result is achieved by the claimed method metallization elements of electronics products, including drawing on one surface of the substrate with the active layer with the pre-formed to the surface topology of the elements of the respective product sub-layer metallization coating in the form of metals with a given thickness, providing adhesion of the base layer metallization coating, the formation of topology - protective photoresistive mask base layer metallization coating by the method of photolithography, deposition locally base layer metallization coating electrolytic method - metal with good electrical and heat conducting properties, with increased thickness, removing the protective photoresistive mask, removing part of the substrate metallization coating located outside the topology of the base layer metallization coating.

Where:

the underlayer coating metallization coating in the form of metals carried out with a total thickness of 0.1-0.5 µm,

- directly on the underlayer metallization coating is additionally applied technology layer of the easily oxidizable metal thickness of 0.1-0.5 µm,

- and the formation of the topology of the metalized coating is carried out on the technology layer of the easily oxidizable metal,

- and before applying locally the base layer metallization coating electrolytic method carry out the removal of parts of the process layer of the easily oxidizable metal through the mentioned protective photoresistive mask,

and removing the remaining parts of the process layer of the easily oxidizable metal is carried out before removing part of the substrate metallization coating located outside the topology of the base layer metallization coating.

The electronics product may be a discrete semiconductor device, for example a field effect transistor with a barrier of a Schottky with beamed conclusions, after forming the metallization beamed conclusions carry out the removal of the substrate from its back side in the locations of the beam conclusions through a photolithography method.

The electronics product may be integrated circuit with air bridges, for example, semiconductor, or plastic, or a hybrid, thus before applying the metallization sublayer coating additionally form the topology of air bridges by means of the photolithography method.

The metallization sublayer coating applied in the form of the metal is in, for example, the titanium-gold or chrome-Nickel, with a layer of gold is removed in two stages: in the first method, ion-beam etching, the second chemical etching, when the ratio of the removed thickness of the gold 2/3, respectively.

As legkookisljajushchihsja metal process layer using group metals, for example, aluminum, chromium, titanium.

Remove the remaining parts of the process layer of the easily oxidizable metal and part of the metallization sublayer coating located outside the topology of metallization coating, carried out by the known methods such as chemical or plasma-chemical etching or a combination thereof.

Disclosure of the invention.

The claimed method of metallization elements of electronic devices - discrete semiconductor devices and integrated circuits provides all its essential features, namely:

The underlayer coating metallization coating in the form of metals with a total thickness of 0.1-0.5 micron, as determined experimentally, is the optimal thickness, which provides high adhesion of the base layer metallization coating and, consequently, improving the quality of metallization coating and, accordingly, improving the reliability of electronic devices, the improvement of electrical characteristics.

<> The technological layer of easily oxidizable metal of the specified thickness and thus and thus surely the presence - the presence on the surface of the easily oxidizable metal to its corresponding oxide.

This allows you to use the technological layer of easily oxidizable metal as an additional protective masks in combination with protective photoresistive mask during electrolytic deposition of the base layer metallization coating and thus:

first, it eliminates the lateral leakage of the latter and thereby eliminates the breach is changing the geometric dimensions of the metalized coating and, as a consequence, the improvement of the electric characteristics of electronic devices,

second, it allows to minimize the likelihood of "false" schema elements and, consequently, improving the reproducibility and, accordingly, the yield and improving the electrical characteristics of electronic devices,

thirdly, it provides an exception is the "poisoning" of the electrolyte products of the destruction of the protective photoresistive mask in his aggressive environment (acidic medium, the temperature of 60-70°C) and, consequently, improving the quality of metallization coating and, accordingly, improving the reliability of electronic devices, invites the electrical characteristics.

Moreover, legkookisljajushchiesja metal process layer performs at the same time, importantly, two functions:

first - as mentioned above (its near-surface oxide) as an additional protective mask protective photoresistive mask during electrolytic deposition of the base layer metallization coating

second - as a conductor connecting the local areas of metallization sublayer coating.

This second addition to the first eliminates lateral leakage metallization sublayer coating and thereby to avoid the violation of - change of the geometric dimensions of the metalized coating and, as a consequence, the improvement of the electric characteristics of electronic devices.

The underlayer coating metallization coating in the form of metals total thickness, as well as the application of technological layer of easily oxidizable metal thickness less than 0.1 μm, it is unacceptable, and more than 0.5 μm is impractical.

In the first case due to the possibility of violation of their integrity and thus inability to perform their main function, and the second does not lead to further improvement of the quality of metallization coating, but creates additional difficulties (problems) when they are removed.

Thus, the claimed method of plating products e the Tronic equipment fully specified technical result namely improving the quality of metallization coating and, accordingly, increased reliability, improved electrical characteristics, increase of yield.

The invention is illustrated by drawings.

Figure 1 Dan cut fragment field-effect transistor with the barrier Schottky (VTS) with beamed conclusions (a special case of implementing the inventive method of metallization of electronic devices), where:

- the surface of the substrate with the active layer - 1,

the topology of the elements of the product - 2,

the metallization sublayer coating - 3,

- topology - protective photoresistive mask base layer metallization coating - 4,

- main layer of metallization coating - 5,

technology layer of the easily oxidizable metal - 6,

- beamed conclusions 7.

Figure 2 (a and b) given the cut fragment topology monolithic semiconductor integrated circuit microwave and film integrated circuits made on a sapphire substrate, respectively (special cases implementing the inventive method of metallization of electronic devices), where:

air bridges - 8.

Figure 3 gives the picture above fragment field-effect transistor with a barrier of a Schottky beamed with the conclusions obtained by raster electron microscope, type Leo 1525.

Examples of specific performance is considered on the examples of implementation the AI instantiations of the claimed method of metallization of electronic devices, namely samples:

field effect transistor with a barrier of a Schottky with beamed findings (examples 1-5),

monolithic semiconductor integrated circuit microwave (examples 7-11),

- film integrated circuits made on a sapphire substrate (examples 13-17).

Example 1.

On the front surface politology substrate of gallium arsenide active layer of n-type conductivity of 1 thickness of 0.3 μm and a dopant concentration of 3×1017cm3the generated topology elements 2 with two alternating pairs of electrodes of the source, drain, channel between them with the groove for the gate electrode in the form of a barrier of a Schottky.

The method includes the following sequence of technological operations metallization elements VTS - beamed findings provided the technological process of manufacture with the use of the claimed method of metallization:

is applied to the surface of the aforementioned substrate 1 with pre-formed therein topologies elements 2 with the metallization sublayer coating 3 in the form of a system of the metals titanium-gold with a total thickness of 0.3 (0.05 and 0.25 μm, respectively) by sputtering in vacuum installation URMS;

- directly on the above-mentioned metallization sublayer coating 3 applied technology layer of the easily oxidizable metal 6, for example, titanium, thick, equal to the 0.3 microns by evaporation in vacuum on the installation URMS;

- form on the technological layer of easily oxidizable metal - titanium 6 topology - protective photoresistive mask 4 of the base layer metallization coating by the method of photolithography using positive photoresist, for example SPR220(7);

- remove part of the process layer of the easily oxidizable metal titanium 6 formed through the protective photoresistive mask 4, for example, by plasma-chemical etching using installation NE860R in the following mode: power - 140 W, the time is 10 minutes, the composition of the gas quality (sulfur hexafluoride (SF6), oxygen (O2), helium (Not)) and quantitative volume, including(60, 2, 5)×10-6respectively;

- applied locally base layer metallization coating 5 - metal with good electrical and heat conducting properties, such as gold, with increased thickness of, for example, equal to 6 μm by an electrolytic method formed through the protective photoresistive mask 4 in the following mode: the electrolyte phosphate-based dicyanoaurate potassium, temperature - 30°C, the current density is 1 mA/cm2time - 2 hours 30 min;

- remove the protective photoresistive mask 4, for example, by exposure and subsequent manifestation in MF-24A;

- remove the remaining portion of the process layer made easy the oxidizable metal - titanium 6, for example, by plasma-chemical etching using installation NE860R under above mentioned conditions;

- remove part of these sublayer 3, located outside the topology of the base layer metallization coating 5, with a layer of gold is removed in two stages, namely:

at first remove the layer of gold with a thickness of 0.18 μm by ion beam etching using setup ion etching, ARMS,

second remove the remaining part of the layer of gold with a thickness of 0.07 μm by chemical etching in the following mode: provide the Etchant composition of qualitative (10% solution of sodium thiosulfate, 10% solution of thiourea, 10% solution of red blood salt) and quantitative volume, including (1:1:1), respectively,

then remove the layer of titanium plasma-chemical etching using installation NE860R in the following mode: power - 140 W, the etching time is 3 min, the composition of the gas quality (sulfur hexafluoride (SF6), oxygen (O2), helium (Not)) and quantitative volume, including(60, 2, 5)×10-6(m3respectively;

- carry out the removal of the above-mentioned substrate 1 with its back side in the locations of the beam 8 conclusions using the method of photolithography and subsequent etching.

Examples 2-5.

Analogously to example 1 was manufactured with, but when other process parameters of the proposed method metallization, MC is connected in the formula of the invention (examples 2-3), and beyond (examples 4-5), and according to the prototype method (example 6).

Examples 7-11.

Similar to examples 1-5 manufactured samples of the monolithic semiconductor integrated circuit microwave, the technological parameters of the method of metallization specified in the formula of the invention (examples 7-9), outside (examples 10-11) and according to the method prototype (example 12).

When you do this:

- monolithic semiconductor integrated circuit microwave also performed on the front surface politology substrate of gallium arsenide active layer of n-type conductivity 1, a thickness of 0.3 μm and a dopant concentration of 3×1017cm3and contains the following elements, at least one VTS 2, at least two of the capacitor 2 from different sides VTS, air bridges 8;

- before applying the metallization sublayer coating 3 is additionally formed on said surface of the substrate 1 with the pre-formed on the topology of the elements 2 a monolithic semiconductor integrated circuit microwave topology of air bridges 8 by the method of photolithography;

- metallitotuus the following elements of the monolithic semiconductor integrated circuit microwave upper plates of capacitors 2, pads 2, air bridges 8.

Examples 13-17.

Similar to examples 1-5 is made samples planon the second integrated circuit, made on a sapphire substrate, when the technological parameters of the method of metallization specified in the formula of the invention (examples 13-15), outside (examples 16-17) and according to the method prototype (example 18).

This metallizer the following elements of film integrated circuits - upper plates of capacitors 2, pads 2, the transmission line 2, the inductive elements 2, air bridges 8.

On prepared samples field-effect transistor with a barrier of a Schottky monolithic semiconductor integrated circuit of the microwave hybrid integrated circuit amplifier microwave carried out on samples of the above film integrated circuits on a sapphire substrate:

- the measured output power microwave (wattmeter AM-66),

- defined reliability according to GOST RV 20.57416-98,

- defined output.

The data are summarized in table.

As the table shows, the samples of field-effect transistor with a barrier of a Schottky monolithic semiconductor integrated circuit of the microwave hybrid integrated circuit amplifier microwave carried out on samples of film integrated circuits on a sapphire substrate, in which the metallization coating provided the technological process of manufacture made according to the claimed method of metallization (examples 1-3), (examples 7-9), (examples 13-15), respectively, we have:

- high o is dnow power of approximately 2,0, 0.5 and 0.85 W, respectively, at the operating frequency of 10 GHz,

a gain of approximately 10,0, 16,0 15,0 dB, respectively,

- high reliability, mean time to failure 107hour

the yield is about 60, 40 and 60 percent, respectively.

Similar results have indicated the samples of electronic devices, but when the metallization sublayer coating applied in the form of system metals chromium-Nickel, and a technology layer in the form of chromium or aluminum. Data not shown in the table due to its bulkiness.

In contrast to samples of field-effect transistor with the barrier Schottky (examples 4-5), monolithic semiconductor integrated circuit microwave (examples 10-11) and a hybrid integrated circuit amplifier microwave carried out on samples of film integrated circuits on a sapphire substrate (examples 16-17), in which the above-mentioned metallization coating is made with process parameters outside the limits indicated in the claims, and according to the prototype method (example 6, 12, 18), which are:

- output power(1,8-1,7), (0,45-0,4), (0,8-0,75) W, respectively, at the operating frequency of 10 GHz,

- low reliability, mean time to failure 5×106hour

- yield of less than 40 percent.

Thus, the proposed method metallization elements of electronic devices allowed is compared with prototype:

- significantly improve the quality of metallization coating and, accordingly, the reliability of electronic devices is approximately 2-5 times,

to improve electrical characteristics,

to increase the yield by about 10-20 percent.

Sources of information

1. Martin Caulton. Subctrates, Materials and processes for microwave applications. "29th Electronic Components Conference, 1979, p. 126-131.

2. Fomin A.V., Bochenkov SCI, Sorokopud, VA Technology, reliability, production automation BGIS and microassemblies. Under. Ed. Avifauna. M.: Radio and communication, 1981, p.114.

3. Higaka N., Takeuchi Y. and Shima T. Miniaturzed GaAs FET Amplifier Fujitsu Sci. Teeh. J., 1980, v.16, n 2, p.77-94.

4. Pelicans J.V., Moscow J.V. Semiconductor devices with three-dimensional conclusions. Reviews on electronics. Ser. "Semiconductor devices", 1974, Q. 8 (220), p.1.

1. The way metallization elements of electronics products, including drawing on one surface of the substrate with the active layer, with pre-formed to the surface topology of the elements of the respective product, substrate metallization coating in the form of metals with a given thickness, providing adhesion of the base layer metallization coating, the formation of topology - protective photoresistive mask base layer metallization coating by the method of photolithography applying locally the base layer metallization coating electrolytic method metal with good electrical and teploprovodnymi properties, with increased thickness, removing the protective photoresistive mask, removing part of the substrate metallization coating located outside the topology of the base layer metallization coating, characterized in that the underlayer coating metallization coating in the form of metals carried out with a total thickness of 0.1-0.5 microns directly on the underlayer metallization coating is additionally applied technology layer of the easily oxidizable metal thickness of 0.1-0.5 µm, but forming a topology metallization coating is carried out on the technology layer of the easily oxidizable metal, and before applying locally the base layer metallization coating electrolytic method perform a delete part of the process layer of the easily oxidizable metal through the mentioned protective photoresistive mask, and removing the remaining portion of the process layer of the easily oxidizable metal is carried out before removing part of the substrate metallization coating located outside the topology of the base layer metallization coating.

2. Method of metallization of items of electronic equipment according to claim 1, characterized in that the said product may be a discrete semiconductor device, the example field-effect transistor with a barrier of a Schottky with beamed conclusions after the formation of the beam conclusions carry out the removal of the substrate from its back side in the locations of the beam conclusions through a photolithography method.

3. Method of metallization of items of electronic equipment according to claim 1, characterized in that the said product may be integrated circuit with air bridges, for example, semiconductor, or plastic, or a hybrid, thus before applying the metallization sublayer coating additionally form the topology of air bridges by means of the photolithography method.

4. Method of metallization of items of electronic equipment according to claim 1, characterized in that the metallization sublayer coating applied in the form of metals, for example titanium-gold or chrome-Nickel, with a layer of gold is removed in two stages: first by ion beam etching, the second chemical etching, when the ratio of the removed thickness of the above-mentioned underlayer 2/3, respectively.

5. Method of metallization of items of electronic equipment according to claim 1, characterized in that as legkookisljajushchihsja metal process layer using group metals, for example, aluminum, chromium, titanium.

6. Method of metallization of items of electronic equipment according to claim 1, characterized in that the removal of the remaining portion of the process layer and is of the easily oxidizable metal and part sub-layer metallization coating, located outside the topology of metallization coating, carried out by the known methods such as chemical or plasma-chemical etching or a combination thereof.



 

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12 cl, 17 dwg

FIELD: ink jet printers.

SUBSTANCE: method includes precipitating resistive layer and conductive layer on insulated substrate, forming a resistive heating element, forming of insulating barrier layer above contour of said conductive layer, forming of gap in said barrier layer, forming of metallic layer being in electrical contact with said conductive layer contour through said gap, having geometry, which opens predetermined portion of said contour of conductive layer, making a layout from metallic layer from said contour of conductive layer through said gap in insulating barrier layer to adjacent portion of said insulated substrate, so that layout from metallic layer on said adjacent portion of said insulating substrate forms a relatively large and flat area, remote from said conductive layer contour, for forming displaced spring contact. After precipitation of resistive layer and conductive layer on insulating substrate, contour of conductive layer is formed first, having a recess, forming later said resistive heating element, and then contour of resistive layer is formed with overlapping of conductive layer contour for value, exceeding precision of combination during lithography process and error of dimensions during etching of resistive layer.

EFFECT: higher quality, higher reliability, higher efficiency.

2 cl, 10 dwg

FIELD: ink-jet printers and their printheads having small holes for programmable ejection of ink droplets.

SUBSTANCE: proposed method for producing printhead thin-film interconnection structure includes deposition of resistor layer and conductor layer onto insulated substrate, formation of patterns of layers deposited onto insulated structure to form resistive heating element, formation of insulating barrier layer onto pattern of mentioned conductor layer, formation of window in mentioned barrier layer, production of metal layer contacting mentioned conductor layer pattern through mentioned window whose geometry opens up predetermined area of mentioned conductor layer pattern, and metal layer pads on insulating barrier layer above heating layer; prior to arrangement of conductors from metal layer, insulating barrier layer is treated with etching solution for cleaning and recovering surface insulating barrier layer, and along with wiring of metal layer from mentioned conductor layer pattern through mentioned window in insulating barrier layer on adjacent area of mentioned insulated substrate metal layer wiring section is made in the form of pad on insulating barrier layer above heating element used as stabilizing evaporation surface. In this way insulating barrier layer is cleaned and its properties are recovered, metal layer wiring adhesion to insulating barrier layer, and especially adhesion of metal layer pad to insulating barrier layer above heating element, is enhanced.

EFFECT: enhanced quality and reliability of printhead.

3 cl, 11 dwg

FIELD: producing copper tracks on insulating substrates.

SUBSTANCE: negative image of track is projected onto copper halide solution layer in organic solvent of substrate with the result that concentric capillary flow occurs in layer which transfers solution to illuminated sections of substrate wherein copper halide tracks remain upon solvent evaporation. These tracks are reduced to copper ones in hydrogen current at temperature sufficient to conduct reducing reaction.

EFFECT: facilitated procedure, reduced cost and copper consumption, improved environmental friendliness due to elimination of wastes.

1 cl, 3 dwg

FIELD: microelectronics; complementary metal-oxide-semiconductor transistors.

SUBSTANCE: proposed method for producing CMOS transistor gate regions includes formation of regions of second polarity of conductivity, insulator, and gate silicon dioxide in substrate of first polarity of conductivity, deposition of polycrystalline silicon layer, its doping, formation of gate regions of p- and n-channel transistors, thermal cleaning in trichloroethylene and oxygen, deposition of separating silicon dioxide, modification, formation of drain and source regions of both polarities of conductivity, thermal cleaning in trichloroethylene and oxygen, deposition of pyrolytic insulating silicon dioxide, its modification by thermal firing in trichloroethylene and oxygen, opening of contact windows, metal deposition, and process operations (removal of natural silicon dioxide, formation of gate silicon dioxide, formation of polycrystalline silicon layer) conducted within single vacuum cycle of one reactor, whereupon polycrystalline silicon layer is doped.

EFFECT: improved and regulated electrophysical properties of gate silicon dioxide enabling enhancement of threshold voltage reproducibility and yield.

4 cl, 3 dwg

FIELD: ohmic contacts for microelectronic devices such as microwave field-effect transistors.

SUBSTANCE: proposed method includes production of vacuum in vacuum chamber, sequential electron-beam evaporation of Ti, Al, Ni, and Au in vacuum chamber onto section of AlGaN layer surface, and high-temperature annealing; prior to Ti, Al, Ni, Au evaporation Ti is sprayed in vacuum chamber to form 2-3 Ti monolayer on surfaces of elements disposed within vacuum chamber; Ti, Al, Ni, Au are evaporated onto section of AlGaN layer surface at vacuum of 1 x 10-7 to 1 x 10-8 mm Hg.

EFFECT: reduced contact resistance of ohmic contacts due to reduced amount of residual oxygen and water vapors in vacuum chamber.

1 cl

FIELD: ohmic contacts for microelectronic devices such as microwave field-effect transistors.

SUBSTANCE: proposed method includes sequential evaporation of Ti, Al, Ni, Au onto section of AlGsN surface layer and fast thermal annealing of semiconductor heterostructure; fast thermal annealing is conducted using contact method and graphite resistive heater, semiconductor heterostructure being disposed on heater surface. In the course of annealing temperature of GaN/AlGsN semiconductor heterostructure is controlled to ensure reproducibility of its parameters.

EFFECT: facilitated procedure, reduced time requirement, enhanced quality of heterostructure.

1 cl

FIELD: light devices production.

SUBSTANCE: method of quantum wells mixing within semiconductor device implies: a) formation of layer structure with quantum wells including doped upper layer; b) formation of etch preventing layer over mentioned upper layer; c) formation of temporary layer over mentioned etch preventing layer, and mentioned etch preventing layer has significantly lower etch rate than mentioned temporary layer on condition that etching requirements are preliminary specified; d) process of quantum wells mixing upon device structure making significant violation of at least a part of consumed layer; e) removal of temporary layer from at least device contact area by etching selective relative to etch preventing layer to uncover mentioned etch preventing layer within contact area; and f) formation of contact over layer structure with quantum wells directly on the surfaced uncovered after execution of stage e) at least within mentioned contact area.

EFFECT: improvement of device contact resistance.

15 cl, 10 dwg

FIELD: electronics.

SUBSTANCE: invention pertains to electronics, particularly to microelectronics, and can be used when making silicon semiconductor devices. The method of making a system for metal plating silicon semiconductor devices involves forming a dielectric film based on silicon dioxide on a silicon substrate with active regions, formation in this film of contact windows to active elements of the substrate, deposition of a film of molten aluminium with a given thickness, formation of the metal pattern and subsequent thermal treatment for obtaining ohmic contacts. Thermal treatment is carried out in a hydrogen atmosphere with addition of 0.5-3.0 vol.% water or 0.25-1.5 vol.% oxygen.

EFFECT: higher quality of the system of metal plating due to reduced defectiveness and improved electrical characteristics.

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