System and method of reducing power consumption of dynamic ram by using valid data indicators

FIELD: information technology.

SUBSTANCE: method of refreshing a dynamic random-access memory (DRAM) array in form of independently refreshable memory units, comprising: associating an indicator with each independently refreshable memory unit; upon writing data to an independently refreshable memory unit, setting the associated indicator to reflect valid data; increasing delay between refreshing operations in proportion to the zero number of suppressed refreshing cycles, wherein a refreshing cycle is suppressed if the associated indicator reflects invalid data, so that only all independently refreshable memory units, which contain valid data, can be refreshed with maximum period of refreshing; and refreshing with said maximum period of refreshing only the independently refreshable memory units whose associated indicator reflects valid data stored therein.

EFFECT: reducing DRAM power consumption.

26 cl, 6 dwg

 

The technical field

The present invention relates to the field of storage devices, in particular to a system and method to reduce power consumption of the dynamic RAM.

Prior art

Solid-state dynamic RAM (DRAM) is a cost-effective solution to the memory of large capacity for many modern computing systems, including portable electronic devices. DRAM, including synchronous dynamic RAM (SDRAM), provides a high density of bits and a relatively low cost per bit compared with the structures comes fast memory, such as registers, static RAM (SRAM) and the like, as well as a significantly higher speed access than the electro-, magneto - or optical-mechanical memory blocks of a large volume such as a hard disk, ROM, CD-ROM (CD-ROM) and the like.

Figure 1 depicts a logical representation of a typical 512 - Bitovoi matrix 100 DRAM. The matrix 100 is organized as a set of separately addressable banks 102, 104, 106, 108. Each Bank is divided into a large number, for example, 4096, row 110. Each line section 110 into multiple columns (e.g., 512 columns), and each column contains a number of data bits, as a rule, organized as bytes (for example, 8 bytes). Various rhythm is s addressing data known in the art. For example, when addressing the Bank, row, column (BRC), the memory address may be interpreted as a

31-2625-2423-1211-32-0
Choice
crystal
Choice
Bank
The row selectionThe column selectionSelect byte

In an alternative addressing scheme, such as addressing a row, Bank, column (RBC), memory addresses can be interpreted as a

31-2625-1413-1211-32-0
Choice
crystal
Choice
line
The choice of the BankThe column selectionSelect byte

Matrix of DRAM are volatile; data stored in the matrix DRAM must be refreshed periodically to maintain its integrity. During the refresh operation of DRAM, a large number of storage cells of the data is odnovremenno read from the matrix 100 and re-loaded. Traditionally, matrix, DRAM refreshed line by line. That is, the line - or, in some implementations, the same string at the same time in each Bank is selected, and all the data in the row is updated in a single operation. Used herein, the term "independently refreshable memory unit or IRMU, refers to the quantum of data that are updated within one refresh operation. IRMU for the matrix DRAM, as a rule, is a string, although the present invention is not limited to the refresh operation line by line.

Update operations aimed at IRMU, usually interspersed with memory accesses, and timed so that the entire matrix DRAM is refreshed before any data will be lost due to the reduction of the charge. Traditionally, update URLs - that is, the address of each independently refreshable memory unit is supplied by a memory controller such as a processor that determines a refresh operation using a unique combination of control signals. Modern SDRAM components may include two additional update mode: self-update and automatic updates. In both modes, the component SDRAM includes the internal address counter update. Self-renewal is used in many systems, such as electronic devices with batteries that use "n is active" mode for energy saving. In the mode of self-renewal SDRAM component is not available for storage and retrieval of data, however, the SDRAM performs refresh operations internally to ensure the integrity of the stored data. In the automatic mode, the memory controller determines the update operation, but does not provide address updates. Instead, the SDRAM provides increment the internal address counter update, which provides a consistent independently of the updated addresses of memory blocks (for example, strings).

Each refresh operation consumes energy when data is read from the matrix DRAM and recharged. However, especially after power-up or system reset, the majority of cells storage memory in the matrix DRAM does not contain valid data.

The invention

In accordance with one or more variants of implementation of the disclosed and claimed here, is supported by a pointer that indicates or no upgradeable memory segment valid data. When the update operation is aimed at its associated memory, the refresh operation is inhibited if the memory does not contain valid data. A significant saving of power supply can be realized by suppressing update operations aimed at invalid the s data.

One variant of implementation relates to a method for updating a dynamic memory. The pointer associated with each independently refreshable memory unit. After the data has been independently refreshable memory unit associated pointer is set to reflect the actual data. Only the independently refreshable memory blocks whose associated index reflects the actual data stored in it are updated.

One variant of implementation refers to a component of a DRAM. Component DRAM includes a matrix DRAM, valid for data storage and organized as a set of independently refreshable memory units. Component DRAM also includes a set of pointers, each of which is associated with the independently refreshable memory unit and indicates whether valid data is stored in the independently refreshable memory block. Component DRAM also includes a controller, receiving the control signals and operable for verifying pointers and update only the independently refreshable memory units that store the actual data.

Brief description of drawings

Figure 1 shows the functional block diagram of the organization of the data in the matrix DRAM.

Figure 2 is a functional block diagram of the organization of the data in the matrix DRAM with a pointer or bit is ejstitelnosti, associated with each independently refreshable memory unit.

Figure 3 is a functional block diagram of the SDRAM component.

Figure 4 is a functional block diagram of a single-processor computing system.

Figure 5 is a functional block diagram of a multiprocessor computing system.

6 is a block diagram of a method of updating the matrix DRAM.

Detailed description

Figure 2 depicts a logical view of the organization of the matrix DRAM 200 in accordance with one embodiment. Matrix 200 is logically organized as four banks 202, 204, 206, 208, and each Bank contains 4096 rows. The characteristic line is depicted as 210. In this embodiment, the line 210 is the smallest independently refreshable memory unit. String 210 in the matrix 200 is associated pointer 211, reflecting the fact whether the row contains 210 valid data. In the shown embodiment, each pointer 211 contains one bit, and also referred to herein as the validity bit associated with each line. Figure 2 depicts the sets of bits 212, 214, 216, 218 of pointers, where each bit is a pointer associated with the banks 202, 204, 206, 208, respectively. In one embodiment, where the smallest independently refreshable memory unit contains a string that spans all four banks 202, 204, 26, 208 need only one set of bits-pointers 212.

During the refresh operation checks the indicator or the validity bit, for example, the pointer 211 associated with the current addressable independently refreshable memory unit, for example, IRMU 210. If the bit is set, the indicator indicating that the associated IRMU contains valid data, the update operation is performed on IRMU to save the data. If the bit-indicator is not set, indicating that the associated IRMU does not contain valid data, in one embodiment, the refresh operation is inhibited, thus saving power, which otherwise would be consumed if the update IRMU. Thus, only IRMU, which contain the actual data that will be updated, and IRMU in the matrix, which are uninitialized or in an indifferent condition, not updated. Address updates can be provided by the memory controller, or may be generated internal address counter, for example, when auto-refresh or self-renewal.

Bits-indicators can be supported in different ways. In one embodiment, bits-indicators are stored in a fixed or programmable part of the matrix 200 memory. In this case, the useful size of the matrix 200 is reduced by 0.003 per cent. Another is the version of the implementation bits-indicators are stored in the component DRAM/SDRAM memory other than the matrix DRAM 200, for example, in the structure of the static random access memory, registers, etc. In one embodiment, the memory indicator fact IRMU is available through 2-cyclic sequence, such sequences access the mode register and extended mode register of the SDRAM components.

Figure 3 represents a functional block diagram of the SDRAM component 300 in accordance with one embodiment. SDRAM 300 includes a matrix DRAM 301, organized as four banks 302, 304, 306, 308. Each Bank contains decoders 312, 310 rows and columns. The amplifier 314 read outputs the data read from the matrix DRAM 301 buffers 316 I / o. The recorded data from the buffers 316 I / o pass through the input buffer 318 and stored in the register 320 data recording before recording in the matrix DRAM 301.

The component SDRAM 300 is controlled by the state machine 322. Addresses of the banks and the memory is entered into the address buffer 324 and stored in the address register 326, where they control circuit 328 pre-decoder and column counter. The register 330 mode and register 332 advanced mode save bits mode selection, such as the delay of the strobe column address (CAS), length of service, etc. that control the operation of the counter 334 packet and circuit 336 control data output.

Scheme logic 338 pack and timer taking the em address IRMU from internal counter 340 and the bits of reality IRMU from memory 342 really IRMU. The update logic outputs addresses IRMU on pre-decoder 344 rows. Note that, although the memory 342 really IRMU is shown in figure 3 as a functional unit that is separate from the matrix DRAM 301, memory, physically allocated for storing pointers fact, IRMU, may be part of the matrix DRAM 301, or may be a separate DRAM, SRAM, registers, or other memory.

In one embodiment, the SDRAM component 300 automatically monitors the addresses of record and sets the pointer actually IRMU respectively IRMU, which directed each write operation. Logic 338 update then checks the memory 342 really IRMU after each update operation, and suppresses the refresh cycles aimed at any IRMU, which does not contain valid data. This minimizes the power consumption of the SDRAM component 300, but does not require any knowledge about the update-suppression or participation of the memory controller or processor. The main savings can occur after power-up or reset, when the matrix DRAM 301 for the most part not filled with valid data. As the memory controller writes the data into more IRMU in the matrix DRAM 301, is set more bits actually IRMU, and less suppressed refresh cycles. In this embodiment, the memory 342 IRMU automating the Eski cleared as part of the initialization of the SDRAM component 300 after power-up or reset. This implementation allows system designers to benefit from the low power SDRAM component 300 when using existing memory controllers and software that do not include complex memory management functions.

In one embodiment, the memory 342 IRMU can be cleared by command from the memory controller, such as a predefined write operation of the register 330 mode or register 332 advanced mode or combination of bits. This implementation allows to reduce power consumption of the component SDRAM 300 after software-initiated reset, but requires that the memory controller has issued a command for clearing the memory 342 IRMU.

Figure 4 depicts a computing system 400 that controls and reduces the power consumption of the DRAM. The system 400 includes a memory controller, such as processor 402, hardware 404 of the memory controller (which may be integrated with processor 402 and a memory device such as SDRAM component 406. Matrix DRAM SDRAM component 406 is logically divided into independently refreshable memory blocks a, 408b, 408c, ... 408j. Every IRMU associated pointer fact, IRMU, such as bit a, 410b, 410c, ... 410j, which indicates whether the associated IRMU valid data.

Many tasks 412, 414 software about the level executing on the processor 402. Each task software can allocate memory for data storage and can reclaim memory that is no longer required. Administrator 416 memory software is a software module that manages memory for the processor 402. Administrator 416 memory software accepts requests to allocate and/or deallocate memory from task 412, 414 of the software. In response, the administrator 416 memory software allocates memory for and on task 412, 414, displays the distributed memory one or more independently updateable blocks a, 408b, 408c, ... 408j memory (e.g., string) and sets and resets the appropriate signs a, 410b, 410c, ... 410j actually IRMU to reflect the status of the data in the current time in IRMU 408f, 408b, 408c, ... 408j. In one embodiment, the current controller memory is an independent element 404 hardware, in another embodiment, the functionality of the memory controller integrated into the processor 402. Component SDRAM 406 suppresses all update operations are aimed at IRMU a, 408b, 408c, ... 408j that contain invalid data.

Figure 5 shows a multiprocessor system that manages memory allocation and minimizes the power consumption of the SDRAM. The processors 502, 504 carry out the communication with each other and with the hardware 508 of the memory controller via the system bus 506. Bus 506 may also be implemented as a switching system, Crosspoint switch, etc. as known in the art. One or more tasks 503, 516, 518 of the software running on the processors 502, 504. System administrator 520 memory software executes on a single processor 504, allocating memory to and from all program tasks 503, 516, 518, running on the system. Any software task 503 executing on a processor 502 may send requests allocation and deallocation of memory to the administrator 520 memory software bus 506. As described above, the administrator 520 memory software allocates memory to and from the task 503, 516, 518, displays the distributed memory on one or more independently updatable units 512a, 512b, s, ... 512j memory, and sets and resets the appropriate signs 514a, 514b, 514c, ... 514j actually IRMU through hardware means 508 of the memory controller to reflect the state of the data stored in the current time in IRMU 512a, 512b, s, ... 512j. Component SDRAM 510 suppresses update operations aimed at IRMU 512a, 512b, s, ... 512j that contain invalid data.

In a normal refresh mode, the automatic mode or the mode of self-renewal, SDRAM component 300, 406, 510 compares the address update (provided by the controller is Amati or internal counter) memory 342, 410, 514 reality IRMU and suppresses update operations aimed at IRMU 408, 512, which do not contain valid data. In one embodiment, in which the administrator 416, 520 memory software actively manages memory and sets/clears bits 410, 514 reality IRMU, the system can further optimize the refresh memory and to minimize power consumption by dynamically suppressing update commands IRMU, when the physical memory is freed of distribution for software tasks and returned to the "pool", in this case, the contents data is not relevant.

In normal mode, update the administrator 416, 520 memory software can provide the update addresses only IRMU 408, 512, containing valid data. In the automatic mode or the mode of self-renewal component of the SDRAM 300, 406, 510 may ignore invalid memory by incrementing its address counter update until the next IRMU 408, 512 contains valid data after each update operation. In any case, the controller 404, the memory 508 may increase the delay between updates, so only IRMU 408, 512, which contain the actual data, all updated with a maximum update period. In this embodiment, the implementation is of no update commands are not suppressed component of the SDRAM 300, 406, 510. This further optimizes the energy consumption and reduces the bus is overloaded), avoiding unnecessary instruction cycles, memory, and latency, which update command impose on the current memory access.

6 depicts a method 600 updates DRAM in accordance with one or more variants of implementation. When you initialize all pointers IRMU are cleared (block 602). The method then checks whether the update operation (block 604). In a traditional refresh mode, the refresh operation is specified by the control signals sent to the component of DRAM memory controller, and IRMU to be updated is specified on the address bus. In auto-refresh mode, the refresh operation is prescribed by the commands of the memory controller, and the internal counter provides the address update IRMU. In the mode of self-renewal expiration of the refresh timer specifies that the update operation, and the internal counter provides the address IRMU.

If you specify the update operation (block 604), the pointer IRMU associated with the current address IRMU (such as, for example, string address)is checked (block 606). If the pointer IRMU indicates that IRMU contains valid data (block 608), then the update operation is performed on the addressed IRMU (block 610). If the pointer IRMU indicates that IRMU not who holds valid data (block 608), the update operation is suppressed, saving energy that would otherwise be spent on upgrading invalid (or "indifferent") data.

In the mode of self-renewal SDRAM component waits in block 604 following the expiration of the address counter update. In other modes, the update if the update operation is not required commands (block 604), DRAM (or SDRAM) component performs the operations of reading, writing, and/or access to the register, as specified by the commands of the memory controller (block 612). In one embodiment, in which the software module memory management allocates and frees memory access operation to the memory or the register may include operations directed to the memory IRMU - reading, setting and clearing pointers IRMU. In one embodiment, the pointer IRMU is automatically set after a write operation directed to the associated IRMU (block 614). In this embodiment, the pointers IRMU only reset upon initialization (block 602), but can provide significant savings in power up until valid data will not be written at least once to many IRMU.

By applying software paradigms for managing memory where memory is relevant only when it is distributed to the task, and involves "beratli the Noah" state prior to the distribution or after release - physical operations update matrix DRAM, a significant saving of power supply can be realized by eliminating unnecessary refresh operations directed to the memory segments that do not have valid data. In one embodiment, the implementation of tracking the actual data by setting the associated IRMU bits automatically. In this embodiment, the energy-saving advantages of the present invention is available in systems without software memory management or knowledge about the possibility of selective suppression of update operations. In other embodiments, a direct memory management IRMU enables the use of complex memory management and obtain maximum savings outlets.

Used herein, the term "independently refreshable memory unit or IRMU refers to the segment of (quantum) information, which is updated within the same refresh operation. IRMU for the matrix DRAM, as a rule, is a string, although the present invention is not limited to this. Used herein, the term "set" refers to the record data in the pointer IRMU to indicate that valid data is stored in the associated IRMU, regardless of the value of data (for example, 0 or 1, or a multi-bit combination). "Clean" refers to the record data in the pointer IRMU to yasat is, that valid data is not stored in the associated IRMU, regardless of the value of data (for example, 0 or 1, or a multi-bit combination). Used herein, the term "matrix DRAM" refers to the matrix memory dynamic random access stores data in the integrated schema components as DRAM and SDRAM. As used herein, the term "DRAM or DRAM component" are included as components of an asynchronous DRAM, and SDRAM components. Used herein, the term "distribute" refers to assigning a memory address range for programming tasks, and the term "release" means the return previously distributed memory addresses in the pool of Unallocated memory.

Although the present invention has been described herein in connection with certain features, aspects and options for implementation, it should be apparent that numerous variations, modifications and other embodiments of possible in the broad scope of the present invention and, accordingly, all variations, modifications and alternatives of implementation shall be considered as included in the scope of the invention. Therefore, the options presented implementation should be considered in all aspects as illustrative and not restrictive, and all changes falling within the range of values and equivalence app is part of the claims, are assumed to be covered by them.

1. How to update matrix dynamic random access memory (DRAM)organized as a set of independently refreshable memory units containing:
associating an index with each of the independently refreshable memory unit;
when writing data to independently refreshable memory unit, installing the associated pointer to reflect the actual data; increase delay between updates, in proportion to the nonzero number of suppressed refresh cycles, and the update cycle is suppressed, if the associated index contains invalid data, so that only all independently refreshable memory blocks that contain valid data could be updated with a maximum update period; and updating with the mentioned maximum update period only independently refreshable memory units whose associated index reflects the actual data stored in them.

2. The method according to claim 1, in which the independently refreshable memory unit is a string.

3. The method according to claim 1, in which the independently refreshable memory unit contains a string across two or more memory banks.

4. The method according to claim 1, wherein the pointer is a bit of reality.

5. The method according to claim 4, in which the validity bit of sohranena matrix DRAM.

6. The method according to claim 4, in which the validity bit stored in static memory.

7. The method according to claim 4, in which the validity bit stored in the register.

8. The method according to claim 1, wherein installing the associated pointer to reflect the actual data includes the installation of a pointer on a command from the memory controller.

9. The method according to claim 1, in which the pointers are set to reflect the actual data is cleared at reset.

10. The method according to claim 1, in which the pointers are set to reflect the actual data is cleared by command from the memory controller.

11. The method according to claim 1, wherein updating only the independently refreshable memory units whose associated index reflects the actual data stored in them, contains self-renewal only independently refreshable memory units whose associated index reflects the actual data stored in them.

12. The method according to claim 1, wherein updating only the independently refreshable memory units whose associated index reflects the actual data stored in them, contains auto update only the independently refreshable memory units whose associated index reflects the actual data stored in them.

13. The method according to claim 1, in which the update is only illegal the performance of the updated memory blocks, have an associated index contains the actual data stored in them, contains a sequential update nonadjacent independently refreshable memory units.

14. The method according to claim 1, wherein updating only the independently refreshable memory units whose associated index reflects the actual data stored in them, contains:
receiving the update command;
check pointer associated with the current address update; and if the index contains the actual data, update the addressable independently refreshable memory unit.

15. The method according to item 13, further comprising, if the index contains the actual data, the execution of the increment of the address update before the next independently refreshable memory unit having a pointer that reflect actual data.

16. Dynamic RAM (DRAM)containing the matrix DRAM, operable to store data, and the matrix DRAM organized as a set of independently refreshable memory units, and a component of the DRAM further comprises:
a set of pointers, each of which is associated with the independently refreshable memory block to specify the stored valid data in the independently refreshable memory block;
each associated pointer is made with the possibility the completion of the installation when writing data to independently refreshable memory unit, thus, to reflect the actual data stored in the block; and
the controller is configured to increase the delay between updates, in proportion to the nonzero number of suppressed refresh cycles, and the update cycle is suppressed, if the associated index contains invalid data, so that only all independently refreshable memory blocks that contain valid data could be updated with a maximum update period;
moreover, the controller is additionally configured to check pointers and upgrade with these maximum refresh period only independently refreshable memory units associated pointers which represent actual data stored in the block.

17. A component of the DRAM according to clause 16, further containing a counter update, acting for generating addresses independently refreshable memory blocks in the matrix DRAM.

18. A component of the DRAM according to clause 16, which additionally contains the memory management, acting for the pointer, when data is written into the associated independently refreshable memory unit.

19. A component of the DRAM according to clause 16, in which the pointers are cleared during initialization.

20. A component of the DRAM according to clause 16, in which the controller additionally operates for installation and the cleaning and pointers in response to the control signals.

21. Component DRAM clause 16, in which the pointers are stored in one or more independently refreshable memory.

22. Machine-readable medium including at least computer program control memory, operable to perform steps of the method according to any one of claims 1 to 15.

23. Machine-readable medium according to article 22, in which a computer program memory management additionally acts for performing the following steps:
receive requests from a software task to free memory that was previously distributed this task;
free memory that was previously distributed to the task; and
if all memory in the independently refreshable memory block released, clearing the associated index to indicate a storage device to suppress an update operation
aimed at this independently refreshable memory unit.

24. Machine-readable medium according to article 22, in which a computer program memory management allocates memory for a variety of software tasks running on a single processor.

25. Machine-readable medium according to article 22, in which a computer program memory management allocates memory for two or more software tasks, each of which is executed on another processor.

26. Machine-readable medium according to article 22, in which a computer program memory management the mouth of allivet index independently refreshable memory unit after the initial write data to associate independently refreshable memory unit.



 

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14 cl, 24 dwg

FIELD: information technology.

SUBSTANCE: method of refreshing a dynamic random-access memory (DRAM) array in form of independently refreshable memory units, comprising: associating an indicator with each independently refreshable memory unit; upon writing data to an independently refreshable memory unit, setting the associated indicator to reflect valid data; increasing delay between refreshing operations in proportion to the zero number of suppressed refreshing cycles, wherein a refreshing cycle is suppressed if the associated indicator reflects invalid data, so that only all independently refreshable memory units, which contain valid data, can be refreshed with maximum period of refreshing; and refreshing with said maximum period of refreshing only the independently refreshable memory units whose associated indicator reflects valid data stored therein.

EFFECT: reducing DRAM power consumption.

26 cl, 6 dwg

FIELD: information technology.

SUBSTANCE: method for regeneration and failure protection of dynamic memory, involving serial reading of data, detecting errors in the data contained in memory, modifying the data by correcting the detected errors at each memory address and reading with a period of time which is not greater than the memory regeneration time, wherein the modified data are recorded at the same memory address with a lower priority, and during the recording latency period, access to the same memory address is listened and stability errors are then analysed.

EFFECT: faster operation and failure safety of the system.

4 cl, 2 dwg

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