Virtually tagged instruction cache with physically tagged behaviour

FIELD: information technology.

SUBSTANCE: system contains a virtually tagged instruction cache; a means for address translation which responds to an address translation invalidate instruction; and a control logic circuit configured to invalidate not all entries in the virtually tagged instruction cache in response to the address translation invalidate instruction.

EFFECT: providing useful power, frequency and carrying capacity of instructions when using a virtually tagged instruction cache.

20 cl, 5 dwg

Related applications

This application claims the priority of provisional application U.S. No. 60/793016 filed April 19, 2006, and provisional application U.S. No. 60/793015 filed April 19, 2006, which is fully incorporated herein by reference.

The technical field

The present disclosure of the invention in General relates to processing systems, and more specifically, to systems virtual bulleted cache commands.

Prior (equipment)

Common processor systems use the concept of broadcast addresses in the processor pipeline to change the page address data or commands with addresses in virtual memory at their current address in physical memory. One way broadcast address uses the buffer quickly convert addresses (TLB), which usually saves a lot of records, where each record includes an identifier space applications (ASID), also called a process ID (PID), tag (TAG) virtual address (VT) and the number of the physical page (PPN). Thus, the buffer is a quick conversion of the address contains the correspondence between virtual address and physical address. In its simplest form, the processor pipeline takes as input virtual address command, compares the virtual address with entries in TB, to find a suitable entry, and replaces a portion of a virtual address number of the physical page associated with the appropriate record to form the physical address. Given the transformation of the physical addresses in a virtual address, as a rule, covers the range of virtual and physical address space, and this range is called a "page" page size, typically larger size of the cache line in the instruction cache, so cache lines can be associated with the same page in a virtual or physical address space.

Conventional processor systems also include one or more caches commands that store the most recently used command comes in fast memory, to minimize delay resulting from sampling teams from slower memory outside of the crystal. The instruction cache can be indexed for efficient search records. The term "indexed", which is used relatively caches commands, means many bits either virtual address or physical address, which are used to specify sets in the instruction cache with multiple Association or line in the instruction cache direct mapping. Instruction cache, indexed by bits in the virtual address, known as a virtual indexia the p cache. Instruction cache, indexed by bits in the physical address, known as a physically indexed cache.

Entries in the instruction cache can be marked with tags using the key, which is compared with either part of a physical address, or part of a virtual address. Instruction cache, labeled as tag part of a physical address, known as an instruction cache, physically labeled with tags. Instruction cache, labeled as tag part of a virtual address, known as an instruction cache, a virtual labeled with tags. Developer processor selects, as the instruction cache is indexed and labeled. Traditional caches commands can be either virtual indexed and virtual labeled (VIVT), virtual indexed and physically marked (VIPT), or physically indexed and physically marked (PIPT). Through the address translation of the virtual address is converted to a physical address, which can be used to search for records in a physically marked instruction cache or to access physical memory in the event of a cache miss commands.

In addition to the label (tag) virtual address virtual bulleted caches teams usually include a label ASID or PID. This tag allows the processor system to distinguish between a valid address record for Akti is nogo software process. For example, if processor system executes the commands associated with the software process with ASID "x", then a successful match, the cache would match as a label ASID and tag virtual address command. Due to various scenarios, such as swapping active ASID, i.e. replacement of one process with the specified value ASID, new process, using the same value of ASID, marked virtual caches teams may have one or more entries that are obsolete and no longer valid. Since the cache-hit protect the processor from fetching from memory, developers processor systems want the cache coherency, that is, the cache whose contents reflect the actual, obsolete commands. To maintain the coherency of the cache entries in the cache are usually made invalid in response to commands on the invalidity cache commands issued by the software application. The amount of cache control commands required software application depends on whether the cache commands marked virtual or physically marked. Because one or more virtual addresses can be displayed on the specified physical address, in a traditional virtual bulleted instruction cache can cause problems aliases and synonyms.

The problem of aliases fuss is AET, when two or more records I-cache, containing different combinations of virtual addresses / ASID, correspond to the same physical address. These different combinations can be caused by any of the following three reasons. First, the virtual address two or more entries of the I-cache can literally be different, but to be part of the same software process with the same field value ASID. Secondly, the virtual addresses of the two or more entries of the I-cache can be the same, but associated with different software processes and, thus, associated with different values of the field ASID. Thirdly, the virtual addresses of the two or more entries of the I-cache can vary and be associated with different software processes, thus, be associated with different values of ASID. In any of these cases, different combinations may correspond to the same physical address. As a result of this problem aliases traditional virtual bulleted caches commands shift the burden on the software application to issue commands on the invalidity of the I-cache for more scenarios than you have to physically marked the instruction cache. For example, a software application written for virtual bulleted cache commands would be required to issue commands on negatvie is a major cache commands to perform the invalidity of each virtual address in the instruction cache, which can be associated with a physical address, which itself was invalid or changed.

The problem of synonyms refers to two or more entries of the I-cache, which are located in different virtual indexes I-cache, but which are associated with the same physical address. The problem of synonyms can occur in traditional virtual indexed I-caches regardless of whether I-caches virtual or physically marked.

Virtual bulleted caches teams also put any additional load on the software in order to invalidate the entries of the I-cache, compared to physically marked caches commands. In particular, when according to the combination of the specified ASID and pages of virtual address space changes from one physical address to another, all the entries of the I-cache in the virtual bulleted I-cache that is associated with that combination of ASID and pages of virtual address space are not valid, because the I-cache can cache the contents of the old addresses of physical memory associated with the old line, not the contents of the new physical memory addresses associated with the new line. This is true even if the actual contents of the base of old and new is the dres physical memory could not be changed. Therefore, software written to manage the virtual bulleted instruction cache, must perform actions to invalidate the instruction cache to invalidate all cache entries command, which could be associated with a combination of ASID and pages of virtual address space for which changed the match.

In the processor with the virtual bulleted instruction cache address translation can be performed in the pipeline in parallel with the search commands in the virtual bulleted instruction cache. Thus, this parallelism provides the best power, frequency and bandwidth commands when using virtual bulleted caches commands. Therefore, there is a need for a system and methods for cache commands that provide the benefits of traditional virtual bulleted cache command along with elimination of the additional load imposed traditional virtual labeled caches commands to the software application, in relation to records management, and does not impose additional requirements on the software application.

The invention

One aspect of the disclosure the invention discloses a system cache commands that have advantages as a virtual bullet to the instruction cache, and physically mA is Kirovenergo cache commands. This aspect of the present invention uses a virtual bulleted instruction cache, which from the perspective of a computer program acts as physically marked instruction cache.

Another aspect of the disclosure the invention discloses that the virtual addresses or parts thereof are used as labels in the means of address translation, and virtual bulleted instruction cache. With this understanding of the team on the invalidity directed to the means of address translation, may optionally be used to invalidate the entry in the virtual bulleted instruction cache.

In another aspect the disclosure of the invention the system cache command includes a virtual bulleted instruction cache, the tool for the network address translation scheme and logic. Means for address translation is responsible for the team on the invalidity of broadcast addresses. The control logic circuit is configured to invalidate entries in the virtual bulleted instruction cache in response to a command for invalid broadcast address.

In yet another aspect of the disclosed method of virtual work bulleted cache commands as if he was physically marked by the instruction cache from the point of view of the computer program. The method includes receiving the command invalidation broadcast hell is representing for the invalidation of entries in the virtual bulleted instruction cache in response to a command for invalid broadcast address.

In an additional aspect, the disclosed scheme logic for managing virtual bulleted instruction cache so that he acted as if he was physically marked by the instruction cache. The control logic circuit includes a first input for receiving commands for invalid broadcast address and the means for generating control signals to invalidate an entry in the virtual bulleted instruction cache in response to a command for invalid broadcast address.

Of course, other embodiments of the present invention will become apparent to experts in the art from the subsequent detailed description, in which various embodiments of the invention shown and described to illustrate. As will be recognized, the invention permits and other great ways to exercise, and some details of the permit modification in various other respects, all without deviating from the present invention. Accordingly, the drawings and the detailed description should be regarded as explanatory in nature and not as restrictive.

Brief description of drawings

Figure 1 - functional block diagram of one possible implementation of the processor.

Figure 2 is a more detailed image of the system cache commands from figure 1.

Figure 3 - block the Hema, illustrating selective invalidate many records virtual labeled I-cache, which could be associated with a physical address in the I-cache direct mapping.

4 is a block diagram illustrating selective invalidate many records virtual labeled I-cache, which can be associated with a physical address in the two-input I-cache with multiple access.

5 is a block diagram of a sequence of operations illustrating a method for virtual bullet to the instruction cache to act as if he was physically marked by the instruction cache from the point of view of the computer program.

Detailed description

Set forth below is a detailed description with reference to the accompanying drawings is intended as a description of various embodiments of the present invention and is not intended to represent the only embodiments of which the present invention can be implemented in practice. Such description includes specific details to ensure a comprehensive understanding of the present invention. However, specialists in the art it will be obvious that the present invention can be implemented without these specific details. In some cases the well-known structures and components are shown in the form of a flowchart, to avoid tangling ideas of the present invention.

Figure 1 depicts the functional diagram of the processor 100. The processor 100 executes the commands in the pipeline 120 for execution of commands according to the diagram of the control logic 110. The processor 100 may be any type of component pipelined processor, including, as an example, a microprocessor, a digital signal processor (DSP), programmable logic diagram of the discrete gates or transistor logic, or any other component of information processing. In some embodiments, the implementation of the conveyor 120 may be a superscalar design with multiple parallel pipelines. The conveyor 120 includes various registers or latches 160A-D, arranged in cascade conveyor, and one or more modules 180 execution. Although figure 1 shows five stages of the pipeline, specialists in the art will recognize that the stages of the pipeline, larger or smaller than illustrated stages of the pipeline may be included in processor 100. File 130 of the General purpose register (GPR) provides registers that make up the top of the memory hierarchy. The processor 100 includes a system 127 the instruction cache, which includes virtual bulleted cache 122 instructions (I-cache), a buffer of 128 quick conversion address (TLB) and the circuit 110 of the control.

The conveyor 120 selects commands from the I-cache 122 p is the filing of a virtual address in the I-cache 122. The address translation memory is controlled using the TLB 128. Concurrently with the filing of a virtual address I-cache 122 conveyor 120 outputs to the TLB 128 virtual address command to determine the corresponding physical address, which can be used for access to a storage device 150 through the interface 140 of the storage device, if the virtual address is not found in the I-cache 122 (a cache miss). Diagram of control logic 110 receives commands on the invalidity of the conveyor 120 and manages the provision of invalidity of one or more entries in the I-cache TLB 122 and 128. The structure and operation of the system 127 cache commands more fully described with reference to the description of figure 2.

Data accessed from the cache 126 data (D-cache) using the address translation memory and permissions managed by the buffer 128 to quickly convert addresses (TLB). Although figure 1 depicts the TLB 128 as an integral TLB, in various embodiments, the implementation of the TLB 128 can be divided into multiple TLB, where one dedicated to broadcast appeals to the D-cache 126, and the other dedicated for broadcast requests in the I-cache 122. The misses in the I-cache 122 and/or D-cache 126 serve as a reason to main memory 150 (outside the crystal) under the control interface 140 of the storage device. Such reference to the main memory using the physical address retrieved from the TLB 128.

The processor 100 may include SEB is the interface 134 input/output (I/O), managing access to various peripheral devices 136 and 138. Specialists in the art will recognize that many possible variations of the processor 100. For example, processor 100 may include a second level cache (L2) for any one or two together of the I-cache 122 and D-cache 126. Moreover, one or more functional blocks depicted in the processor 100 may be omitted from a particular variant implementation.

Figure 2 is a more detailed image system 127 the instruction cache of Fig 1. In this typical embodiment, TLB 128 is configured with three columns 210A-210C. Column 210A contains the IDs of space applications (ASID)associated with software processes. The register 215 contains the ASID of the executable currently a software process that can be stored in a dedicated register or file 130 GPR. Column B contains the virtual TLB tag. Virtual TLB tag is part of a virtual address. For example, a virtual address 205 is a 32-bit address stored in the register, such as register program counter (PC). In this example, the positions of the bits 31-12 determine the portion of the virtual address that specifies a virtual TLB tag.

Column C contains a 20-bit number physical page (PPN), corresponding to the combination of ASID / virtual TLB tag. The number of the physical pages in suraweera of the TLB 128, when active ASID (associated with execution of the software process) and virtual TLB tag of the virtual address 205 correspond to the combination (combination) label ASID and virtual TLB tag stored in the string TLB 128. Returned PPN concatenated with the page offset to determine the corresponding physical address. In particular, during the concatenation returned PPN is placed in position bits 31-12, whereas the offset part of the page in the virtual address continues to occupy positions of bits 11-0.

In this typical embodiment, the virtual labeled I-cache 122 is a 32-KB cache direct display with 1024 "set of 1-line, 32-byte lines. In this embodiment, the virtual labeled I-cache 122 is configured with four columns 220A-220D. Column 220A contains the IDs of space applications (ASID)associated with software processes. Column 220 contains a virtual tag I-cache (I$). Column 220C contains a 32-byte line commands associated with a specific combination of virtual labels I-cache and ASID. Optional column 220D contains flags that indicate under what conditions associated record has been stored in the I-cache to limit the amount of subsequent jobs of invalid records.

Virtual address 205 is depicted showing the state of two superimposed values for bit positions. When the virtual address 205 uses virtual labeled I-cache 122, the bit position 31-15 define a virtual tag I-cache (I$), bit position 14-5 determine the index 207 to select a single row or multiple of 1024 sets of 1 of rows in the I-cache 122 and the bit position 4-0 determine the offset in the column 220C line commands. The line in the I-cache 122 direct display also referred to as "set 1 row". Although eight 32-bit commands, for example, can be accommodated in one line of commands, for simplicity, is illustrated by one team in a virtual tag I$. It should be noted that this disclosure of the invention provides for other sizes of teams. When the virtual address 205 is used in the TLB 128 for broadcast addresses, the bit position 31-12 define a virtual TLB tag, and position of bits 11-0 determine the page offset.

During the search for a specified virtual addresses in the I-cache index 207 of the virtual address selects the appropriate line in the I-cache 122. Active ASID 215 and the position of the bits 31-15 specified virtual address is then compared with the label and virtual ASID mark I$is stored in the selected cache line.

Similarly, during the broadcast TLB for the specified virtual address active ASID 215 and the position of the bits 31-12 of the specified virtual address is compared with labels and virtual ASID tagged TLB, the latter in the TLB 128, to find the matching and, thus, the corresponding PPN.

Although not illustrated here, in some embodiments, the implementation part of the virtual address includes a virtual TLB tag may be one and the same part of the virtual address includes a virtual label of the I-cache. Specialists in the art will recognize that although virtual labeled I-cache 122 is illustrated as a cache direct mapping, the I-cache 122 may also be implemented as a cache with multiple access to contact groups of records as sets from multiple rows.

Returning to the TLB 128, depicted as the relationship (ratio) of aliases, and the relationship of discernment. The connection alias occurs when the same number of physical page (PPN) is located in two or more entries in the TLB 128. For example, both entries 211 and 213 reference PPN 0x80000. In this example, entry 211 and 213 have the same virtual TLB tag, but associated with different software processes to make a unique combination (a combination of) label ASID / virtual TLB tag. Record 212 and 214 are aliases of each other, because both refer to the PPN 0x90000. In relation to each other records 212 and 214 have a unique virtual TLB tag and a unique label ASID, to determine a unique combination of ASID / virtual TLB tag. The communication time is icene occurs when the same virtual TLB tag corresponds to two or more different numbers of physical pages. Writing 211 and 212 represent the relationship of discernment, as the same virtual TLB tag (TLBtag_A) corresponds to two different numbers of physical pages, 0x80000 and 0x90000, respectively.

Recognizing that the virtual tag TLB virtual tag I$ are composed of the positions of bits in the virtual address (some of them are common bit positions), the entries in the TLB 128 refer to the entries in the I-cache 122. Therefore, for the sake of the legend using the subscript when referring to a specific virtual tag I$ (for example, I$tag_Aspecifies that the value of a particular virtual label I$ is in communication with the virtual TLB tag with the same subscript (for example, TLBtag_A). In an exemplary embodiment, figure 2 virtual TLB tag contain more bits than the virtual label I$. Therefore, one virtual TLB tag may correspond to one or more virtual tags I$. Thus, one TLB entry having the number of a physical page may correspond to one or more entries of the I-cache, meaning that the command or commands in the I-cache 122 also can physically be placed on the number of the physical page corresponding entry TLB. For simplicity, it should be noted that not illustrated su the entries of the I-cache, specific entry TLB. Taking into account the above relation one-to-many between TLB entries and the entries of the I-cache when the specified line of I-cache is associated with the same label ASID and value labels of the virtual addresses in the given string TLB, the command or commands in the specified line of the I-cache can optionally be placed on a page of the physical address space, the corresponding page of the virtual address space associated with a given string TLB.

Over time, the entries in TLB 128 and I-cache 122 may become obsolete. For example, if ASID reused following neotomas computer program and convert virtual [address] in the physical at the next program different than the previous program, the entries in the TLB and I-cache, containing reusable ASID, will not be correct since they will be converted to a physical address associated with the previous computer program. To maintain the coherence of the TLB and the cache uses the schema of the control logic 110 to control the obsolete entries in TLB 128 and I-cache 122. In General, a computer program written for the physically labeled I-cache can be easier than written for the virtual labeled I-cache in relation to the management of obsolete entries in the I-cache for various reason is, including the fact that the problem of aliases does not exist in physically marked I-cache, and that a simple change in the transformation of a virtual address into a physical does not require invalidation of the I-cache is physically marked I-cache. However, computer programs, written for physically marked I-cache and written to the virtual labeled I-cache, must include an explicit command for invalid TLB changing the compliance of the specified virtual address for the specified process ID from one physical address to another.

There are two main classes of scenarios, where the entries of the I-cache must be made void by using virtual bulleted cache commands. The first class of scenarios concerning changes in the address translation, where, for example, the virtual address is converted to a different physical address. In traditional implementations of virtual labeled I-cache command on the invalidity of the I-cache is used to invalidate I-cache for this class of scenarios. In addition, in the first class script commands on the invalidity of TLB is used to invalidate TLB in traditional implementations of virtual labeled I-cache and physically labeled I-cache. The second class of scenarios involves a situation where changing the contents of physical memory. In the second class of scenarios team on the invalidity of the I-cache is used to invalidate I-cache in the traditional implementations of virtual labeled I-cache and physically labeled I-cache. However, in traditional implementations physically labeled I-cache command on the invalidity of the I-cache only needs to identify the physical address of the changed memory to make (it) is not valid, unlike all possible virtual addresses that may belong to this physical address in the traditional implementation, the virtual labeled I-cache.

Diagram of the control logic 110 is configured to recognize that the first class of scenarios that traditionally would require a computer program to run the apparent invalidity of the I-cache for the virtual labeled I-cache, also requires a computer program to cause the invalidity of the TLB even for physically labeled I-cache. For example, one scenario involves a situation where the combination of ASID / virtual TLB tag is converted to a new number of the physical page. In this scenario, the circuit 110 of the control logic in response to an explicit command for invalid TLB invalidates entries in the TLB 128 concerning the combination ASID / virtual TLB tag, and also invalidates entries in the virtual mark is proofed the I-cache 122, concerning the combination ASID / virtual label of the I-cache. In some embodiments, the implementation of the explicit command of the TLB invalidation causes instant invalidate all entries in the I-cache 122, for any given combination ASID / virtual TLB tag.

Regarding the second class of scenarios aimed at modification made to the content in the specified physical address, the computer program generates an explicit command on the invalidity of the I-cache to cause an update to the I-cache 122. The contents of the explicit command of the invalidity of the I-cache may specify or not specify a virtual address associated with the changed physical address, or changed physical address.

In one embodiment, the circuit 110 of the control logic in response to this explicit command on the invalidity of the I-cache is configured for instant invalidating all entries in the virtual bulleted I-cache 122. In this embodiment, a virtual address associated with the specified physical address, or, in the alternative, the specified physical address can be specified in an explicit command on the invalidity of the I-cache. However, since all the entries of the I-cache instantly become invalid, the specified virtual or physical address of the explicit command of the invalidity of the I-cache is simply ignored.

In Alt rnative embodiment, the circuit 110 of the control logic in response to an explicit command on the invalidity of the I-cache is configured for selective invalidation of entries in the virtual bulleted I-cache 122. As I write cache, as a rule, have a virtual labels that correspond to the physical address, write I-cache, which may correspond to the specified physical address, you will need to invalidate. Refer to the entries in rows 212 and 214 in the TLB 128 for example, identification information of the multiple virtual addresses for which the corresponding entries of the virtual labeled I-cache will need to invalidate the result of changes in the content of the physical address. These records are records-aliases and converted in the same room 0x90000 physical page.

Similarly, entry 225 and 224 I-cache are also located at the physical address specified by the first 17 bits of the number of the physical page, because the value of the virtual labels I$ (I$tag_Aand I$tag_B) refer to the value of the virtual TLB tags (TLBtag_Aand TLBtag_Brespectively, as illustrated by the double-imposed value of the positions of bits in the virtual address 205 discussed above. Therefore, if, for example, the contents of the physical address 0x9000_0000 changes, the record 225 and 224 together with any other neprogruntovannye records whose teams are also on the physical address 0x9000_0000 will be selectively made invalid circuit 110 operate is her logic. More specifically, in this embodiment, perform a selective invalidation of entries in the virtual bulleted I-cache 122 diagram of the control logic 110 is configured to invalidate all entries associated with the particular virtual indexes I-cache, at which the specified physical address could be, for example, all records in the selected set I-cache.

Figure 3 is a block diagram illustrating the implementation of selective invalidation many records virtual labeled I-cache, which could be associated with a physical address in the I-cache 122 direct display. As depicted in the virtual address 205, the position of the bits 14-12, or link 305, are part of bits of the index, also called bits index I-cache when the virtual address 205 uses virtual labeled I-cache 122. Position bits 14-12 are also part of the virtual TLB tag. However, since the positions of the bits 14-12 are transmitted bits during address translation, these bits are part of the non-physical page corresponding to the virtual address 205. Since the position of bits 14-12 not used virtual mark I$ and the number of the physical pages can be specified for the execution of invalidity, each combination of bits 14-12 defines the boundaries 0, 128, 256,... 896 in virtual brand is consistent I-cache 122, where could be associated to the I-cache corresponding to the number of the physical page. The remaining bits of the index bits 11-5 or link 315, are not broadcast during the broadcast address and, thus, are shared between the virtual address 205 and the translated physical address. Therefore, bits 11-5 indicate the offset from the defined borders, to find the corresponding entries of the I-cache, possibly related to the physical page. As the link 305 contains three bits, the circuit 110 of the control logic in response to the physical address that should be made invalid, can be configured for simultaneous implementation of the invalidity of the eight entries in the virtual bulleted I-cache 122 by combining each combination of bits 14-12 bits 11-5 physical address.

As a rule, because the bits 11-0 not be translated using broadcast addresses, they do not differ between the specified physical address and any virtual addresses that could be translated into the physical address. In other words, all virtual addresses that may correspond to the specified physical address must match the physical address in bits 11-0. Therefore, any bits of these positions 11-0, which are used as part of the index of the I-cache to choose the abortion practices I-cache, which may contain entries that match a specified physical address must have the same value as the corresponding bits of the physical address. It is only those bits of the index of the I-cache in positions 14-12, for example, which can take a different value than the corresponding bits of the physical address, still identifies the set of records may contain records that match the specified physical address.

In response to an explicit command on the invalidity of the I-cache that identifies the physical address that you want to invalidate I-cache due to the fact that the contents of this physical address has changed, the circuit control logic 110 uses bit positions 11-5 to determine the offset from the boundaries defined bits 14-12 to invalidate all entries in the translated set of matching entries in the I-cache, allowing you to invalidate I-cache set-based, and not based on the entire I-cache. With one command, specifying the physical address that you want to invalidate, or, alternatively, a virtual address associated with an invalid physical address, this implementation allows software written for the model physically labeled I-cache, automatically start the execution operation n is actually the I-cache on the virtual bulleted I-cache, to ensure that all possible aliases, virtual address for the specified physical address be removed from the cache. As described, such removal may be based on a string, set, or the entire cache. Thus, the virtual labeled I-cache properly controlled without any additional load on the software that was written for the model physically labeled I-cache.

The number of concurrent indexes in virtual bulleted I-cache 122 with schema 110 logic depends on multiple associativity virtual labeled I-cache. 4 is a block diagram illustrating a sample implementation of the invalidity of the recordset virtual labeled I-cache, which could be associated with a physical address in the two-input I-cache 422 multiple access. In addition to its associativity, input I-cache 422 multiple access is a 32-kilobyte virtual labeled I-cache with 32-byte lines and, accordingly, may be similar to the I-cache 222. Virtual address 405 is a 32-bit (bit) address stored in the register, such as the program counter (PC), and similarly virtual address 205 is depicted showing two overlapping values for bit positions. I-cache 422 has an index 418, have d size nine bits, and, accordingly, the virtual tag I$, have a size of 18 bits. For this variant of implementation of the position bits 13-12 or translated bit position 410 will determine the four borders, resulting in four concurrent index, and bit positions 11-5 or netransliruemye bit position 415 would determine the offset between each of the four edges to selectively invalidate the line in the virtual bulleted I-cache. In two cache multiple access each row includes two cache line. Therefore, the circuit 110 control logic simultaneously indexes the four cache line and thus invalidates eight records virtual labeled I-cache.

It should be noted that the various dimensions and configuration of a virtual labeled I-caches are considered as additional embodiments. As an example, 4-shadowy an implementation option multiple access 32-kilobyte virtual labeled I-cache with 32-byte lines result in the index that have a size of eight bits and, accordingly, the virtual tag I$, have a size of 19 bits. 4-Vodolaga I-cache with multiple access position 12 bits would define two boundaries, and bit positions 11-5 determine the offset from the two boundaries to selectively make negatve the preliminary record in 4-vchodove I-cache.

As another example, 8-shadowy an implementation option multiple access 32-kilobyte virtual labeled I-cache with 32-byte lines results in the index that have a size of seven bits, and accordingly, the virtual tag I$, having the size of 20 bits, the size of the virtual TLB tag and the actual number of physical pages. For 8-Vodolaga I-cache with multiple access no defined borders, and bit positions 11-5 index 8-shadowy cache. Note, however, that each line in 8-vchodove the cache contains 8 cache lines, eight cache lines selectively invalidated. In addition, as in this example, the size of the virtual TLB tag is equal to the size of the virtual label I$, any entries in the I-cache, which can be associated with the specified physical address, is guaranteed to be located at the entrance to the I-cache, the selected one index I-cache, which, in turn, are similar to the positions of bits of the index from the specified physical address, as these bit positions are not broadcast. In other words, when all bits of the index of the I-cache are bit positions in the shift on the page, respectively, the bits of the index of the I-cache will not be translated using the translation address any entries in the I-cache, which can be associated with the specified physical address, to ensure the Annot be located at the entrance to the I-cache, selected this one index I-cache.

These previous examples demonstrate how virtual indexed and virtual labeled I-cache with multiple access in accordance with the ideas of this disclosure affects selective execution of invalidity. In particular, the higher the multiple access virtual indexed and virtual bulleted cache, the less the number of bits that can be transferred by the process of address translation, but which are used in their netransliruemoi form index I-cache, leading to fewer selectively invalid rows I-cache. Similarly, the physical page size affects the number of bits of the addresses, which are translated. As the page size increases, transmitted less upper order bits in the virtual address. Therefore, the larger the page size, the smaller the number of bits that can be transferred by the process of address translation, but which are used in their netransliruemoi form for index I-cache, again leading to fewer selectively invalid rows/sets of the I-cache.

In the case where the number of bits in the number of the physical page is the same as the number of bits in the virtual label of the I-cache, no bits 305 index I-cache, which, ultimately, under alauda broadcast through the process of address translation. Thus, the set of possible inputs to the I-cache is reduced by one guaranteed entrance. In General, the increase in page size leads to smaller broadcast bits, and thus, decreases the amount of possible entries of the I-cache, associated with the physical address.

Returning to figure 2, the circuit control logic 110 receives as input commands on the invalidity of, for example, the Command TLB invalidation and Commands on the invalidity of the I-cache from the computer program, regardless of whether written a computer program to physically marked I-cache or virtual labeled I-cache. These teams of invalidity may be made available from cascade decoding in the pipeline 120, such as a cascade 160V conveyor, for example, the Circuit 110 of the control logic responds to many Commands TLB invalidation to invalidate one or more entries in the I-cache 122 using known mechanisms, such as the formation of control signals of the I-cache to invalidate one or more entries of the I-cache in response to known commands on the invalidity of the I-cache. With the help respond to many Commands about invalidation of TLB for additional control of the I-cache and response team on the invalidity of the I-cache for the scenario, indicating that the contents of the Phi is practical address has changed, diagram of control logic 110 frees the computer program from having to issue commands on the invalidity of the I-cache separately for each scenario that requires traditional virtual labeled I-cache. Therefore, a computer program written to control physically marked I-cache can now successfully executing on the processor 100, the control virtual index, virtual labeled I-cache, so that it behaves as if it was physically indexed and physically labeled with the position of the software.

Diagram of control logic 110 also responds to well-known teams on the invalidity of the I-cache to invalidate one or more entries in the virtual bulleted I-cache 122, for existing computer programs that are written to manage the virtual labeled I-cache. Additionally, in some embodiments, the implementation scheme of the control logic 110 may take an optional enable signal 237 from the processor 100, which can be used if a computer program specially written for the virtual labeled I-cache. Enable signal 237 may be caused as a result of the discharge state of the processor, discharge configuration, etc. When you call enable signal 237, CX is 110 mA logic works, as explained above. When an enable signal 237 is not called (forbidden), diagram of the control logic 110 will respond to Commands on the TLB invalidation to invalidate one or more entries of the TLB 128, and will respond to Commands on the invalidity of the I-cache to invalidate one or more entries in the virtual bulleted I-cache 122. When an enable signal 237 is not called (forbidden), diagram of the control logic 110 will not make invalid entries in the virtual bulleted I-cache 122 in response to Commands on the invalidity of TLB and will not necessarily invalidate more records I-cache than those specifically associated with the specified virtual address, in response to Commands on the invalidity of the I-cache.

In some embodiments, the implementation scheme of the control logic 110 may include a generator 235 of the control signal TLB and generator 245 control signal of the I-cache. Inputs 241 and 243 in the generator 245 control signal I-cache respectively served Commands on the invalidity of TLB and Commands on the invalidity of the I-cache in the generator 245 control signal of the I-cache. Generator 245 control signal of the I-cache is configured for generating control signals to invalidate one or more entries in the virtual bulleted I-cache 122 on the basis of the accepted command of invalidity. Generator 235 of the control signal TLB generates control signals in a known manner to invalidate one or more entries in the TLB 128 based on the specific type of the accepted command of the TLB invalidation. When the input to the generator 245 control signal of the I-cache is the result of the command on the invalidity of the I-cache, generator 245 control signal I-cache generates control signals in a known manner to invalidate one or more entries in the virtual bulleted I-cache 122. Additionally, the generator 245 control signal I-cache generates control signals to invalidate one or more entries in the virtual bulleted I-cache 122 in response to Commands on the invalidity of TLB. The following table describes the functional behavior of the generator 245 control signal I-cache caused by taking the following Commands on the TLB invalidation.

The column is 220D one embodiment, to ensure that no erroneous "coincidence" with the entry in the I-cache 122 on the basis of comparison virtual label when the record was set during the time when the translation mechanism was in the same condition unlock (permissions), but the coincidence occurs at a later time, when the translation mechanism is another condition unblock (enable). For example, in situations where the translation mechanism, such as TLB 128 has a function of resolution, which allows TLB 128 to be permitted or prohibited condition stored in the I-cache 122 zavisimost to contain a flag value, indicates whether working TLB at that time when you saved the record. When the recording is saved in the I-cache during idle TLB 128, the stored record associated with the physical address, which is the same as netransliruemye virtual address.

In the case of switching TLB from the prohibition in the write-enable I-cache that were saved during the idle TLB are invalidated circuit 110 of the control logic in response to the signal 239 switch (transition) TLB. Also in the case of switching TLB from permission to prohibition of entry I-cache that were saved while working TLB are invalidated circuit 110 of the control logic in response to the signal 239 switch TLB. The signal 239 transition TLB is usually formed at the crossings TLB 128 of prohibition in the resolution and Vice versa. In particular, the generator 245 control signal of the I-cache in response to a signal 239 transition TLB generates control signals to invalidate entries in the I-cache 122, which coincide with the flag field that indicates the records that were initially retained until TLB 128 was in a state from which he has just switched. In an alternative embodiment, can be set flags column 220D, when the status of the address table is allowed. In this embodiment, when the search in the I-cache, discusses the flags to determine whether there is a match with the current state of the address table.

In another alternative embodiment, the problem of ensuring that not a false "match" with the I-cache, installed in the previous inconsistent state, is eliminated without the optional column 220D. In this embodiment, the circuit 110 logic instantly invalidates the entire cache 122, when the signal 239 changing permissions TLB indicates that there was a switch in the mechanism of TLB permission.

Specialists in the art should recognize that the size of the virtual address 205 and dimensions TLB 128 and I-cache 122 can be applied to other variants of implementation without deviating from the ideas of the invention.

5 is a flowchart of operations illustrating a method 500, in order to make virtual bulleted instruction cache to act as if he was physically marked by the instruction cache from the point of view of the computer program. At functional step 510, the method selects the command.

The selected command is sent to the decoder 530 commands, where the selected command is decoded. At step 540, the method determines the type of command. If the type command is a command for invalid broadcast address, the method proceeds to step 550, which invalidates one or b is more of the entries in the TLB, for example TLB 128, in accordance with the invalidation broadcast addresses. Next, the method proceeds to step 560. At step 560, the method also invalidates one or more entries in the I-cache 122 in accordance with the conversion commands for invalid broadcast address, for example, as defined in Table 1. Specialists in the art will take into account that the order of step 550 and stage 560 may be changed without affecting the process of implementation of invalidity. Returning to step 540, if the command type is the team on the invalidity of the I-cache, the method proceeds to step 560 to invalidate one or more entries in the I-cache 122 in accordance with the command on the invalidity of the I-cache. Returning to step 540, if the type command is not a command on the invalidity of any type, then return to step 510 to select the next command.

Various explanatory logical blocks, modules, circuits, elements and/or components described in relation to options for implementation disclosed in this document, may be implemented or performed using a General purpose processor, a digital signal processor (DSP), a specialized integrated circuit (ASIC), programmable gate array (FPGA) or other programmable logic components is the schemes for discrete components or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in this document. The General-purpose processor may be a microprocessor, but in an alternative embodiment, the processor may be any standard processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing components, such as combinations of a DSP and a microprocessor, a variety of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The methods or algorithms described in relation to those disclosed in this document, options for implementation, can be implemented directly in hardware, in a software module, executable by the processor, or a combination of both. A software module may reside in RAM memory, flash memory, memory, ROM memory, EPROM (electrically programmable ROM), EEPROM (electrically erasable and programmable ROM), registers, hard disk, removable disk, a CD-ROM or any other form of storage medium known in the art. The storage medium may be connected to the processor so that the processor can read information and zapisi the te information to the media. Alternatively, the storage medium may be integral with the processor.

Although the invention is disclosed in the context of embodiments, it should be noted that the usual experts in this field can be used with a wide range of implementations with regard to the above discussion and the claims which follows.

1. The caching system commands containing:
virtual bulleted instruction cache;
means for address translation, and the said means responsive to the command for invalid broadcast address; and
the control logic circuit configured to invalidate less than all entries in the virtual bulleted instruction cache in response to a command for invalid broadcast address.

2. The system according to claim 1 in which the means for address translation buffer is a quick conversion address (TLB).

3. The system according to claim 1, in which the control logic circuit is configured to perform an instant invalidation virtual bullet to the instruction cache in response to a command for invalid broadcast address.

4. The system according to claim 1, in which the control logic circuit is configured to invalidate one or more entries in the virtual bulleted instruction cache, the corresponding identificat the ROS service application (ASID), the specified command on the invalidity of broadcast addresses.

5. The system according to claim 1, in which the control logic circuit is configured to invalidate a sample set of records in a virtual bulleted instruction cache corresponding to the index specified in the command is invalid broadcast address.

6. The system according to claim 1, in which the control logic circuit is configured to perform an instant invalidation virtual bullet to the instruction cache in response to a change of state funds for broadcast addresses.

7. The system according to claim 1, in which the control logic circuit includes an input for receiving the enable signal, and the control logic circuit is configured to invalidate an entry in the virtual bulleted instruction cache in response to a command for invalid broadcast address after receiving the permission signal.

8. The system according to claim 1, in which the control logic circuit is configured to perform an instant invalidation virtual bullet to the instruction cache in response to a command on the invalidity of the instruction cache that indicates the invalidity of the specified physical address.

9. The system according to claim 5, in which the index contains the translated bit position and netransliruemye bit positions,
where each combination of values Tran the isolation of bit positions defines the boundaries in virtual bulleted cache commands,
moreover, the control logic circuit is additionally configured to perform a selective invalidation of entries in the shift from defined borders, and the offset specified by the value netrenirovannykh bit positions.

10. The system according to claim 1, which is located in the processor.

11. The method of virtual work bulleted cache commands, as if he was physically marked by the instruction cache from the point of view of a computer program containing phases in which:
take command on the invalidity of broadcast addresses; and invalidate less than all entries in the virtual bulleted instruction cache in response to a command for invalid broadcast address.

12. The method according to claim 11, in which the phase in which invalidate the entry in the virtual bulleted cache of commands further comprises a stage on which:
instantly invalidate virtual bulleted instruction cache.

13. The method according to claim 11, in which the phase in which invalidate the entry in the virtual bulleted cache of commands further comprises a stage on which:
invalidate one or more entries corresponding to the service ID of the application (ASID), the specified command on the invalidity of broadcast addresses.

14. The method according to claim 11, in which step, which makes negatve the compulsory entry in the virtual bulleted instruction cache, it further comprises a stage on which:
invalidate the set of selected entries corresponding to the address specified by the command on the invalidity of broadcast addresses.

15. The method according to claim 11, in which the phase in which invalidate the entry in the virtual bulleted cache of commands further comprises a stage on which:
instantly invalidate virtual bulleted instruction cache in response to a change of state funds for broadcast addresses.

16. The method according to claim 11, in which the phase in which invalidate the entry in the virtual bulleted cache of commands further comprises a stage on which:
receive the enable signal; and
invalidate an entry in the virtual bulleted cache command after reception of the permission signal.

17. The method according to claim 11, in which the phase in which invalidate the entry in the virtual bulleted cache of commands further comprises a stage on which:
take command on the invalidity of the instruction cache that indicates the invalidity of the specified physical address; and
instantly invalidate virtual bulleted instruction cache in response to a command on the invalidity of the instruction cache.

18. Diagram of control logic for instructing branded virtual instruction cache to act as if what he was physically marked by the instruction cache, from the point of view of a computer program that contains:
the first input to accept commands for invalid broadcast address; and
means for generating control signals to invalidate less than all entries in the virtual bulleted instruction cache in response to a command for invalid broadcast address.

19. Diagram of control logic for p, further comprising: a second input for receiving commands on the invalidity of the instruction cache, and the said means for generating control signals responsive to the command on the invalidity of the instruction cache.

20. The control logic circuit according to claim 19, further comprising:
the third input to disable the means for generating control signals to invalidate entries in the virtual bulleted instruction cache in response to a command on the invalidity of broadcast addresses.