|
RusosPatentes.com
|
Discrete-analogue device. RU patent 2432611. |
|
        
|
FIELD: information technology. SUBSTANCE: device has five analogue multipliers, four analogue subtractors and three analogue adders. EFFECT: performing logic and arithmetic operations with discrete and analogue values of zeroes and ones. 1 dwg, 3 tbl
|
 Discrete-analogue device / 2427036Device has first and second analogue subtractors, first and second analogue multipliers and an adder. Analogue values (one or zero) or discrete values (with logic level one or zero) enter first, second and third data inputs in parallel. An additional data input of device "1" from which the value of the signal entering the third data input of the device is subtracted. |
 Discrete-analogue device / 2422897Discrete-analogue device has a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth and an extra data input, a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth, a tenth, an eleventh, a twelfth and a thirteenth analogue subtracter, as well as a first, a second, a third and a fourth analogue multiplier, the extra data input of the device "1" is the first data input of the first-thirteenth analogue substracter. |
 Multi-zone roll-out converter / 2422896Multi-zone rolling out converter has a first electrical power source, series-connected input signal source and roll-out amplifier, consisting of series-connected first adder and an integrator, the output of which is connected to a group of n main relay elements, where n≥3 is an odd number, the outputs of which are connected to a second adder whose output if connected to the second input of the first adder. The output of the fist electrical power source is connected to the roll-out amplifier and specifically to power terminals of the first and second adders, the integrator and power terminals of the main relay elements. The disclosed converter also includes an output stage consisting of (n≥3), where n is an odd number, extra optocouples connected in series to extra relay elements and a third adder, as well as a second electrical power source. |
 Analogue multiplier of voltages / 2396595Device comprises the first source of the first multiplied voltage ux, the second source of the first multiplied voltage ux antiphased to the first source, the first and second antiphased sources of the second multiplied voltage uy, the first, second, third and fourth input transistors, the first and second current-stabilising two-terminal networks, the first load element, new connections are included - base of the second inlet transistor is connected to the first source of the second multiplied voltage uy, base of the fourth inlet transistor is connected to the second source of the second multiplied voltage uy, besides between emitter of the first input transistor and bus of power supply source there is the first additional capacitor connected by alternating current, and between emitter of the third input transistor and bus of power supply source there is the second additional capacitor connected by alternating current. |
 Zero current sensor / 2390906Zero current sensor includes in-series connected control signal source, the first four-pole device, summator, integrator, the first relay element the output whereof through the second four-pole device is connected to the second input of summator, in-series connected proportional-differentiating element, demodulator, smoothing filter, the second relay element the output of which is connected to output terminal. Also to the device there introduced is non-linear element with dead zone, the input of which is connected to output of integrator, and output is connected to the third input of summator; at that, input of proportional-differentiating element is connected to output of the first relay element. |
 Analogue voltage multiplier / 2383054Invention relates to radio engineering. The analogue voltage multiplier has a first source of the multiplied voltage ux, a second source of the first multiplied voltage which is antiphase to the first source, a voltage uУ - current converter connected to the source of the second multiplied voltage uУ, which has first and second antiphase outputs, a first input transistor whose base is connected to the first source of the first multiplied voltage, a second input transistor whose emitter is connected to the emitter of the first input transistor and connected to the first output of the voltage uУ - current converter, and the collector is connected to the first output of the analogue signal multiplier and the first load element, a third input transistor whose base is connected to the second source of the first voltage multiplier , and the emitter is connected to the emitter of a fourth input transistor and the second output of the voltage-current converter, where the collector of the fourth input transistor is connected to the first output of the analogue voltage multiplier. |
 Analogue voltage multiplier / 2383053Invention relates to radio engineering and communication and can be used in automatic gain control devices, phase detectors and modulators, as well as phase-locked loop systems and frequency multiplication systems or as an amplifier whose voltage transfer ratio depends on the control signal level. The analogue voltage multiplier has first and second input transistors of a first differential amplifier whose emitters are connected to the current input of the first differential amplifier, first and second input transistors of a second differential amplifier whose emitters are connected to the current input of the second differential amplifier, a third differential amplifier which has first and second inputs of a first multiplication channel, as well as first and second current outputs. The circuit includes first, second, third and fourth reference current sources, first and second potential matching circuits. |
 Analogue voltage multiplier / 2382405Invention relates to radio engineering and communication and can be used in automatic gain control devices, phase detectors and modulators, as well as in phase-locked loop systems and frequency multiplication systems or as an amplifier whose voltage transfer ratio depends on the control signal level. To achieve the result, the analogue voltage multiplier has a first differential stage (1), which has current outputs (2) and (3), potential inputs (4) and (5) and a current input (6), a second differential stage (7) having current outputs (8) and (9), potential inputs (10) and (11) and a current input (12). The second (5) potential input of the first (1) differential stage is connected to the first (10) potential input of the second differential stage (7) and the first input (13) of the first multiplication channel X. The first (4) potential input of the first differential stage (1) is connected to the second (11) potential input of the second differential stage (7) and the second input (14) of the first multiplication channel Y. The analogue voltage multiplier also has a first (15) controlled reference current source, and a second (16) controlled reference current source. The circuit also includes a first additional composite transistor (17) whose base is the first (18) input of the multiplication channel Y, the collector (emitter) is connected to the current input (12) in the common emitter circuit of the second (7) differential stage, and the emitter (collector) is connected to the current input (6) in the common emitter circuit of the first (1) differential stage. |
 Device of logical and arithmetical operations with discrete and analog values of zeros and units / 2356090Invention is related to computer engineering and may be used for realisation of both logical and arithmetical operations with discrete and analog values of zeros and units. Device comprises analog subtractors, analog multipliers and analog summator. |
 Multipurpose module / 2348976Invention concerns field of computer facilities and application in computing systems with parallel processing of the information and high speed can find. The device contains blocks of devices "AND", (n+1)-input adders, the logic block consisting from r of chains from consistently included frequency-modulated generator of start, the high-frequency self-oscillator with the plan of self-clearing which is delivery-radiating systems of the high-frequency self-oscillator. |
 Forward and electronic mail content / 2432603Tools are configured to analyse content in order to determine its characteristics, classify the content based on its characteristics and display content in a user interface which is specialised with respect to the classification. The tools can also organise content elements into groups based on a common characteristic and allow the user to select content elements through their group. In response to selection of a group by the user, the tools can display content, display an attachment and change characteristics of content elements in the group. |
Σ(Σ) of positional format of multiplicand [mj]f(2n) and multiplier [ni]f(2n) (versions)" target="_blank"> Σ(Σ) of positional format of multiplicand [mj]f(2n) and multiplier [ni]f(2n) (versions)" align=left vspace="30" hspace="30" /> Functional structures for parallel-serial ripple carry fj+1(←←)+ и fj(←←)+ in conditional "i" "formation zone" for correcting resultant preliminary first level sum of arguments of partial products of parallel-serial multiplier fΣ(Σ) of positional format of multiplicand [mj]f(2n) and multiplier [ni]f(2n) (versions) / 2431886Invention can be used when designing arithmetic units and performing arithmetic operations, particularly preliminary summation of arguments of a multiplicand [mj]f(2n) in positional format. In one version of the invention, functional structures are in form of two structure-equivalent logic carry-over functions of the j-th and (j+1)-th bits, where each bit contains elements performing AND, OR and NOT logic functions. |
 Mechanism for dynamic syntax analysis/assembly based on scheme for syntax analysis of multi-format messages / 2429533Mechanism converts messages in different formats to a common format, and the common format message is processed by a business logic application. The syntax analyser analyses the message and determines the suitable scheme for the specific format of the received message. The scheme is a data structure in a scheme register which includes a grammatical structure for the received format, as well as handler pointers for converting different message fields to an internal message format using a grammatical structure ("grammar" may include a field priority, field type, length, symbol coding, optional and mandatory fields etc). The handlers are compiled separately. As far as formats change, new formats or changes in old formats may be dynamically added to the syntax analysis/assembly mechanism by loading a new scheme and handlers. |
 Quick-acting generator of random shifts and combinations / 2427885Device comprises a unit of data registers arranged with the possibility of parallel and serial data loading, and a switching matrix with baseline topology. The device comprises n data outputs, formed by outputs of data registers unit, m binary inputs of control signals, to which random signals are supplied from external sources, input S of serial download of initial line of reinstalled data A1 - An, formed by an input of serial downloading of data registers unit, a binary unit to control serial and parallel recording of data into a unit of data registers PE, input of clock pulses of data registers unit clk. Parallel q digit outputs of data registers unit are electrically connected with q digit inputs of the switching matrix, outputs of the switching matrix are electrically connected to parallel q digit inputs of data registers unit. |
 Completion of instruction with account of consumed energy / 2427883Method includes the following: reception of static information, related to an instruction, as information is extracted, and preservation of static information section in the first section of the extraction buffer, and preservation of the second section of static information in the second section of the extraction buffer, if static information stands for an event, which should be executed at the time of instruction completion; generation of an early signal of guarantee at the time of instruction completion for the instruction, if static information related to the instruction is not available in the second section of the extraction buffer; otherwise supply is connected in the second section of the extraction buffer, to ensure access to the second section of static information, in which, provided that early signal of guarantee has been generated, the second section of the extraction buffer is switched off, to reduce consumed power in process of normal actions on completion of the instruction. |
|
Discrete-analogue device / 2427036 Device has first and second analogue subtractors, first and second analogue multipliers and an adder. Analogue values (one or zero) or discrete values (with logic level one or zero) enter first, second and third data inputs in parallel. An additional data input of device "1" from which the value of the signal entering the third data input of the device is subtracted. |
![Functional input structure with logic differentiation procedure d/dn of first intermediate sum of minimised arguments of terms ±[n<sub>i</sub>]f(+/-)<sub>min</sub> and ±[m<sub>i</sub>]f(+/-)<sub>min</sub> (versions of russian logic)](http://img.russianpatents.com/img_data/241/2417971-s.gif) Functional input structure with logic differentiation procedure d/dn of first intermediate sum of minimised arguments of terms ±[ni]f(+/-)min and ±[mi]f(+/-)min (versions of russian logic) / 2427028In one version of the invention, the i-th bit of the functional structure of the adder is in form of positive and conditionally negative summation channels. Each channel has elements which execute logic functions AND, OR, NOR, NAND and NOT. |
 Device-specific content indexing for optimised device operation / 2427026Index database which is customised for a specific responder device using device parameters of the responder device is generated. The index database is generated on a device other than the responder device. An indication of a selection of objects is received and parameters of the responder device are accessed. An index database is generated for the selection of objects using parameters of the responder device. The index database may then be transferred to the responder device. |
j]f(2n) of positional format in parallel-serial multiplier fΣ(Σ) (versions)" target="_blank"> j]f(2n) of positional format in parallel-serial multiplier fΣ(Σ) (versions)" align=left vspace="30" hspace="30" /> Functional structure of serial ripple carries fj+1(←←)+ and fj(←←)+ of conditional "i" formation zone for correcting resultant sum of presummation of active arguments of multiplicant [mj]f(2n) of positional format in parallel-serial multiplier fΣ(Σ) (versions) / 2424550In one version of the invention, in the i-th formation zone comprising (j+1)-th and j-th bits, functional structures are equivalent, wherein each functional structure contains elements which realise logic functions AND and OR. |
![Functional structure of pre-adder f<sub>Σ</sub>([m<sub>j</sub>]&[m<sub>j</sub>,0]) of parallel-series multiplier f<sub>Σ</sub>(Σ) with procedure for logic differentiation d/dn of first intermediate sum [s<sup>1</sup> <sub>Σ</sub>]f(})- or structure of active arguments of multiplicand [0,m<sub>j</sub>]f(2<sup>n</sup>) and [m<sub>j</sub>,0]f(2<sup>n</sup>) (versions)](http://img.russianpatents.com/img_data/239/2394063-s.gif) Functional structure of pre-adder fΣ([mj]&[mj,0]) of parallel-series multiplier fΣ(Σ) with procedure for logic differentiation d/dn of first intermediate sum [s1 Σ]f(})- or structure of active arguments of multiplicand [0,mj]f(2n) and [mj,0]f(2n) (versions) / 2424549In one version of the invention, the functional structure in each bit contains elements executing logic functions OR, AND, NAND and NOR, wherein each bit is in form of two summation channels for generating a positive sum and a conditionally negative sum. |
 Pulse code transformer / 2248607Device has information input device, clock generator, connected to address counter with decoder, outputs of which are connected to inputs of recording device, inputs of which are connected to output of programming device, signal generator and multiplexers. Device for recording object sate is connected to output of decoder of cells address of device. Signal generator includes cells for recording checksum. First input of signals generator is connected to output of decoder of address of cells of checksum, second input - to output of recording device, first output - to first inputs of multiplexers, and second output - to first input of binary adder, by its output connected to third input of signal generator and checksum. Outputs of decoder of checksum cells address and decoder of object state recording device cells addresses are connected to second output of address counter, which is connected to second inputs of multiplexers. Recording device is programmable. |
| © 2014 RusosPatentes.com |