Manufacturing method of multi-level copper metallisation of vlsic

FIELD: electricity.

SUBSTANCE: in manufacturing method of multi-level copper metallisation of VLSIC, which involves application operations of metal and dielectric layers, photolithography and selective etching of those layers, chemical mechanical polishing of dielectric layers, to plate of silicium, which is coated with dielectric material with vertical conductors of underlying structure, which protrude on its surface, there applied is multi-layered conducting film consisting of adhesive barrier, etched and auxiliary layers; grooves are formed in auxiliary layer before etched layers by electrochemical method; copper horizontal conductors are grown inside grooves in open sections of etched layer till grooves are fully filled; the second auxiliary layer is applied to surface of plate, and in that layer holes are made to the surface of horizontal copper conductors; vertical copper conductors are grown by electrochemical method in open sections of horizontal conductors till holes for vertical conductors are fully filled; then, auxiliary layers are removed; conducting layers between horizontal copper conductors are removed; dielectric layers are applied to surface of the plate by smoothing and filling methods, and then dielectric material layers are removed above vertical conductors by means of chemical and mechanical polishing method.

EFFECT: improving quality of copper conductors.

16 cl, 11 dwg, 1 tbl

 

The technical field

The present invention relates to the field of electronic technology: manufacturing technology multilevel metallization of integrated circuits.

The level of technology

At the present time in the manufacture of VLSI as guides in multilevel VLSI interconnects are used two types of material: aluminium and copper. Aluminum is used in circuits with a design rule of 0.18 μm and above. Copper is used in VLSI design rule below 0.18 micron. This is due to the fact that with decreasing design rules the resistance of conductors begins to significantly affect the performance of the integrated circuit. However, the amount of signal delay t in the system interconnects depends not only on the total resistance of the conductors, it is also determined by the capacity in the system interconnects. The value of t is directly proportional to the product RC. The transition to copper conductors was defined by its low resistance (approximately twice lower than that of aluminium). At the same time due to the lack of copper volatile compounds at relatively low temperatures to use technology direct etching of the copper through the photoresistive mask was not possible. So they invented the process of Damascen, in which the dielectric layer is etched groove on the surface of the plate, and the bottom wall Cana is OK to apply adhesion.amorality film and the seed layer of copper and then the entire plate, including an internal cavity of the grooves, the electrochemical method is applied to the copper to fill the grooves. From the surface of the plates layers of copper and barrier layer are removed chemical-mechanical polishing. This process, by analogy with Damascus inlay called Damascena. When forming multi-level metallization, including both horizontal conductors of the same level, and vertical connecting conductors of different levels, the process

copper Damascene is used in the form of a Double Damascene, in which the dielectric layer mytravelguide not only grooves, and holes for forming the vertical conductors. Application of barrier and seed layers, and copper deposition occurs simultaneously in the grooves and vertical holes. The DD process was beneficial for the production, the Number of operations it has about 30% less than aluminum process. Usually layers of dielectrics, in which are formed grooves for horizontal and holes for vertical conductors separated by a dielectric retaining layers, which are a barrier to migration of copper ions and are used to stop the etching.

Online published a list of patents on various improvements of the DD process [1]. Now it is fixed 8808 patents. Figure 1 is redstapler one of the route alternatives DD from this list. It we use as a prototype [2].

In position 1 figure 1 shows a fragment of a silicon wafer with a not shown transistor and provodnikov structures, in which the upper dielectric layer on the surface are vertical conductors in contact with the underlying elements of the structure. The top is equipped with a laminated dielectric film including the lower, middle and upper locking, barrier layers and between lower-level and upper vnutrizonovye insulating layers

Usually the first level of conductors in contact with the transistor structure and the first vertical conductor is made of tungsten. The first horizontal level copper conductors have to do to process a single Damascene that slightly lengthens the overall route.

The DD process compared to the aluminum has allowed not only to eliminate the etching of the metal (copper), but also reduced the total number of operations (about 30%) and a range of equipment. At the same time he made a serious complication in a number of operations. First, the total depth of the trench and the transition window is increased to ~to 1.0 μm. This created great difficulties (Problem 1when plotting on the sides and bottom of such grooves and narrow deep hole thin barrier and the germ is o layers (Fig.2 [3]). It is very important that these layers were continuous in all areas of the grooves and holes, and the barrier layer, which occupies within these areas of double thickness, should be required, but the minimum thickness that the core conductor of copper was the largest volume. The barrier layer several functions: it is a barrier against diffusion of copper into the insulating layer of dielectric and adhesive sublayer is for the seed layer. The need to exclude penetration of copper into the insulating layers associated with a high diffusing capacity of copper through some of the dielectric layers, for example silicon dioxide. Reaching transistor structure, copper displays integrated circuit malfunction (Problem 2).

When the electrochemical deposition of narrow grooves are filled faster than wide. Because of this necessary to put "too" thick film of copper to a minimum level the surface of the film of copper over a wide grooves was on the whole wafer above the level of the plate surface before applying the barrier layer.

During chemical-mechanical removal from the surface of the copper plate and then the barrier layer with wide areas of conductors allowed to continue for the removal of copper due to the higher stiffness of the barrier layer, creating conditions for erosion (Dishing out 3) of these sites (Problem 3).

If aluminiumtechnik he is only used for planarization of the surface of the dielectric layer, during the DD process HMP copper is used for planarization of the surface of the plate and to separate the copper conductors on the whole wafer, and it is far more difficult.

The complexity of the process HMP copper films has led many researchers to seek methods of local deposition of copper only in the grooves and the contact window [4]. We have also patented one such electrochemical methods [5].

One is not fully solved the problem of copper metallization DD is smaller than expected, and the lack of reproducibility of resistance to electromigration failure. This is determined by a high defect crystal structure of a copper film deposited by electrochemical method, especially due to the inclusion in the film of copper, carbon, which is present in the electrolyte in the composition of the organic additives, for example, to lighten the surface [6]. In this work it is shown that due to the high defects of the crystalline structure of the copper films immediately after electrochemical deposition of their electrical resistance and mechanical stress they begin to decrease. This occurs at room temperature and can last up to achieve the minimum values from several hours to several months. High defects of the crystal structure of the copper conductor is in, certainly is a major factor in determining their resistance to electromigration. In some works, for example in [7], it is shown that by changing the material, separating the surface of the copper conductor from the insulating dielectric, can significantly be controlled electromigration resistance of copper conductors. From Figure 4 [7] shows that copper conductors, covered with standard DD technology dielectric layers type SiNx and SiCxNyHz, have the lowest activation energy of the process of electromigration. Only 1.4 times higher than the activation energy of the process of electromigration of the copper conductors in the protection of their surface standard barrier layer Ta/TaN. At the same time protecting the open surface of the copper-cobalt alloyed W and R, can increase the activation energy of electromigration at times.

Therefore, there are great possibilities for improving the resistance of copper conductors electromigration failure. Finding solutions to this problem now in the spotlight. For this purpose, in particular, are under development [8] local chemical deposition of cobalt. However, the final industrial results because of a number of the difficulties yet to be achieved. Studies of electromigration process of destruction of multilevel copper metallization has shown that there are early failures caused the failure of the vertical conductors, and late failures associated with horizontal conductors [9]. These failures are attributed to the emergence and movement of the conductors of voids (Figure 5 [10]). It can be assumed that the early failures of the vertical conductors are connected with the fact that the specific ratio of the vertical surface of the conductor to its volume significantly higher than the same ratio for the horizontal conductor. In fact, the main reason for lower than expected, the resistance of copper conductors to electromigration is the high defect crystal structure of electrochemically deposited copper. There is another difficult problem of modern Double Damascene. The deposition rate of copper in different parts of the trench and contact Windows should generally decrease with distance from the surface of the plate. This leads to the fact that at the top of the trench opposing two fronts deposited copper closed earlier than at the bottom. This leads to the formation of voids in the copper conductors (Figure 3 and Figure 7 [17]), which reduces the reliability of conductors and increases their resistance (Problem 4). Continuous reduction in the size of conductors led to the manifestation of the known laws of the increase in bulk resistance of the metal film to reduce its thickness.

Figure 6 [11] shows the change in average resistivity of copper is about what ednica, surrounded on the sides and bottom barrier layer to reduce the width of the conductors. The width of the conductor in a Damascene structure is equivalent to two folded layers, each of which consists of a barrier, bare copper and copper electrochemical layers. The thinner the barrier layer, the thicker the copper and the lower the resistance of the conductor. Using the process of applying the barrier layer ionization spray stream with simultaneous backward sputtering, it is possible to increase its ravnoudalennostj and thereby reduce its average thickness in favor of increasing the thickness of the copper. This method allows you to change the profile of a deposited seed layer of copper at the bottom of the grooves, creating a profile is opened up (superpipeline, 2 and 7). However, with decreasing width of the groove of the average specific resistance of conductors increases sharply (Problem 5). The problem is solved yet due to the significant complexity of the equipment and increase its price?

With the reduction in the width of horizontal and vertical conductors of the barrier layer, in spite of its small thickness, begins to exert strong influence on the average value of the specific resistance of the conductors. It is also seen from Fig.8 [11], where the integrated results of the research of several leading companies.

In the process DD this effect is reinforced by the technology of production is the situation, because copper conductors formed in this way is derived from two independently grown layers. The resistivity of each of these layers, and we can assume dual layer, will be the same and correspondingly higher than for the Explorer of the same width, but grown from one seed. For example, the trench width of 100 nm in the process DD dual copper conductor without barrier layers has ρv≈2,88 µohm·cm, and a barrier layer ρv≈3,84 µohm·cm For copper conductor of the same width, but grown on a single seed layer resistivity without barrier layers is equal to ρv≈2.35 a µohm·cm, and a barrier layer ρv≈2,69 µohm·see Therefore, in the case of barrier layers with a thickness of 5 nm average resistivity of conductors made on the DD process is expected to be 43% higher than that of copper conductors constructed on the seed layer. For copper conductor without barrier layers of this difference may be 23%, which is also a significant amount.

Individual ability to improve performance VLSI is the solution of the problems of forming besprovodnoy insulation with the lowest possible dielectric constant. Widely used in VLSI technology dielectric film of silicon dioxide has a dielectric p. the constant k≈4,0-4,2, and the air gap allows to form the insulation with k≈1. Leading manufacturers of VLSI use in the production of insulating layers with a dielectric constant k≈2,7-3,0. This is achieved using different source of organosilicon compounds (precursors) and different deposition conditions. The challenge is to master production range k≈2,0-2,6. This range of k can be achieved by introducing in the film is controlled by the pore size. However, it should be noted that the introduction of a dielectric film of carbon and porosity leads to a significant deterioration of the mechanical and electrical strength dielectric layers (Problem 6), which leads to problems in chemical-mechanical polishing. When using porous films especially complicated issues of integration of technological operations on the route of manufacture. In particular, in the process of plasma-chemical etching and removing the photoresist in the pores penetrate the reaction products, which are difficult to later delete (Issue 7), which increases the effective value of k in this area. For small values of the width of the dielectric gaps that may negate the effectiveness of the introduction of porosity. Currently under extensive research on various ways to create an air gap between adjacent PR is the water the same level. It is believed that this approach is the most realistic and reduces the effective dielectric constant of 2.2 to 2.5. In [12] concluded that air gaps come even faster than expected. The literature describes two main approaches to creating air gaps between closely spaced conductors of the same level. In the first method, proposed specifically to form voids (voids) in the narrow gaps using nekomfortno activated by plasma vapor deposition of the dielectric layer, thereby reducing the effective dielectric constant in the region of the narrow gaps between the conductors. In the narrow gaps of two opposite front deposition of the dielectric layer in the upper part of the gap closed, forming a closed empty space between the parallel conductors. However, with some, a wider width of the gap and at a certain thickness of the dielectric layer, the closing does not occur on the surface of the plate cracks in an empty area with a very unpredictable and difficult terrain surface. In this technology, there were other issues. One of them is the possibility of the formation of the hole created in an empty area of the gap, if the hole for the vertical conductor of resumeware extends beyond the bottom of the guide (it's real, C currently, all topological projects are created with virtually no reserves resumeedge). The next problem is that when applying reconforming dielectric seal blank area in the narrow gap not only in the upper part of the narrow gaps, but also in other parts of the topology of conductors, otherwise when applying planarizing dielectric method HNR solution can penetrate into the blank area and to increase the effective value of the dielectric constant K. In [13] it is noted that for the development of this method in the production of practically does not require new processes and new materials. Inspection of electrical characteristics of parallel conductors with a width of 65 nm air gaps also a width of 65 nm, manufactured using reconforming deposition showed that the breakdown voltage and leakage currents in these conductors are not inferior and superior to the similar characteristics of conductors with gaps filled with standard dielectrics. To eliminate the above problems, there are various ways of making multilevel copper interconnect technology DD, for example, in which the blank areas between closely spaced conductors nekonformnyi applying a dielectric formed after creating horizontal and the slight pressure from the beginning conductors. In particular, in U.S. patent [14] after forming almost a standard way of horizontal and vertical conductors of the DD method is proposed pit dielectric layers, in which these conductors are formed, and then re-create besprovodnoy isolation, since reconforming applying a dielectric layer (9). But this patent does not mention that when nekomfortno applying dielectric empty region with its tip may extend above the surface of the horizontal conductors. For example, figure 10 shows the profile of a blank area in the groove, etched in the silicon wafer obtained in one of the technological modes of applying the dielectric layer nekonformnyi method. It is seen that in this case, after removal method HMP dielectric on the upper horizontal projections between the grooves appears after clicking in an empty area. This method also does not allow to simultaneously solve the problems of improving the quality of the crystal structure of the copper conductors and create voids between the horizontal tightly spaced conductors.

In another patent [15], to avoid etching the insulating dielectric for forming a vertical conductor, also pre-form the horizontal and vertical conductors. For this purpose, the serial plate is correctly applied to all conductive layers, included in the horizontal and vertical conductors, and further sequentially selective etching to form first vertical and then horizontal conductors. This structure nekonformnyi and then fill conformal methods are applied dielectric layers, and the surface of the vertical conductors interlevel dielectric layer is removed and planarized method HMP. However, this method is more suited to the creation of aluminum metallization, but not copper.

Developed another method of manufacturing a copper conductors with voids between them [16]. In the auxiliary layer (for example, from compounds such as norbornene (NB)-based, tetra-cyclododecene (TD)-based, which almost completely destroyed during the heat treatment with the formation of volatile products) mytravelguide groove, which is formed copper conductor standard method single Damascene. The surface is covered with a hard porous film. During the heat treatment auxiliary layer is destroyed and the resulting products through the pores in the surface layer is diffused to the outside, leaving between conductors empty area. This method is currently being dealt with by many researchers. But the need to use new materials and new processes requires long-term tests. On the other hand, scrivani the process of forming air gaps in technological route DD leads to a significant increase of technological operations. It with great difficulty are industrial enterprises.

Literature

1. Patents: Dual Damascen.htm

United States Patent 5635423. Simplified dual damascene process for multi-level metallization and interconnection structure.

2. United States Patent 5635423, Simplified dual damascene process for multilevel metallization and interconnection structure.

3. Laura Peters, - Semiconductor International, 10/1/2007.

4. Lok U.S. Patent No. 7247560 from 24 July 2007

5. Ashlee, Snilow. A method of manufacturing samosobrannoy built-in copper metallization of integrated circuits, the Patent of the Russian Federation (19) RU (ID 2230391 (i3) C2 (51) 7 H01L 21/283 priority from 21.03.2002.

6. S.Lagrangea,*,1, S.H.Brongersmaa, .Judelewicza, A.Saerensb, I.Vervoorta, E.Richarda, R.Palmansa, K.Maexa,c, Self-annealing characterization of electroplated copper films.

7. C.-K.Hu', L.Gignac and R.Rosenberg, - Electromigration of Cu/low dielectric constant interconnects, Appl. Phys. Lett., 84, 4986, (2004).

8. Peter Singer, The Advantages of Capping Copper Wits Cobalt, Semiconductor International, 10/1 2005.

9. Laura Peters, - Exploring Advanced Interconnect Reliability-, Semiconductor International, 7/1/2002.

10. Glenn Aler, 45nm Reliability Issues s Integration Group Novellus Systems.

11. Roev Shaviv, at all,-the Metallization for the 45 nm Node NCAVS Meeting-February 22, 2006, Novellus.

12. Laura Peters,- Are Air Gaps Coming Sooner Than We Think? - Semiconductor International, 7/1/2003.

13. R.Hoofman and others, - Alternatives to low-k nanoporous materials: dielectric air-gap integration, Solid State Technology, august, 2006.

14. United States Patent 006 403 461 B1, - Metod to reduce capacitance between metals lines-Kim-Hyun Tae, Orlando, FL (US); Chok-Kho Liep; Choi-Byoung II, both,. Jun, 11, 2002.

15. Pat US 6 281, 585 B1 - Air dielectric gap in self-aligned via structures, Subhas Bothra, Fremont, CA (US), August 28, 2001.

16. SEONGHO PARK, an others - Air-Gaps for High-Performance On-Chip Interconnect Part II: odeling, Fabrication, and Characterization. Journal of ELECTRONIC MATERIALS, Vol.37, No.10, 2008.

17. Panos C.Andricacos, Copper On-Chip Interconnections A Breakthrough in Electrodeposition to Make Better Chips, The Electrochemical Society Interface, Spring 1999.

Disclosure of inventions

Earlier it was said that the main reason for the differences in the quality of the copper conductors from the expected is high defects of the crystalline structure of the copper conductors, obtained by electrochemical method. We believe that this is facilitated by the very terms in which electrochemical deposition of copper. First, this process is low temperature and flows in aqueous electrolyte in the presence of various additives, in particular organic. In our view, there is another circumstance, namely very cramped conditions and with non-uniform distribution of the mechanical stresses that are present in the deposition of copper in the DD process. For example, when copper deposition in a narrow and deep hole for vertical conductors crystal structure can not be of acceptable quality, since the crystallites must grow from the side walls only to centre of hole, faced with neighboring crystallites. There's just no place for the growth of crystallites. In the trenches a little more space, but even there the normal growth of the crystallites can be only in space is e, equal to half the width of the conductor. Therefore, the growing film is filled unevenly distributed vacancies that immediately after deposition of the layer starts to wander by volume conductors and are condensed in an empty time, increasing its volume. Vacancies from the vertical conductor rush to the border with horizontal conductor having a large mass, and there create time, which potentially can cause breakage of the conductor (figs 3 and 5). The smaller the project the norm, the more acute this problem. Currently, this problem is solved by the introduction of heat treatment after the deposition of the copper, the choice of modes of cleaning the surface of the wafer, investigated the application of an additional protective layer on the surface of copper (Fig.4), and with a certain profile is applied germinal layer. Figure 7[6] shows the possible formation pattern profiles of the copper layers in the grooves and the holes for conductors and expect the consequences. Mode superpipeline can eliminate the formation of voids due to non-uniformity of the deposition rate of copper on the height of the gap, but at the same time to exclude the formation of a defective crystal structure of conductors in full it is not possible. The currently used heat treatment plate after filling copper grooves and vertical holes to a certain extent improves Cree is a metallic structure, but due to the migration of already formed defects (vacancies) crystal structure in places with a high level of mechanical stresses, with high current density and high temperature begin to form micropores. Growing, micropores lead to rupture of the conductors. It follows that the main reason for the insufficient quality of the copper conductors is in high defects of the crystalline structure formed during electrochemical deposition. We believe that the significant improvements of the crystal structure of the copper layers can be achieved if we abandon the traditional process of Double Damascene, which creates a cramped conditions of film growth is copper. In this paper we propose to modify (11) a method of manufacturing a copper conductors, which, according to the authors, in the same geometrical dimensions will allow you to create more favorable conditions for the electrochemical formation of the crystalline structure of the copper conductors. In the proposed method, the electric potential at the electrochemical deposition of copper layer is applied to the seed layer, which is open only at the bottom of the grooves and vertical holes, while the traditional DD seed layer is open to the entire surface of the plate. Therefore, the proposed method is implemented local the e deposition of copper. Over the open surface of the copper can be precipitated also by electrochemical method locally to besiege the protective film. After removal of the auxiliary layer, the protective film can be applied on the entire surface of the plate as electrochemical and vacuum methods.

The presence of such a protective film make it possible to considerably reduce the risk of copper poisoning plate, the copper conductor is fully closed.

The process of etching the barrier layer between the conductors, it is advisable to combine with the standard process of applying a barrier layer with its simultaneous drain connecting an electrical bias to the substrate. It is necessary to regulate the speed ratio of the deposition and etching so that the gaps between the conductors of the conductive film was strawley, and side surfaces of the copper wires was formed conductive barrier film of the minimum required thickness. With appropriate choice of modes, this process will guarantee the removal of the conductive layer between the conductors and the application of a barrier layer on the lateral surface of copper conductors (solved part of the Problem 2). Formed when the barrier film does not reduce the width of the copper conductor. Of course, the process of removing the conducting layer between conductors t is aetsa the most complex operation of the proposed method.

This route is almost turns the DD process. Here first are formed of horizontal and vertical conductors, and then the space between them is filled with a dielectric.

In the itinerary of manufacturing the same level of conductors, including both horizontal and vertical conductors are presented in Fig.11, the original adopted plate with planarizing dielectric layer, where the surface are formed vertical conductors in contact with the underlying level of tungsten or copper. In the traditional process DD first copper conductor can be done using a single Damascene. Thus there is some loss of efficiency of the DD process. In the proposed method, all copper levels conductors are made in the same way. Typically, the dielectric, in which is formed a vertical tungsten conductors on the surface has a dielectric barrier film that prevents diffusion of copper ions. On this surface, consistently applied multi-layer film consisting of a conductive adhesion / barrier layer, such as TiN, TaN, TaN /TA and others, the seed layer, such as Cu, Ni, Co, CoWP, and the auxiliary layer. In the process of applying an auxiliary layer to provide for his absence on the edge of the plate with the purpose provided what I supply to the surface of the seed layer electrical voltage when the electrochemical deposition of copper. In the auxiliary layer, whose thickness is equal to or slightly greater than the thickness (height) made of a conductor, are formed grooves corresponding to the shapes of the horizontal conductors of the current level of metallization. Then the deposition of the copper layer will occur only under the influence of the potential connected to the conductive film under the auxiliary layer. A significant reduction in the route of manufacturing can be achieved using the photoresist as an auxiliary layer. Consider the General case, assuming that the auxiliary film is a photoresist. In the auxiliary layer mytravelguide grooves to the surface of the seed layer and electrochemically locally grooves are filled with copper, and the end surface copper conductors electrochemical same way can be covered with the conductive protective film, such as cobalt, Nickel, alloys, etc. Then repeat the operation 4-5 (11), the second auxiliary film mytravelguide holes, in which locally electrochemically applied vertical copper conductors with a protective film. It is necessary that when the electrochemical deposition of the upper surface of both types of conductors is not performed over the surface of the auxiliary layer.

Further, the follower is about, using as a mask copper conductors with protective layers on the surface, mytravelguide auxiliary, the seed and barrier layers. The process of etching the barrier layer between the conductors, it is advisable to combine with the standard process of applying a barrier layer with its simultaneous drain connecting an electrical bias to the substrate. Thus we have formed is covered with a protective (barrier) layer horizontal copper conductors with protruding above them vertical copper conductors. This process would eliminate the possibility of voids in the copper conductors (solved Problem 4since in this process the copper is grown only in one direction across the thickness (height) of conductors, with almost the same speed for grooves and holes of various sizes (solved Problem 3) until they are full. In this route there is no operation of deposition of barrier and seed layers in globalresource under the trenches holes for vertical conductors (solved Problem 1). This process is not a chemical-mechanical polishing of copper. The process he, in principle, can be used when an invalid exceeding the thickness of the deposited copper, and if it is necessary to smooth the surface microrelief of copper conductors. In the process there is no need for locking dielectric layers with high selectively etching. The proposed method of manufacturing a copper conductors to a certain extent, solves another rather important issue copper DD. It is associated with the known pattern of a sharp increase in bulk resistance of the metal films with decreasing thickness in the region of small thickness. This problem worries now many manufacturers VLSI. First, from Figure 8 is a considerable difference between the average value of the resistivity of copper conductor from the barrier and seed layers on both sides and without barrier layers. In our method, the side walls of the barrier layers are absent and copper conductor increases the width of the grooves and contact holes on one of the seed layer from the bottom up. Secondly, in the traditional process DD copper conductor consists of two independently grown layers. The resistivity of each of these layers, and we can assume dual layer, will be the same and correspondingly higher than for the Explorer of the same width, but grown from a single seed, as in our case (solved Problem 5). Naturally, during the subsequent heat treatments possible recrystallization and consider the effect may be reduced. But it will happen. In the proposed method, the number of vacancies in the crystal structure of the electrochemically grown copper is Lenka will be significantly less therefore, the probability of formation of voids due to the condensation of vacancies is significantly reduced. Moreover, in the proposed version, the formation of columnar crystal structure of copper is already in the process of electrochemical deposition, so as in the direction of growth of the copper film from the bottom of the trench and the contact window for the growth of crystallites restrictions significantly less than standard DD process. In the proposed process, the columnar structure is directed transversely of the conductor and will be a great obstacle for the development of the electromigration process in Windows Explorer. It should also be noted that in the proposed method, the deposition of copper for delivery and removal of reaction products improved as filling of trenches and holes in the supporting layer, while the traditional process DD (see Fig.7) with increasing film thickness on the side walls of the trenches and holes, these conditions worsen. This naturally affects the quality and reproducibility of the crystal structure of copper conductor and its operational reliability. Perhaps this is related to the large variations in the published results in electromigration resistance of copper conductors. It can be assumed that in the proposed method, the effect of using the protective film of the CoWP will be less, because max is e conductors, generated by the proposed method will be less prone to the formation of voids during and after recrystallization processes compulsory annealing, so they will have a higher resistance to electromigration.

Figure 7 illustrates the various schemes profiles deposition that occur when applying a copper layer in the traditional process DD and for comparison in the proposed version. In order to obtain an acceptable quality of filling copper vertical and horizontal conductors, it is necessary to provide the option of superpipeline germinal layer. Such wedge-shaped profile germinal layer at the bottom of the groove is provided during application of the ionized beam deposited material with simultaneous ion etching. To ensure reproducible deposition of such a layer on the bottom and the sides of the well, below the groove for the production of a difficult task. For example, figure 2 shows a snapshot of the profile grooves with an attempt to make this process superpipeline when applying the germinal layer. We believe that for the electrochemical deposition of copper obtained profile is not satisfactory, as this is still the place for the free growth of copper conductor in full is not provided and it will take the form of emptiness.

Described in the previous section the problem of the introduction of air gaps in the proposed route are solved as follows. First, in contrast to the standard DD in the proposed version initially formed horizontal and then vertical conductors. Next is applied conformly dielectric, the thickness of which is sufficient to close the blank area between closely spaced conductors as above, and the ends of the conductors. The resulting complex topography of the surface of the crystal is removed, using a combination of operations of gas-phase deposition of the dielectric in the plasma by applying a high-frequency substrate potential and liquid-phase deposition of the dielectric layer (method HNR). Subsequent removal of the multilayer dielectric from the surface of the plate to the upper ends of the vertical conductors method he here does not lead to the opening of the voids between the conductors, since the presence of above the horizontal wires vertical wires increases the thickness of the dielectric layer above the voids, and the operation of etching the dielectric to create a vertical conductors is absent here. While some features of the structures of conductors, to ensure sealing of the blank area, it is necessary that the bulk of the gaps between the conductors have the same minimum width, the wider the gap should be not less than twice as wide as the minimum width of the gap. If you need to increase the ITU transistor structure from the penetration of copper ions after filling and smoothing the surface of the plate film HNR part of the dielectric film must pit in the plasma, not selective to different types of inter-level dielectric, prior to the formation of a protrusion of the vertical conductor (11-8A) apply dielectric layer from a material having barrier properties with respect to migration of copper ions. Next (Figure 11-9a-10A) method HMP to the upper surface of the vertical conductor dielectric is removed (solved Problem 2).

Technological routes in the drawings for DD and offer presented on figures 1 and 11, respectively. More technological routes DD and two options proposed in this paper are presented in the table.

Lengthening the main version of the route using photoresistive auxiliary layer, due to the fact that to create a partially air gap between the first conductors are the wires themselves with loose clearances. This part of the route, but with power supply for the deposition of copper on top, is used in all the works on creation of partially air insulation. Interest is a variant of the photoresistive auxiliary layer. In this scenario, you receive the opportunity to make a copper metallization with partial air gaps between conductors with Keff~2,2-2,5, even when used as interlevel dielectric layers of silicon dioxide. Instead of silicon dioxide, it is advisable in order to use non-porous dielectric with K~2.8 to 3.0. This will solveProblems 6, 7by doing almost the same number of technological operations, as in the traditional process DD. In addition, if in the traditional DD process is multi-stage operation of the selective etching of multilayer dielectric, the route with the photoresistive auxiliary layer there is no operation of the selective etching using a photoresistive mask. This reduces the range of equipment.

In the proposed method, the increase in the number of technological operations in the embodiment, when the auxiliary layer is impossible to use the photoresist, offset by a significant improvement of the technical characteristics of multilevel metallization.

Application:td align="justify"> Applying a layer of reconforming dielectric
Technological route DD and two options proposed in this work.
Technological route of Cu Dual DamasceneThe proposed Cu technological route (Air gaps)The proposed Cu technological route (Air gaps), the armed forces of the photoresist
123
1Application: Ta/TaN/CuApplication: Ta/TaN/Cu
2Honorable after application ID/BSD/ID/BSDHonorably after the application of Ta/TaN/CuHonorably after the application of TA/ TaN/Cu
3F/l holes for vertical conductorApplication of SUF/l horizontal conductors
4RIT BSD/ID/BSDHonorable after applying sunElectrochemical deposition of Cu (protective layer)
5The removal of the resistF/l grooves for horizontal conductorHonorable after deposition of Cu (protective layer)
6Honorable after RIT SiCN/PCT subsidiaryF/l vertical conductors
IDlayer
7Application: ID/BSDHonorable after chemotherapy
the auxiliary layer
Honorable after deposition of Cu (protective layer)
8F/l grooves for horizontal conductorThe removal of the resistElectrochemical deposition of Cu (protective layer)
9RIT BSD/IDHonorable before deposition of CuHonorable after deposition of Cu (protective layer)
10Honorable after RIT BSD/IDThe formation of horizontal conductors electrochemical deposition of Cu (protective layer)Removing the photoresistive layer
11Application of Ta/TaN/CuHonorable after deposition of Cu (protective layer)Destruction of Ta/TaN/Cu from the intervals between the horizontal conductors
12Honorably after the application of TA/ TaN/CuApplying an auxiliary layer
13Electrochemical deposition of CuHonorable after applying the auxiliary layerHonorable after applying a layer reconforming dielectric
14Honorable after deposition of CuF/l holes for vertical conductorApplying a layer of planarized dielectric method JNR
15HMP si /TaN/TaPCT auxiliary layerPCT dielectric to form a ledge vertical conductors
16Honorable after he Cu/TaN/TaHonorable after chemotherapy auxiliary layerHonorable after chemotherapy dielectric
17The removal of the resistApplication of dielectric barrier
18Forming vertical guides electrochemi the definition deposition of Cu Honorable after application of dielectric barrier
19Honorable after deposition of CuHMP dielectric barrier
20Removing the auxiliary layerHonorable after he dielectric layers
21Honorable after removal of the auxiliary layer
22Destruction of TA/TaN/Cu of the gaps between the conductors ME2
23Honorable after removal of the TA/TaN/Cu
24Applying a layer of reconforming dielectric
25Honorable after applying a layer reconforming dielectric
26Applying a layer of planarized dielectric method JNR
27HMP dielectric prior to the opening of the vertical conductors
28Honorable after he

Conclusion

In the proposed method simultaneously solves both problems: the improvement of the crystalline structure of the copper conductors and the decrease in electric capacity in the system interconnects, which cannot be done using standard [2] and enhanced [14] DD processes.

H01L 21/283

Description

A method of manufacturing a multilevel copper metallization VLSI

Used abbreviations:

BIS - verbally integrated circuit;

t - time between failures (MTBF) due to the electromigration;

With - electric capacity in the system interconnects;

R is the electrical resistance of the conductors;

DD and D - dual and therefore single processes Damascen;

ID - insulating dielectric;

HMP - chemical-mechanical polishing;

K is the dielectric constant;

HNR - chemical deposition from solution in the centrifuge;

OGF - deposition from the gas phase;

OGF NC - deposition of plazmostimulirovannom gas phase nekonformnyi method;

OGF OGF PA - deposition from the gas phase plazmostimulirovannom;

OGF runway - deposition from the gas phase into high-density plasma;

Runway ES - deposition from the gas phase into high-density plasma with an electrical bias to the substrate;

Runway - deposition from the gas phase into high-density plasma.

BSD - barrier locking dielectric.

SU - auxiliary layer.

1. A method of manufacturing a multilevel copper metallization VLSI, including the operation of applying the metallic and dielectric layers, photolithography and selective etching of these layers, the chemical-mechanical polishing of dielectric layers, wherein, with the aim of improving the quality of the copper conductors on a silicon wafer covered with a dielectric, with protruding on the surface of the vertical conductors of the underlying structure is applied to a multilayer conductive film consisting of the adhesive-barrier, seed and auxiliary layer, the supporting layer are formed grooves to the seed layer by electrochemical method, inside the grooves on the exposed areas of the seed layer is grown horizontal copper conductors to fill the grooves on the surface of the plate is applied to the second mobile is ovately layer, in which holes are formed to the surface of the horizontal copper conductors, electrochemical method in the open areas of the horizontal conductors are grown vertical copper conductors to fill the holes for the vertical conductors, then deleted the first and second auxiliary layers, conductive layers are removed between the horizontal copper conductors, next on the plate surface applied dielectric layers smoothing and filling methods and then use the method of chemical-mechanical polishing of dielectric layers above the vertical conductors are removed.

2. The method according to claim 1, characterized in that the auxiliary layer can be used layers of silicon dioxide, organic and organosilicon polymers, photoresist and other dielectrics, in particular multilayer, which is not degraded in the process of electrochemical deposition of copper and can be removed selectively with respect to the formed copper conductors and underlying layers previously formed structure.

3. The method according to claim 1, characterized in that the removal of the conducting layer between the horizontal conductors of the method of applying a barrier layer ionization spray flow and reverse sputtering, but speeding reverse sputtering over the velocity of the th application.

4. The method according to claim 1, characterized in that as the seed layer are films of si, Ni, CoWP.

5. The method according to claim 1, characterized in that during application of each sub-layer provides for his absence on the edge of the plate.

6. The method according to claim 1, characterized in that, to improve crystal structure and microrelief of the surface of the copper conductors, the electrochemical deposition is performed in AC mode, the deposition/etching dominated deposition.

7. The method according to claim 1, characterized in that, for the purpose of protecting the surface of the seed layer from interacting with the auxiliary layer during its formation and removal on the surface of the seed layer, a conductive protective film which is selectively to the seed layer is removed after forming the supporting layer horizontal grooves and vertical holes.

8. The method according to claim 1, characterized in that after electrochemical deposition of copper in the grooves for horizontal conductors and holes for vertical conductors, the surface of copper by electrochemical method is locally covered with a conductive protective film, in particular, allows to reduce the mechanical stress between the copper film and the inter-level insulating film.

9. The method according to claim 3, characterized in that when the COI is whether the photoresist as an auxiliary layer, to improve the sustainability of the photoresistive mask to the process of electrochemical deposition of copper, when the circuit is used adhesive sublayers and methods of ultraviolet and microwave treatments.

10. The method according to claim 1, characterized in that, to reduce the effective value of the dielectric constant of the dielectric isolation system of multilevel metallization creation of voids between closely spaced conductors, after the formation of horizontal and vertical copper conductors on the surface of the first plate is applied to a dielectric layer of plazmostimulirovannom gas phase (OGF NC) mode reconforming deposition.

11. The method according to claim 10, characterized in that, in order to completely seal voids between closely spaced conductors, the main length of the gaps between the horizontal conductors must have the same minimum width, and mode of deposition of dielectric films nekonformnyi method should allow to completely close the empty volume in the gaps between the horizontal conductors minimum size as in the upper part of the gap, and on their backs from top to bottom.

12. The method according to claim 11, characterized in that, in order to fully populate (exclude the possibility of formation on the surface of the slit plate cavities after removal method HMP di is elektricheskogo layer above the vertical conductors), formed after deposition of the dielectric nekonformnyi method of complex profile of the surface relief outside areas with hollow gaps, uses a combination of processes smoothing deposition of dielectric plazmostimulirovannom gas phase by applying an electric bias to the plate and fill method HNR from the liquid phase.

13. The method according to item 12, characterized in that, to prevent possible diffusion of copper ions to the transistor structure after the deposition of the filling dielectric layer portion of the dielectric in the plasma is discharged to education over the surface of the plates of the ledges of vertical conductors, next on the plate is applied to the dielectric barrier film, the thickness of which exceeds the height of the protrusions, and the method of chemical-mechanical polishing the dielectric layer above the vertical conductors is removed.

14. The method according to item 13, characterized in that the dielectric barrier film layers are used type SixCy, SixNy, SixCyNz, where x, y, z indicate the relative content of these elements in the film.

15. The method according to item 12, characterized in that, to avoid formation on the surface of the plate uncontrolled basins, low level on the surface of the fill layer should be above the upper level of the underlying vertical conductor.

16 the Method according to item 12, characterized in that, to avoid formation on the surface of the plate uncontrolled depressions and create conditions for guaranteed fill gaps larger, they should be wider than the gaps of the minimum size of not less than two to four times.



 

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