Method of synchronising clock signals of export module and exciter

FIELD: information technology.

SUBSTANCE: method of synchronising a clock signal of an exciter with a modem frame clock signal in an IBOC radio broadcasting system involves receiving multiple modem frame pulses which represent the onset of modem frames of audio signals and data signals. The time positions of the modem frame pulses are controlled by the modem frame clock signal. An exciter clock signal is generated. Pulses representing the exciter clock signal are counted so as to form a reading representing the error in the time position of each input modem frame pulse, and the exciter clock signal is controlled in response to this reading.

EFFECT: higher synchronisation accuracy.

15 cl, 11 dwg

 

The technical field

The present invention relates to a broadcasting systems, more particularly, to a method and device for synchronizing clock signals in the studios and transmitters.

Background of the invention

System iBiquity Digital Corporation HD RadioTMdesigned to ensure a smooth evolution from the modern analog radio systems with amplitude modulation (AM) and frequency modulation (FM) to a fully digital In-Band On-Channel (IBOC - in range, channel"). The system delivers digital audio services and data transmission to mobile, portable and fixed receivers from territorial transmitters in existing radio medium frequency (MF) and very high frequency (VHF). Broadcasters can continue to transmit AM and FM simultaneously with the new high-quality and more reliable digital signals, providing the opportunity for themselves and their listeners to convert from analog broadcasts to digital broadcasts, while preserving their existing frequency allocations.

The two main components of the system architecture radio are the export module and the pathogen. Typically, the export module is in the Studio at the radio station, and the exciter is located on the side of the transmission, although nothing prevents them to sit together on the side is peredachi. The interface between the module and export agent is unidirectional (usually digital Studio transmission line (STL)), in a typical case using Ethernet for communication lines with the pathogen.

Digital audio signals and data may include a variety of services, including service main program (MPS) and the information service station (SIS). Export module contains the software and hardware required for MPS and SIS. It accepts analog and digital audio through audio, compresses the audio and outputs the compressed audio on the causative agent for unidirectional communication lines of the pathogen.

HD codec (HDC) can be in the Studio in the export module. Export module generates a signal to tract STL, which contains both audio, encoded by HDC and all data services. The analog audio signal is delayed in the export module for the delay of delivery and is displayed at a frequency of 44.1 kHz. It can then be sent on an existing STL or re-discretionality with a frequency of 32 kHz and sent with the thread HDC in multiplexed STL, which can be located within the distribution STL frequency of 300 kHz. Section RF modulation is on the side of the transmitter. This allows the implementation of an effective strip width of the bit stream.

The pathogen can sod is neigh subsystem mechanism of the pathogen (exgine) and the necessary hardware, required for signal type HD RadioTM. All interfacing between the export module and exgine occurs on unidirectional communication lines of the pathogen. Messages of the communication line of the pathogen that is transmitted over lines contain the data of the logical channel that should be subject to modulation by exgine, and appropriate command and control required between the module export and exgine.

Encoded audio and data combined into a single transport duct, and the audio encoding and manipulation are done in the Studio. All passing through the line of the pathogen is based on messages. Each message has a message header and a message body. The header includes at least the identifier, the body, the sequence number bits and the cyclic redundancy check. Message bodies have a specific format. For unidirectional communication lines the body is always the command message, because there is no reverse channel for transmitting the response.

Element exgine module is imported. The import module is implemented in software and manages all the data, including, for example, information about a third party, program-associated data (PAD) or auxiliary channels. It multiplexes the data encoded HDC-information from the digital IBOC accommodation is and delivers this information in a single bit stream in the causative agent.

In some systems, HD RadioTMFM system HDC provides the response at 20 kHz, while the AM-system HDC provides a response to 15 kHz. For audio response at 20 kHz for FM HDC system STL must use a sampling rate of 44.1 kHz or higher, to ensure the transmission of the upper spectra. Since the HDC system requires a master clock signal at a frequency of 44.1 kHz, there is some advantage to using digital STL system, which operates at a frequency of 44.1 kHz, since this will eliminate the need for sampling rate Converter (SRC). However, the STL system, using a sampling frequency of 32 kHz or 48 kHz, are also possible.

The HDC system uses a master clock signal for synchronization of all components on the sampling frequency of 44.1 kHz. Treatment can be used in two configurations: two separate blocks (one for HDC and one for normal transmission) or a single processor for combining dual output, which provides specialized audio processing for both channels.

Consider first the influence of the error of the clock signal for time synchronization between export and exgine. If the clock signals to these devices is the difference between errors of order 10-6(ppm, ppm), the error in one clock pulse will occur on every millionth clock impulseto also can be described thus, the error of time equal to one millionth of the entire elapsed time. For example, an error of 1 ppm leads to a displacement of 3.6 MS per hour or 86,4 MS per day, equivalent to 159 clock pulses or 3810 clock pulses of the clock signal audio frequency 44.1 kHz per hour or day, respectively. If you want access to the sampling frequency of 44.1 kHz, equal to one sampling clock pulse, the clock signal will move the specified limits only 22.7 seconds when the error of the clock signal equal to 1 ppm. It is clear that we need some type of additional synchronization.

The clock signal at a frequency of 10 MHz with GPS synchronization can be used on both side of the module exports in the Studio, and exgine on the side of the transmission to maintain synchronization between the two locations, if they are connected via STL-line. However, in some cases, it may be difficult to receive the GPS signal at the location of the transmitter due to the high RF noise.

There is a need for an alternative method for generating a synchronous clock signal on the transmitter side.

The invention

The invention provides a way to synchronize the clock signal of the pathogen with HR clock signal to the modem in the broadcasting system. The method includes the steps of receiving a variety of personnel impul the owls modem, which represent the beginning of modem frames of audio signals and data signals, and temporary provisions personnel pulses modem managed HR clock signal to the modem, the formation clock signal of the pathogen, to count pulses representing the clock frequency of the exciter to generate reference representing the failure time position of each incoming personnel impulse modem, and a control clock signal of the exciter in response to the reference. Also the claimed device for implementing the method.

In another aspect the invention provides a device for synchronization of a clock signal of the pathogen with the recruiting momentum modem in the broadcasting system. The device has an input for receiving a variety of human impulses modem, which represent the beginning of modem frames of audio signals and data signals, and temporary provisions personnel pulses modem managed HR clock signal, a modem, a voltage controlled oscillator for forming a clock signal of the exciter, a counter for counting pulses representing the clock frequency of the exciter to generate a reference representing the failure time position of each incoming personnel impulse modem, and a loop filter to control a clock signal of the exciter in response to the count.

b> Brief description of drawings

Figure 1 - block diagram, Studio, transmitter and lines of communication between Studio and transmitter for FM radio stations.

Figure 2 - block diagram, Studio, transmitter and lines of communication between Studio and transmitter for AM radio stations.

Figure 3 - functional diagram of the part of the pathogen on the transmitter side.

4 is a block diagram of a circuit synchronization performed in accordance with the invention.

5 is a block diagram of a circuit made in accordance with the invention.

6 is a diagram of the linear model according to the invention.

Figa and 7b is a chart illustrating the time constants of the models.

Fig diagram of a digital model according to the invention.

Fig.9 is a graph of the response of the PLL to the initial displacement of 1 MS and an input of the phase fluctuations with variance 1 MS.

Figure 10 - graph of the response of the PLL to the initial offset of 10 MS and an input of the phase fluctuations with a standard value of 10 MS.

Detailed description of the drawings

Figure 1 shows the functional block diagram of relevant components of the Studio module 10, the transmitting module 12 and lines of communication between Studio and transmitter (STL) 14 made in accordance with the invention. The Studio contains, among other things, the joint operations center (EOC) 16, which includes an import module 128, the export module 20 the synchronizer 22. Module import and export module are connected by a line 24 data export module. The synchronizer 22 includes a GPS receiver, which is connected to the antenna 25. The export module and the synchronizer share many signals, including digital audio services main program (MPS), analog audio services main program (MPS), delayed analog audio services main program (MPS), the control passage, as shown by arrows 26, 28, 30 and 32. Centre AGM accepts multiple audio signals and data from a Studio audio equipment 34, and an auxiliary audio line 36, services auxiliary audio line 38, data services main program at line 40 and audio services to the main program at line 42. Providers 44 data services provide data services in line 46. The transmitter 48 lines of communication between Studio and transmitter (STL) receives the delayed analog audio MPS on line 50 and line data communication module of the pathogen on line 52.

Centre AGM formats of various signals in the modem frames, and the STL transmitter modem transmits frames in the form are arranged in data frames in the transmitting module 12 through STL communication line 14. Modem frames provide a sequence of pulses synchronization agent. The clock signal modem frame is used to manage temporary and the characteristics of the signal. The transmitting module contains STL receiver 54, the causative agent 56, which contains a subsystem exgine 58 and analog exciter 60. The transmitting module receives audio signals and data signals and processes them to broadcast amplifier 62 high power and antenna 64. Data line connection of the exciter served on the subsystem exgine, as shown by the arrow 66. Detained MPS analog audio is fed to the exciter, as shown by the arrow 68. The exciter includes a clock frequency of 10 MHz and a boost Converter.

Figure 2 shows a functional block diagram of relevant components of the Studio module 110, the transmitting module 112 and lines of communication between Studio and transmitter (STL), made in accordance with the invention. The Studio contains, among other things, the centre AGM 116, which includes an import module 118, the export module 120 and the synchronizer 122. Module import and export module are connected by a line 124 data export module. The synchronizer 122 includes a GPS receiver, which is connected with the antenna 125. The export module and the synchronizer share many signals, including digital audio services main program (MPS), analog audio services main program (MPS) and the workaround, as shown by arrows 126, 128 and 130. Centre AGM accepts multiple audio signals and data about the Studio audio equipment 132, including service auxiliary audio line 134, service auxiliary audio line 136, data services basic program line 138 and audio services to the main program at line 140. Providers 142 data services provide data services on line 144. The transmitter 146 lines of communication between Studio and transmitter (STL) receives signals for transmission over line 148 communication module of the pathogen.

Centre AGM formats of various signals in the modem frames, and the STL transmitter modem transmits frames in the form of a sequence of pulses at the transmitting module 112 via STL communication line 114. The clock signal modem frame is used to control the temporal characteristics of the signal. The transmitting module contains STL receiver 150 and the exciter 152, which contains the subsystem exgine 154. The transmitting module receives audio signals and data signals and processes them to broadcast amplifier 156 high power and antenna 158. Data line connection of the exciter served on the subsystem exgine, as shown by the arrow 160. The exciter includes a clock frequency of 10 MHz and a boost Converter.

One solution to the issue of synchronization based on the periodic signal transmission frame synchronization in STL. It is assumed that the STL-clocking is asynchronous to the clock is ignal frequency of 10 MHz transmitter, so STL clock signal can hardly be a candidate for use as a reference clock signal in the subsystem exgine. However, periodic pulses of timing, almost coincident with the frame rate of the modem, can be used to synchronize the clock signal subsystem exgine. Although the signal timing can be synchronized in frequency with the reference clock signal module exports over a long enough period of time, he has temporary fluctuations between peaks, for example 1 MS, due to the asynchronous STL clock signal and clocking software. It is also important to note that fluktuasi noise probably is uncorrelated (white) and can have a greater frequency or the frequency of the beating. If the system phase automatic tuning (PLL) was used in the subsystem exgine for the regeneration of a clock signal frequency of 10 MHz, the phase noise and frequency error were to remain within the technical requirements for these speed error, if activated signal transmission. Tolerance frequency stability of the PLL circuit, the capture range and time constants required for this circuit PLL, set the design parameters for the practical implementation. The unusually high frequency multiplication(approximately 15 million) personnel of the clock signal to the modem up to 10 MHz with fluctuations at the input of the STL lead to unusual design with a very high constant time.

Another factor that must be considered is the accuracy or temporary fluctuations of the information synchronization. Statistical averaging provides a means for estimating the parameter (i.e. the time period of modem frame) from noisy samples, distorted by fluctuations (assuming uncorrelated Gaussian distribution for the analysis to obtain the best unbiased estimates). The statistical variance of the mean estimate is equal to the variance of each sample divided by the number of samples. Or, equivalently, the standard deviation decreases in the number of times determined by the square root of the number of samples in the average. Some type of weighted averaging can be performed using methods PLL.

Figure 3 presents a functional diagram of the part of the agents in figure 1 and 2. Subsystem exgine 180 generates a clock signal having a frequency of about 0,673 Hz in line 182. This clock signal is output from the clocking of the modem frame. The clock signal is provided as the synchronization message on STL-line from the export module and then is decoded to generate a pulse when the synchronization message arrives uridicheski with a frequency of approximately 0,673 Hz. This signal serves as the input signal for the clock generator 184 frequency of 10 MHz. The oscillator frequency 10 MHz generates a clock signal frequency of 10 MHz in line 186 used to control digital boost Converter 188. Digital upconverter receives the data from the fluctuations of the subsystem exgine, as shown by the arrow 190, and generates signal HD Radio™ line 192.

Figure 4 shows the block diagram of the clock generator frequency to 10 MHz in figure 3. The clock signal generator frequency 0,673 Hz is supplied via line 182, for example, in a programmable gate array (FPGA) 194. FPGA processes the clock signal to generate digital control signal line 196. Digital-to-analog Converter 198 generates an analog voltage signal in line 200. Voltage controlled oscillator (VCXO) 202 generates the clock signal frequency 10 MHz in line 186 in response to the analog control voltage. The clock signal frequency of 10 MHz is fed back to the FPGA, as shown by the arrow 204.

The present invention provides a method of synchronizing a clock signal frequency 10 MHz subsystem exgine personnel with a clock signal to the modem from the export module. Figure 5 shows the block diagram of the phase-locked loop (PLL)in accordance with the invention. In the diagram in figure 5 HR pulses of the modem period is approximately 1,486 seconds (the reciprocal of the frequency 0,673 Hz) served by the line 210 to the circuit 212 latches (digital logic chip intermediate storage). Human impulses modem modem signal the beginning of the frame. Primary synchronization signal line 214 is subjected to the logical operation "And" human impulses modem in the logic circuit 216 for generating the reset signal for the counter 218 modulo 216in line 220. Various methods can be used to launch the initial capture synchronization. One prototype uses a command button to start the search for the initial synchronization. Commercial hardware can initialize it from the computer controller, where all transmission parameters are controlled from the graphical user interface (GUI) or other means considered by the manufacturer as convenient. The count from counter 218 is stored in the circuit 212 latches. The count stored in response to the leading edge HR pulse of the modem.

Negative addition to 2 saved reference is determined in block 222 to generate the error signal, which is fed into the loop filter 224 PLL. Determination of additions to 2 is a convenient way of representing both positive and negative errors of the reference clocking (relative to zero error count in the counter/phase detector. This count (add up to 2) provides a measure of the error relative phase or clocking between the input pulses, and d is generirovannykh HR clock signal to the modem subsystem exgine. The PLL operates to reduce this count down to zero. The resolution of the reference is determined by sampling with a clock frequency of 44.1 kHz or about 23 ISS. In a conventional PLL circuits use a binary latch circuit to generate the pulse width of the error for each pulse, which is equal to the difference of times of the pulse input signal and the divided feedback signal. The pulse duration was usually processed in a contour filter of the PLL. Instead, the invention uses a counter (instead of the analog pulse duration) to indicate failure clocking every human impulse modem. This method allows you to reset the counter to its original state, to ensure the PLL circuit within the target phase error (time) and its faster convergence (although this still corresponds to several hours), but otherwise it would have required several days to ensure convergence. This counter is reset to the initial state allows the initial capture synchronization that otherwise would be impossible using traditional method with analog pulse duration. Extremely large, otherwise, the timing synchronization is the motivation for this method on the basis of the counter/phase detector, although the beginning of the capacity capture synchronization is still long (hours instead of days).

Loop filter of the PLL contains a point 226, 228 and 230 summation, limiters 232 and 234, amplifiers 236 and 238 and the elements 240 and 242 feedback. Feedback elements are the elements of a delay on one sample. The output of the loop filter of the PLL is limited, as shown in block 244, and the digital output signal of the limiter is converted into an analog control voltage in line 245 through d / a Converter 248. Voltage controlled oscillator 250 generates the clock signal frequency 10 MHz in line 252 in response to this control voltage.

Variable divider 254 module is used to generate the clock signal frequency 44.1 kHz from the clock signal frequency of 10 MHz. Variable divider 254 module includes counters 256 and 258 and the detector 260 and generates the clock signal frequency is 44.1 kHz in line 262. Frequency 44.1 kHz convenient because it is used for the sampling frequency of the audio signal and is an exact multiple of the value framerates modem. Variable divisor modulo effectively multiplies the frequency of the 10 MHz clock signal by a factor of 441/00000. The clock signal frequency of 10 MHz is injected into a 16-bit counter that cycleroad with the frame rate of the modem 44100/65536 or about 0,673 Hz, resulting in a personnel modem period, approximately 1,486 seconds.

The counter 218 has israsena 16 bits. These 16 bits represent the relative phase difference between the virtual frame counter of the modem and the input reference clocking modem frame. The countdown is fixed on the leading edge of human input clock signal to the modem. This count (add up to 2) provides a measure of the error relative phase or clocking between the input pulses and the regenerated human signal of the modem subsystem exgine. This phase error is then processed by a loop filter of the PLL and DAC to control the instantaneous frequency of voltage-controlled oscillator VCXO. Loop filter the PLL controls the characteristic of the overall PLL.

Voltage controlled oscillator VCXO is defined in such a way as to have a nominal frequency of 10 MHz ± 0,5 ppm. This range of control voltage must allow the VCXO frequency to reach the value of 10 MHz ± 1,0 ppm. In addition, the maximum frequency of VCXO should be limited to the value of 10 MHz ± 1,5 ppm under all conditions. This limitation prevents the increase in frequency above its systemic tolerance for the worst case ±2 ppm.

Assuming you are using 16-bit DAC, although adequate characteristics need only 8 senior (most significant) bits (for example, 8-bit DAC). The full range of the DAC is limited to ±215that should provide in the management of VCXO, at least, until the range of 10 MHz ± 1,0 ppm, but not more than ± 1,5 ppm, to ensure compliance with the system specifications. Restrictions applicable at different points in the path of the digital signal, to prevent numeric overflow or failure to complete.

The PLL in figure 5 generates a clock output signal frequency of 10 MHz in line 252, and the associated frequency divider is used to generate virtual modem period frame duration approximately 1,486 seconds. The PLL is synchronized in phase with the virtual modem periods of the frame to the incoming pulses modem frame, ensuring that the clock signal frequency 10 MHz subsystem exgine coherently associated with incoming modem periods of the frame in the export module.

A special characteristic of the described variants of the implementation is the use of the input counter is reset to its original state at the input of the phase detector. In known circuits PLL binary latch circuit is used to generate the pulse width of the error for each input pulse, which is equal to the difference in time of the pulse input signal and the divided feedback signal. This pulse duration typically must be processed in a contour filter of the PLL. Instead, the invention uses a counter with srasong initial state to ensure that to the PLL was within its target error in phase (time) and reached convergence more quickly (though still within a few hours), otherwise to achieve convergence would require several days.

Stability, damping factor and other performance parameters of the PLL is the most convenient to analyze the mode steady state using the approximation of an ideal linear model of the PLL. The linear model provides the possibility of conventional methods of analysis of theory of servo control to determine appropriate design parameters (in particular, the loop filter PLL) to control the stability and performance in the process. This model, shown in Fig.6, describes the frequency in units of radians per second and the value of the signal in volts.

Figure 6 shows a diagram of the linear model 270 PLL on figure 5. The model includes a phase detector 272, which receives input pulses modem frames, as shown by line 274. The output of the phase detector on line 276 is amplified by the amplifier 278, with the strengthening of the Kd volts/radian. The amplified signal at line 280 is amplified and integrated by the integrator 282, with the rise of “b”, and is amplified by the amplifier 284, having a gain “a”. The integrated signal on line 286 added to the enhanced signal line 288 at point 290 summation. The resulting signal in the line 292 is used to control a voltage controlled oscillator (phase integrator) 294 to generate an output signal at line 296, which is fed back into the phase detector. Contour filtering PLL illustrated in figure 6, may be implemented in software and implemented using a hardware voltage-controlled crystal oscillator (VCXO), managed by the d / a Converter (DAC).

The values of the acceleration “a” and “b” in the contour filter PLL can be determined using conventional methods of theory of servo control, since the inferred values “a” and “b”defined by the full analysis. Then the resulting performance characteristics of the PLL can be described using these estimated values. According to Fig.6 transfer coefficient Kd is the phase detector generates a value (voltage)related to fixed in the latch the counter value of 16 bits. Therefore, Kd is calculated as:

VCXO, which includes a frequency divider that generates a rectangular wave with a period P=1,486 seconds (f0≅0,672 Hz). Changing the value of the DAC on the 215(volts) causes a frequency shift of 1 ppm. Then the gain To the VCXO is calculated as:

or:

Two Kd and Ko can conveniently be expressed as a single parameter K, where:

The transfer function H(s)closed-loop linear model of the PLL can be used to assess performance and stability. Figa and 7b are fundamental diagrams showing a conventional analog circuit loop filter, which serve as the initial design, to facilitate the use of the conventional theory of servo circuits (Laplace transform and so on). Then these patterns can be converted into an equivalent digital version. On figa the circuit 300 having an input 302 and output 304. A resistor R1 connects the input amplifiers 306 and 308. The outputs of the amplifiers are summed at point 310 summation. The capacitor provides feedback to the amplifier 306. Resistor R2 provides feedback to the amplifier 308.

On fig.7b the circuit 320 having an input 322 and the output 324. The input is connected to the first amplifier 326 and point 328 summation. Point 328 summation connected with the second amplifier 330. The output signals of the amplifiers are summed at point 332 summation. Impedance 334 provides feedback to point 328 summation. Time constants of the circuits shown in figa and 7b are of the form:

The transfer function H(s) best describes using the methods of Laplace transform as follows:

where F(s) is the transfer function of the embedded contour filter. Perfect loop filter of the second order has the following transfer function:

The usual analysis of the contour filter describes important characteristics of the PLL in terms of time constants τ1 and τ2. These time constants are related to the properties of the integrator and the components of the gain contour filter implemented with RC components used in an ideal PLL of the second order. The ratio between the constant time and their digital equivalents are illustrated by Piga and 7b.

The resulting transfer function for the PLL can be now rewritten in the form:

In addition, the transfer function can be described by the terminology tracking systems in the form:

where ωn- the natural frequency and ζ is the damping factor of the PLL, and:

Analysis, design and characterization modeling PLL give the desired value of a=512 and b=0,063 (b=1/16). The natural frequency of the PLL can be calculated as:

The resulting attenuation factor is then equal to:

The attenuation coefficient is higher than the typical value (more typically between 0.7 and 1.0 in) to provide an additional margin of a phase for stability. Additional stock is needed to compensate for delays in the implementation of an additional filter for the path with gain “b”. The reserve provides stability and minimizes the overshoot, if implemented To strengthen VCO is somewhat higher than predicted. Although the approximation based on linear models are useful in obtaining some parameters, as described above, in the General case, it is desirable for some additional clarification schemes using methods of digital simulation.

On Fig shows a scheme of the model 350 digital modeling according to the invention. The model includes input 352 connected to a point 354 summation. The summing point connected with contour filter 356 in the form of a filter with an infinite impulse response (IIR)containing amplifiers 358 and 360, the point 362, 364 and 365 summation, limiters 368 and 370 and the impedances 372 and 374. The output signal of the loop filter is limited by the limiter 376. The resulting limited signal line 378 is combined at point 380 summation signal frequency shift in line 382 and a signal about atoi connection with digital phase integrator 384 line 386 for forming a clock signal frequency of 10 MHz in line 388. The clock signal is supplied via the feedback point 354 summation via the amplifier 390.

The performance of the PLL can be further evaluated using a digital model, shown in Fig. The design parameters derived from the linear model used in the digital model. Any analog components, such as VCXO, converted into their equivalent digital version (for example, a digital phase integrator for VCXO). Digital simulation can be used to characterize the effects of nonlinearities and parts that do not easily convert to simplified methods of linear analysis.

One clarification during the transition from the linear model to the digital model is a modification of the tract with the intensification of “b” in the contour filter. A simple increase b was replaced by a single-pole IIR filter with the gain b of the permanent component. This was done for smoothing and peak limiting noisy samples of the phase error. Without this filter, the noise emissions in a typical case would be cut. This cutting would lead to a bias error if the control voltage is nominally is not zero, for example, when capturing synchronization. Filtering reduces the value of the emission and suppresses any offset in the capture process synchronization. However, this filtering is in fact snige is a phase margin due to the extra delay of the IIR filter with respect to the uniform strengthening b. The attenuation factor was initially set higher than in a typical case, to compensate for this expected effect.

This scheme was simulated, and the results for the standard operating conditions are presented in figures 9 and 10. Figure 9 shows a graph of various signals when the entrance was initialized speed error of 1 MS and RMS value of the fluctuations of 1 MS. Figure 10 presents similar results when the value of the initial speed error and the RMS value of the phase noise, installed every 10 MS.

The synchronization error between the incoming pulses modem frame and the regenerated pulses of the PLL can be estimated from observations of the output of the section gain IIR loop filter. The IIR filter has a time constant of about 512 periods of modem frame, or approximately 12.7 minutes, where sampling error efficiently were averaged with an exponentially decaying impulse response. The average value of the filter represents the average error of the input synchronization (±215full scale = 1 period), multiplied by the gain a=512. Since the IIR filter includes an option to limit ±215then the output goes into saturation at the value of the input error ±215/512=±64, which is equal to the output of ±215the IIR filter or CA is approximately 2,9 MS. This value can be used to determine whether the error of the initial capture of sync too large to continue processing, and it would be preferable to re-synchronize the system. Otherwise, the value represents the short-term (12.7 minutes) average phase error. If the fluctuations of the input phase error is small (less than 1 MS), the error steady state after a long period of establishment (approximately 8 hours) must converge to the RMS value of less than 0.1 MS. When the value fluctuations of the input error 10 MS, the resulting fluctuations in the system phase error must be less than 1 MS in RMS value.

The PLL used in the described digital systems audio broadcasts, is unusual because of the very high multiplication factor frequency of about 15 million (0,673 Hz to 10 MHz) with a relatively high phase fluctuations in the input pulses supplied through the communication line STL. The pulse input frequency is generated by decoding the periodic messages from the communication line STL.

The output signal line STL bearing modem periodic frames, converted in sync at the beginning of each accepted modem frame. Input PLL contains a periodic messages, and input the e pulses indicate the beginning of a modem frame. Because the output phase noise is calculated as the input phase noise is multiplied by the multiplication factor (15 million), and filtered transfer function of the circuit, this phase noise is in General very large except if the bandwidth of the circuit will be made very small for the formation of very small output phase noise. In fact, the bandwidth of the circuit is so small that it takes several hours to achieve convergence for phase error (as shown in figures 9 and 10). This requires a highly stable oscillator, and some special design parameters.

The parameters of the PLL are selected to provide the desired operating characteristics for the (unusual) described conditions (phase noise, timing synchronization, the multiplication factor). Using conventional terminology tracking systems natural frequency of the circuit should roughly correspond to 1 hour, and the circuit reaches a supercritical damping with a damping factor of about 1.5 for stability taking into account the margin of error of the transmission coefficient in volts at a frequency of VCXO. The resulting time constants (t1 and t2 described above) are calculated as the nearest convenient values in the function of natural frequency and attenuation factor.

Although the invention is described in note the re various embodiments, specialists in the art should understand that various changes may be made in the described embodiments implement without deviating from the scope of the invention as defined by the claims.

1. How to synchronize the clock signal of the pathogen with HR clock signal to the modem in the broadcasting system, the method comprises the steps
taking multiple human impulses modem, which represent the beginning of modem frames, and temporary provisions personnel pulses modem managed HR clock signal modem
the formation of the clock signal of the pathogen,
count pulses representing the clock frequency of the exciter to generate reference representing the failure time position of each incoming personnel impulse modem
control clock signal of the exciter in response to the reference and reset reference in response to a combination of signal synchronization and personnel pulses modem.

2. The method according to claim 1, additionally containing the commit phase of reference in response to human impulses modem.

3. The method according to claim 1, further containing the step of determining additions to 2 count.

4. The method according to claim 1, in which the pulses representing the clock frequency of the pathogen, are formed using a variable modulo divider.

5. The method according to claim 1, inwhich the frequency of human impulses modem equal 0,673 Hz and the frequency of the clock signal of the pathogen equal to 10 MHz.

6. The device for synchronization of a clock signal of the pathogen with the recruiting momentum modem in a broadcasting system, comprising:
an input for receiving a variety of human impulses modem, which represent the beginning of modem frames, and temporary provisions personnel pulses modem managed HR clock signal modem
voltage controlled oscillator for forming a clock signal of the pathogen,
a counter for counting pulses representing the clock frequency of the exciter to generate a reference representing the failure time position of each incoming personnel impulse modem, loop filter to control a clock signal of the exciter in response to the count, and
input to reset the count in response to a combination of signal synchronization and personnel pulses modem.

7. The device according to claim 6, further containing a latch for latching the count in response to human impulses modem.

8. The device according to claim 6, further containing a scheme for determining additions to 2 count.

9. The device according to claim 6, further containing a variable modulo divider for generating pulses representing the clock frequency of the causative agent.

10. The device according to claim 6, in which the frequency of human impulses modem is
0,673 Hz and the frequency of the clock signal of the pathogen equal to 10 MHz.

11. The device for synchronization of a clock signal of the pathogen with the recruiting momentum modem in a broadcasting system, comprising:
means for receiving a variety of human impulses modem, which represent the beginning of modem frames, and temporary provisions personnel pulses modem managed HR clock signal modem
the means for forming a clock signal of the pathogen,
means for counting pulses representing the clock frequency of the exciter to generate a reference representing the failure time position of each incoming personnel impulse modem
means for controlling a clock signal of the exciter in response to the count and
means for resetting the count in response to a combination of signal synchronization and personnel pulses modem.

12. The device according to claim 11, further containing a means for fixing a reference in response to human impulses modem.

13. The device according to claim 11, further containing a means for determining additions to 2 count.

14. The device according to claim 11, further containing a means for generating pulses representing the clock frequency of the causative agent.

15. The device according to claim 11, in which the frequency of human impulses modem is
0,673 Hz and the frequency of the clock signal of the pathogen equal to 10 MHz.



 

Same patents:

FIELD: information technology.

SUBSTANCE: fewer faults take place when switching from a first input clock signal to a second input clock signal which actuates the circuit of the clock signal multiplexer. The clock signal multiplexer receives the first input clock signal and provides an output clock signal and determines the low phase output level in the output clock signal in response to the low phase input level in the first output clock signal. During a limited period of time, the low phase output level is forcibly maintained independent of the phase level of the first input clock signal. The clock signal multiplexer receives a second input clock signal and determines the low phase input level in the second input clock signal. Switching to provide the output clock signal in response to the second input clock signal is carried out during the low phase input level in the second input clock signal. Further, the output signal of the clock signal multiplexer follows the phase level of the second clock signal.

EFFECT: fewer faults.

31 cl, 8 dwg

FIELD: machine building.

SUBSTANCE: proposed method consists in that accepted input sequence made up of several words coming one after another, each representing modulus digit-by-digit sum, of two noise-resistant cyclic codes, synchronising sequence and numbering sequence are multiplied by verification polynomial of noise-resistant cyclic code and by verification polynomial of numbering sequence to obtain the sum of syndrome of noise-resistant cyclic code and synchronising sequence. Then numbering sequence of accepted noise-resistant cyclic code is extracted and compared with numbering sequences of noise-resistant cyclic codes accepted earlier. The number of agreements of numbering sequences with those accepted earlier in one of F agreement counters. If numbering sequence agrees with numbering sequences accepted earlier, the number in appropriate agreement counter is increase by 1, and, if the number of agreements exceeds that written in appropriate counter of threshold value agreements, code cyclic synchronisation of input sequence is taken to result.

EFFECT: simplified procedure.

4 cl

FIELD: information technologies.

SUBSTANCE: in order to perform time synchronisation with application of spectral estimator, receiver receives estimate of frequency characteristic for symbols of pilot-signal received for each set of frequency subranges used to transfer pilot signal. Receiver performs spectral estimation of frequency characteristics estimates for various sets of subranges to produce measured time of arrival of transferred signal from transmitter. Spectral estimator determines dominant frequency component in estimates of frequency characteristics and produces measured time of arrival on the basis of this dominant frequency component. Time mismatch between measured time of arrival and required time of arrival is calculated, and filtered or non-filtered time mismatch is scaled with permanent or adjustable coefficient of reinforcement. Then time correction is generated on the basis of scaled time mismatch and with application of linear and/or non-linear functions. Time correction is sent to transmitter and is used to adjust time characteristics of transferred signal in transmitter.

EFFECT: improved accuracy of transmitted signal arrival time measurement.

39 cl, 10 dwg

FIELD: physics, communications.

SUBSTANCE: invention relates to multimedia communication over IP and specifically relates to a signal mechanism used in multimedia communications to instruct a device not carryout synchronisation or jitter synchronisation between different multimedia streams. The improved system and method enable a transmitting electronic device to explicitly indicate streams in the transmitted multimedia stream which must not be synchronised or must include a given value of synchronisation jitter. The present invention helps a receiving device understand characteristics of streams. The present invention also enables a receiving device make an informed decision on whether a synchronisation jitter value must be used when synchronising two or more streams. For certain applications, such as unidirectional distribution video data or video PoC, the transmitting device can instruct the receiving device not carryout synchronisation or carryout limited synchronisation to ensure better quality of the multimedia signal.

EFFECT: higher quality of multimedia signal.

36 cl, 4 dwg

FIELD: information technologies.

SUBSTANCE: method is proposed for generation of digital broadcasting transport flow pack, including formation of transport flow pack comprising filling area for insertion of available data of subsidiary reference sequence (SRS), randomisation of pack, which includes filling area, and SRS-data is inserted into filling area of randomised packet, addition of parity for correction of errors in pack, where SRS-data is inserted, pack, in which parity has been added, is alternating, and its trellis coding is carried out. Signal of segment synchronisation and signal of field synchronisation are inserted into pack produced by trellis coding, and modulation is carried out with vestigial sideband (VSB) and RF-transformation of pack for transfer of VSB-modulated and RF-transformed pack.

EFFECT: improved efficiency of reception in receiving system and support of compatibility with existing digital broadcasting transmitting receiving system.

23 cl, 14 dwg

FIELD: information technology.

SUBSTANCE: each of the microcomputers operating in parallel periodically interrupts operation and sends a broadcast packet to the network. Upon receiving the first of broadcast packets sent from different microcomputers, a router sends each microcomputer a synchronisation signal after a delay time τ, from the moment the microcomputer sending the first broadcast packet interrupts operation. Upon arrival of the synchronisation signal, each microcomputer is started and the program continues to operate.

EFFECT: increased reliability of onboard equipment and faster operation of the system.

9 cl, 4 dwg

FIELD: radio engineering.

SUBSTANCE: in binary information transmission and processing method at using pseudonoise signals, which involves operations of coming into synchronism as per a signal and optimum processing of received information, on transmitting side, the front edge of information symbols is attached to i-phase of code structure of pseudonoise signal, and on receiving side after the signal has entered the synchronism there performed is extraction of synchronising pulses attached to i-phase of the code structure of reference pseudonoise signal. At that, binary information processing device includes correlation information highlighting scheme which uses pseudonoise signals, generator of reference pseudonoise signal, a block of n-stages keys, n-stages register, search/tracking device, threshold device, two (n+1) input AND circuits connected to each other.

EFFECT: increasing binary information transmission speed and accuracy.

2 cl, 1 dwg

FIELD: radio engineering.

SUBSTANCE: on transmitting side, the front edge of information symbol and moment of discrete change of signal symbol are attached to i-phase of the period of reference pseudonoise signal, and on receiving side after entering synchronism as per reference pseudonoise signal there performed is extraction of synchronising symbolic pulses attached to i-phase of the period of reference pseudonoise signal, and after discrete change of signal structure is performed - to signal structure distant as per time from the previous synchronising pulse by the period of pseudonoise signal. Information transmission and processing device includes correlation information highlighting scheme, generator of reference pseudonoise signal, n-stages register, two blocks of n-stages keys, search device, threshold device, generator of pseudonoise signal, coincidence circuit by i-phase of reference pseudonoise signal, coincidence circuit by (i-1)-phase of reference pseudonoise signal, two AND circuits, RS-flip-flop, and OR circuit.

EFFECT: providing symbolic synchronisation of input information with high accuracy.

2 cl, 1 dwg

FIELD: physics; communication.

SUBSTANCE: code cycle phasing device relates to systems for transmitting discrete information and can be used for cycle phasing in noise-immune information security systems which use correcting codes, particularly factorable codes. The code cycle phasing device includes a decoder for confirmed words, a number multiplexer, a distributor and a counter unit. Signals on the end of each information unit are generated at the output of a threshold unit.

EFFECT: more reliable information reception in channels with high noise levels.

1 dwg

FIELD: physics, communication.

SUBSTANCE: invention is related to electric communication and is applicable for synchronisation of message sent by sequence of words of block turbo-code, in which component codes are binary cyclic codes of primitive lengths with generator polynomials having common divisor and expanded due to addition of verification for parity, under conditions of parametric uncertainty expressed in absence of any data on coder structure, excluding length of code word. Substance of code cyclic synchronisation method consists in the fact that discrete sequence of code word symbols is accepted with application of discrete information receiver. From received discrete sequence fragment is separated with length that is less than length of code word by one symbol, discrete Fourier Galois transform (DFGT) is carried out for this fragment, and synchronous condition of discrete information receiver is defined by availability of synchronous condition criterion. Criterion of synchronous condition of discrete information receiver is equality to zero of at least one spectral component in spectrum of separated fragment. In case of synchronisation absence prior to its establishment, synchronous condition is searched by means of serial shift by received sequence by one symbol into one and the same side with further separation of new fragment, its DFGT and determination of receiver synchronous condition availability by criterion of synchronous condition. After synchronous condition criterion has been detected, additionally synchronous condition establishment verity is confirmed by availability of phasing verity criterion. For this purpose at least four fragments of the same length are separated, which are serially installed downstream fragment selected at the stage of synchronous condition definition, at that beginning of another fragment is separated from the end of preceding fragment by one symbol of sequence, DFGT of additionally separated fragments is carried out, and phasing verity criterion availability is defined. Criterion for verity of phasing is nonempty crossing of multiple numbers of zero components in received spectra. In case phasing verity criterion is not available, searching of synchronous condition is restored from the moment of synchronous condition criterion detection.

EFFECT: increased number of synchronized codes under conditions of parametric uncertainty.

1 tbl, 1 dwg

FIELD: information technologies.

SUBSTANCE: it is proposed in subsequent linear transport network built on the basis of system of synchronous digital hierarchy transfer, to include subsequently at least two secondary clock-pulse generators (SCPG), separately for each direction of synchronisation signals transfer.

EFFECT: improved quality of communication services by increasing quality of network synchronisation in case of accident of synchronisation signal sources and in case of failure in communication line between network elements.

4 cl, 19 dwg

FIELD: information technology.

SUBSTANCE: method provides generation of a synchronisation signal (Sisynch) from a synthetic audio file, initialisation involving recording parametres which include a list of preferred instruments in the portable communication device; generation, involving analysis of information read from synthetic audio file relating to each instrument for which a track may be extracted in the synthetic audio file, and deciding which extracted track is to be used for generating the synchronisation signal (Sisynch) as a function of said parametres. Parametres include a predetermined frequency threshold, and reading and analysis apparatus can detect frequency of notes in the synthetic audio file for each extracted track.

EFFECT: more accurate synchronisation of a multimedia peripheral device.

8 cl, 3 dwg

FIELD: information technology.

SUBSTANCE: invention relates to POST synchronisation, transferred over DSL, i.e. for VoDSL, DSL, receiving data from a packet transmission network, more specifically ETHERNET. A retransmission unit, such as DSLAM, receives Ethernet packets and retransmits information in them over a digital subscriber line. To retransmit voice data of the received Ethernet packets, a reference clock signal is generated by a synchronising device and transmitted to digital subscriber line modems. The synchronising device comprises an extraction unit for selecting at least one stream of received Ethernet packets, and a unit for generating the clock signal, configured as an adaptive synchronisation unit for generating a reference clock signal in accordance with the arrival time of a packet in the selected stream or streams of packets. The reference clock signal can be transmitted to time referencing units in modems. The extraction unit can analyse reception of Ethernet packets so as to find packet streams from a single user transfer target, each packet in the stream carries information in real time, belonging to a service in real time, and then select one or more streams, which should be used by the adaptive synchronisation generator.

EFFECT: more accurate synchronisation.

14 cl, 19 dwg

FIELD: communications engineering; digital data transfer and synchronization systems; communication network synchronization systems.

SUBSTANCE: proposed method is characterized in that additional links are organized in network and provision is made for transferring sync signals in backup driving network component, output signals of the latter being generated bypassing internal generator from sync signals arriving from last first-priority component nn and from last second-priority component mm. Sync signal arriving from main sync signal supply is conveyed in series over network through backup driving network component bypassing internal generator; variation (reduction) in quality level of sync signals being used is entered in status message of STM-N heading. As a result, using backup path running to main driving component through m components does not cause closed-circuit synchronization. Hence, network will be always synchronized from one sync signal supply upon occurrence of any single accident.

EFFECT: enhanced quality of rendered communication services.

1 cl, 4 dwg

FIELD: mobile communications.

SUBSTANCE: when client terminal moves to area, where it can receive data from multiple nodes B, soft service transfer is realized at client terminal.

EFFECT: client, receiving multimedia broadcast service and moving from existing cell to new cell, receives reliable multimedia broadcast service signal, and it is also possible for client terminal to perform soft realization of data, received from multiple nodes B.

4 cl, 13 dwg

FIELD: radio engineering.

SUBSTANCE: method includes quality estimation of selected messages, while signals, having deviations from determined structure at different levels of their generation are recorded in operative memory buffer device, formatted and through controller are recorded on detachable data carrier on hard drives for later analysis, and modulated signals with deviation of system characteristics of output of second direction of branch for input to operative memory device of buffer are previously subjected to amplification, filtering and analog-digital processing.

EFFECT: higher efficiency, broader functional capabilities.

2 dwg

FIELD: digital communications;

SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.

EFFECT: enlarged functional capabilities.

1 cl, 2 dwg

FIELD: radio engineering; communication systems.

SUBSTANCE: proposed invention can be used in designing national mobile and stationary radio communication systems including effective industrial and technological ones, as well as mass produced radiophone systems. Transmission initiation time is proposed to be recorded for each of channels passing "Channel free" broadband control signal, data on transmission initiation time is to be transferred simultaneously with "Channel free" broadband control signal, and channel kept free for longest time is to be engaged; it is also proposed to connect second control output of mode-of-operation switch in subscriber code-frequency division system for transceiving by broadband signals to switchboard channel selection input.

EFFECT: enhanced reliability of system due to equalizing operating time of system channel-forming components.

2 cl, 4 dwg

FIELD: radiophone groups servicing distant subscribers.

SUBSTANCE: proposed radiophone system has base station, plurality of distant subscriber stations, group of modems, each affording direct digital synthesizing of any frequency identifying frequency channel within serial time spaces, and cluster controller incorporating means for synchronizing modems with base station and used to submit any of modems to support communications between subscriber stations and base station during sequential time intervals.

EFFECT: enhanced quality of voice information.

12 cl, 11 dwg

The invention relates to a radio network

FIELD: radiophone groups servicing distant subscribers.

SUBSTANCE: proposed radiophone system has base station, plurality of distant subscriber stations, group of modems, each affording direct digital synthesizing of any frequency identifying frequency channel within serial time spaces, and cluster controller incorporating means for synchronizing modems with base station and used to submit any of modems to support communications between subscriber stations and base station during sequential time intervals.

EFFECT: enhanced quality of voice information.

12 cl, 11 dwg

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