Pseudo-dual-port memory with synchronisation for each port

FIELD: information technologies.

SUBSTANCE: pseudo-dual-port memory contains the first port, the second port and array of memory cells with six transistors. The first call to memory is initiated by means of anterior front of the first synchronising signal (ACLK) received along the first port. The second call to memory is initiated in response to anterior front of the second synchronising signal (BCLK) received along the second port. If anterior front of the second synchronising signal occurs in the first period of time, than the second call to memory is initiated immediately after completion of the first call to memory by pseudo-dual-port method. If anterior front of the second synchronising signal occurs later in the second period of time, than the second call to memory is delayed till the time after the second anterior front of the first synchronising signal. Duration of the first and second calls to memory does not depend on beats of synchronising signals.

EFFECT: possibility to control ordering of two operations with memory having two separate ports, every of which has its own input synchronising pulse.

37 cl, 16 dwg

 

The technical field to which the invention relates

Disclosed embodiments of, in General, belong to pseudodiaptomus memory.

The LEVEL of TECHNOLOGY

Dual-port memory in a typical embodiment, has two ports and an array of memory cells. The address to the memory array can be carried out simultaneously with both ports on the condition that the memory cells that are accessed the same port are not the same memory cells, reference to which is made with a different port. A common type of memory cell used in such a dual-port memory includes eight field-effect transistors (FET). Four transistors interconnected so as to form two inverter with cross-feedback. The first node D data of the memory cell is a node on the line output of the first inverter and the input line of the second inverter. The second node DN data of the memory cell is a node on the line output of the second inverter and the input line of the first inverter. There are two input transistor connected to the first node D data. The first input transistor is provided so that the first bit B1 can be selectively connected to the first node D data. The second input transistor is provided so that the second bit B2 can be selectively connected to the first node D data. Analogion is, there are two input transistor connected to the second node DN data. The first input transistor is provided so that the line B1N first bit bus can be connected to the second node DN. The second input transistor is provided so that the line B2N second bit bus can be connected to the second node DN. The first bit B1 and the line B1N first bit bus constitute a pair of bit bus and connects to addressable memory cell to the first of the two ports of the dual port memory. The second bit B2 and the line B2N second bit bus constitute a pair of bit bus and connects to addressable memory cells to the second of the two ports of the dual port memory.

Memory cells in the single-port memory in a typical embodiment, include only six transistors. As in the case of a cell with eight transistors, four transistors form the structure of the inverter with cross-feedback. Instead of two pairs of input transistors in a cell with eight transistors, however, the cell with six transistors has only one pair of input transistors. The first input transistor is provided to selectively connect the first node D data inverters with cross-feedback bit to the bus B. the Second input transistor is provided for the absorbed selectively by the pigments is its connection to the second node DN data of inverters cross-feedbacks to the line BN bit bus. The memory cell with six transistors in a typical embodiment, occupies only about half the area of an integrated circuit than a cell with eight transistors, when two types of memory cells are fabricated using the same process.

To take advantage of the memory cell with six transistors smaller, often used storage device, called pseudodiaptomus memory. In one example pseudodementia memory has one memory array, each memory cell array is a memory cell with six transistors, which can be selectively connected to one pair of bit buses (for example, bit bus B and the line BN bit bus). The memory array operates as a single-port memory that at one time is only one reference to memory.

However, pseudodementia memory simulates a dual-port memory in that it has two ports. In one example pseudodementia memory has a scheme, sometimes referred to as a multiplexer with a time delay (TDM). One of the input clock signal is received in pseudodiaptomus memory, and that one of the input clock signal is used to latch the input read address, the input address of record and the value of the input data. The leading edge of the input is sinhronizirajo signal is used to initiate a read operation using the input read address. The read operation is performed. After that, a falling edge of the input clock signal. TDM uses the falling edge of the input clock signal to initiate a write operation. The input address record is used to address the memory array during a write operation, and the data recorded in the memory array are input data value. Although two memory operations are executed in one clock cycle of the input clock signal, two memory operations are actually performed one after the other. However, outside pseudodiaptomus memory, as it seems, pseudodementia memory allows two accesses to the memory array simultaneously or almost simultaneously.

The inventor has found that the amount of time required to perform the first read operation from memory, may not be equal to the amount of time required to perform the second write operation in the memory. The use of traditional TDM approach slows down the total time of memory access, because the relative amount of time available for the two operations, is determined by the time when the leading edge of the stroke is performed, and the time when the rear edge of the stroke is performed. For example, what if the clock signal has a low level during the same time, as high in tact (i.e. the clock signal has a duty cycle 50/50), then the same amount of time should be allowed to run as faster read operations, and a slower write operations. The result is the number of lost time that begins after the read operation is executed, and ends at the trailing edge of the synchronizing signal.

The traditional approach TDM sometimes slows down the total time to access memory not only in situations where the relative amount of time required to perform two memory accesses, does not coincide with the duration of the enable clock signal, but the traditional approach TDM can also cause total time memory access is less than it would be otherwise due to the use of the trailing edge clock signal to initiate the operation. Can be phase jitter when the duration of the enable clock signal, so that the synchronization of the trailing edge clock signal changes from beat to beat. If the schema is optimized for operation in one cycle of the synchronizing signal, it is typical version is not optimized for operation in the other time to synchronise the corresponding signal. Slack time in typical embedded in the scheme so that the scheme of the dual-port memory should work correctly in all modes-time clock signal. This time translates into lost time when certain operating conditions in which to operate is not required lead time. The maximum clock frequency pseudodiaptomus memory, therefore, is set to be smaller than it could be when there is no such time.

Although pseudodementia memory, described above, has a single input clock signal, in some embodiments, the application must be desirable for pseudodiaptomus memory having a first port, which is synchronized with the first input clock signal, and the second port, which is synchronized with the second input clock signal. By providing two separate input clock using only one port can be made largely independent of the use of a different port. By setting these two ports more independent, using pseudodiaptomus memory can be simplified.

In light of the above, requires advanced pseudodementia memory, which does not use both the front and back of the ront of the same input clock signal, to control the ordering of the two memory operations, which also has two separate ports, each port has its own input clock pulse.

The INVENTION

Pseudodementia memory has a first port, second port and the array of memory cells with six transistors. The first port (e.g. port read only) includes the input line of the clock pulse for receiving the first clock signal. The second port (e.g. port write-only) includes the input line of the clock pulse for receiving the second clock signal.

The first memory access (for example, the option to read from the memory array is triggered by leading edge of the first clock signal received on input line sync pulses of the first port. The second memory access (for example, the option to write to the memory array is initiated in response to the leading edge of the second clock signal received on input line sync pulses of the second port. If the leading edge of the second clock signal occurs during the first time period (for example, when the first clock signal goes to a high level or within the next amount of time when the first C is kreisiraadio signal high), the second memory access is initiated almost immediately after the first access to the memory. On the other hand, if the leading edge of the second clock signal occurs within a second period of time (for example, during a subsequent time period when the first clock signal is low), then the initiation of the second memory accesses not immediately after the first access to the memory, but instead is delayed to the second leading edge of the first clock signal. When the second leading edge of the first clock signal initiates a third operation accesses memory through the first port, the second operation circulation memory is carried out after the third operation of the memory access.

One example of a circuit which detects when the leading edge of the second clock signal relative to the first clock signal, and which instructs will delay the initiation of the second memory access, if such delay is applicable, described in the detailed description below. The circuit includes a multiplexer with a time delay, which receives the clock signal reading for the first memory access (read operations) and the clock signal recording for the second memory access operation Zap the si). A multiplexer with a time delay outputs a control signal which determines that the array of memory cells is addressed for the first access to the memory or is addressed to a second memory access. The circuit additionally includes a diagram of the suppressor clock records. If the leading edge of the second clock signal occurs too late (when the first clock signal is low) to the multiplexer with a time delay worked properly when initiating the second operation of the memory access already initiated immediately after the first operation of the memory access, the scheme suppressor clock write suppresses the clock signal recording supplied to the multiplexer with a time delay, thereby delaying the initiation of the second operation of the memory access until the end of the second leading edge of the first clock signal.

In contrast to conventional dual-port memory, where the falling edge of the input clock pulse is used at the time when the second memory access begins, the duration of the first and second memory accesses in a new dual-port memory disclosed in this patent document does not depend on when there is a falling edge clock signal. Instead, the longer the beard the first access to the memory depends on the delay spread (for example, the delay introduced by the scheme of one-time operation). The duration of the second memory access depends on the delay spread (e.g., delay spread through the random logic and/or latency introduced by the scheme of one-time operation). The ratio of the amount of time allocated to the first memory access to the amount of time allocated to the second memory access may be adjusted at the design stage pseudodiaptomus memory by adjusting attitudes and values of the latency distribution. The ratio of the amount of time allocated to the first memory access to the amount of time allocated to the second memory access practically does not depend on time either the first clock signal or second clock signal.

Additional embodiments of hardware, advanced methods and additional details are explained in the detailed description below. This entity does not mean to ask the invention. The invention is defined by the claims.

BRIEF DESCRIPTION of DRAWINGS

Figure 1 - block diagram of a high level pseudodiaptomus storage device 1 in accordance with one embodiment.

Figure 2 is a more detailed the number of memory array 2 of figure 1.

Figure 3 is a more detailed diagram of the eight-column multiplexers/demuxers 3-10 of figure 1.

4 is a more detailed diagram of the latch input address and block multiplexer read/write unit 11 of figure 1.

5 is a more detailed block circuit latches data input block 11 of figure 1.

Figa and 6B is a more detailed diagram for the circuit 12 clock reading circuit 13 clock write circuit 14 of the multiplexer with a time delay and circuit 16 suppressor sync pulses and recording circuit 105 single actuation of figure 1.

7 is a chart of waveforms which illustrate the first scenario (case 1) work pseudodiaptomus storage device 1 of figure 1-6.

Fig - chart of the waveform, which illustrates the second scenario (case 2) work pseudodiaptomus storage device 1 of figure 1-6.

Figure 9 - diagram of the waveform, which illustrates a third scenario (scenario 3) work pseudodiaptomus storage device 1 of figure 1-6.

Figa is a simplified diagram of the waveform of the first scenario (case 1).

Figa is a simplified diagram of the waveform of the second scenario (case 2).

Figa is a simplified diagram of a waveform of the third scenario (scenario 3).

Figure 10 is a simplified diagram of the waveform of the first example, g is e, the ACLK frequency above the frequency of BCLK, but BCLK increases at the same time increases and ACLK.

11 is a simplified diagram of the waveform of the second example, where the frequency of BCLK increases over time, when ACLK is low.

Fig is a simplified diagram of a waveform of the third example, where the frequency of BCLK increases over time, when ACLK has a high level.

DETAILED DESCRIPTION

Figure 1 is a block diagram of a high level pseudodiaptomus storage device 1 in accordance with one embodiment. The storage device 1 includes an array of 2 cells, static random access memory. In the illustrated example, the array 2 includes two rows of memory cells, where each row includes sixteen memory cells. In addition to array-2 storage device 1 includes a set of eight-column multiplexers/demuxers 3-10. Illustrated only the first and eighth column multiplexer/demultiplexer 3 and 10. The memory device 1 also includes a latch address input multiplexer read/write and diagram 11 type "latch" data input circuit 12 clock reading circuit 13 clock write circuit 14 of the multiplexer with a time delay, the circuit 15 one-time alarms and circuit 16 suppressor synchronise the actual operation of the recording pulses. Scheme 16 suppressor clock records include 17 clock suppression and circuit 18 suppressor. Circuit blocks 3-15 is a control scheme that controls the address to the array 2.

Figure 2 is a more detailed diagram of the memory array 2. Each of the memory cells is a memory cell with six transistors. Reference number 19 identifies the memory cell in the upper left corner of the array. Four transistor cell 19 memory are interconnected to form a pair of inverters 20 and 21 with cross-feedback. The first node D data cell 19 memory connected to the line output of the inverter 20 and is connected to the line input of the inverter 21. The second node DN data cell 19 memory connected to the line output of the inverter 21 and is connected to the line input of inverter 20. The first input transistor 22 is provided so that the node D data can be selectively connected to a vertically running bit bus B0. The second input transistor 23 is provided so that the node DN data can be selectively connected to a vertically running bit bus B0N. As illustrated, a pair of bit buses B0 and B0N, B1 and B1N,..., B15 and B15N go through the array in the vertical dimension. For example, a pair of bit buses B0 and B0N go vertically through the left-most column of memory cells. The suffix "N" in this is otachi indicates "no" or the addition signal, with the same signal name without suffix "N". A pair of numeric tire WL0 and WL1 goes through the array in the horizontal direction. Numeric tire WL0 is connected to the gates of the input transistors of different memory cells in the top row of memory cells of the array. Numeric tire WL1 is connected to the gates of the input transistors of different memory cells of the bottom row of the memory cells of the array.

Figure 3 is a more detailed diagram of the eight-column multiplexers/demuxers 3-10 of figure 1. Each column multiplexer/demultiplexer has two pairs of bit lines of the bus. Column multiplexer/demultiplexer 3, for example, has lines that are connected to the first pair of bit buses B0 and B0N, and also has lines that are connected to the second pair of bit buses B1 and B1N. Two pairs of bit buses illustrated, going from top to bottom in the column multiplexer/demultiplexer 3 figure 3.

Each column multiplexer/demultiplexer accepts address RCA0 column read and addition RCA0N. During read operations, one of the two pairs of bit buses is multiplexed by the multiplexer 24 to the differential pair of input lines of the amplifier 25 is read. What kind of two bit pairs of the tires is determined by the values of RCA0 and RCA0N. The amplifier 25 reading includes a latch which latches the value that is output on the output line data column multiplexer/demultiplexer. The latch is transparent when the input signal SENS is low, and the latch is latched when the signal transition from low SENS. Line DOUT[0:7] data output of the storage device 1 is a line output eight-column multiplexers/demuxers 3-10, respectively.

Each column multiplexer/demultiplexer also receives the internal clock signal ICLK. Signal ICLK is a signal for pre-charging, which instructs the pre-charge bit buses, when ICLK is low. Signal ICLK is described below.

Each column multiplexer/demultiplexer takes the address WCA0 column entries and the addition WCA0N. Each column multiplexer/demultiplexer takes the input value of the data stored in the latch, and its addition. The first column multiplexer/demultiplexer 3, for example, takes the input value DIN[0] data stored in the latch, and its addition DINN[0]. During a write operation, the input value DIN[0] and DINN[0] data demultiplexed by the demultiplexer 26 to one of the two pairs of bit buses, which are connected to the column multiplexer/demultiplexer 3. Specific pair of bit buses is determined by the address WCA0 column entries and additions WCA0N. Accordingly, the operation of reading data held in the selected pair of bit buses, through the multiplexer 24, via the amplifier 25 is read and the line DOUT[0] output data column of the multiplexer/demultiplexer 3. During a write operation, data are from lines DIN[0] and DINN[0] input data, via the demultiplexer 26 and the selected pair of bit buses B0 and B0N or B1 and B1N.

Figure 4 is a more detailed diagram of the type "latch" input addresses and host multiplexer read/write unit 11 of figure 1. The diagram in figure 4 latches the incoming case of double-bit address RADR[1:0] reads and latches the incoming case of double-bit address WADR[1:0] record. The diagram in figure 4 displays the values WL1 and WL0 numeric tire, the values of RCA0 and RCA0N address columns are read and the values WCA0 and WCA0N column address entry.

Figure 5 is a more detailed diagram of the host latches data input block 11 of figure 1. As illustrated, has eight identical latches 27-34 input data, which are arranged in parallel so that they zamalchivaut eight-bit input value DATAIN[7:0] data and output eight-bit value DIN[7:0] data stored in the latch, and its addition DINN[7:0]. The clock signal WCLK write is used to latch the incoming input value DATAIN[7:0] data in eight latches input data. Each latch input data is transparent when the clock signal WCLK write has a low level, and protect livesa, when the clock signal WCLK write transitions from a low to a high level. The latch 27 input transistors constituting the bandwidth of the logical element 35, and the inverters 36 and 37 with a reverse cross-links together form a transparent latch 38. The digital value stored in the latch input and the complement of the stored digital values serves on line DIN[0] and DINN[0] data latch input data when the decoding clock signal RWDCLK read/write is supported by a high signal. On the other hand, if the signal RWDCLK has a low level, both of the signal on the lines of DIN[0] and DINN[0] output force becomes high.

6 is a more detailed diagram of the 12 clock reading circuit 13 clock write circuit 14 of the multiplexer with a time delay circuit 15 one-time alarms and circuit 16 suppressor clock entries of figure 1. Scheme on 6 outputs the clock signal RCLK read clock signal WCLK write, the internal clock signal ICLK and the clock signal RWDCLK decode read/write.

Work pseudodiaptomus storage device 1 is described below in connection with schemes waveform in Fig.7-9. Fig.7 is a diagram of waveforms of the first scenario (the case of 1), which front the fronts of the input clock signal ACLK for the first port and the input clock signal BCLK for the second port simultaneously. Fig is a diagram of a waveform of the second scenario (case 2), in which the leading edge of the input clock signal ACLK for the first port precedes the leading edge of the input clock signal BCLK for the second port. Fig.9 is a diagram of a waveform of the third scenario (case 3), in which the leading edge of the input clock signal ACLK for the second port precedes the leading edge of the input clock signal BCLK for the first port. The signal names preceded in Fig.7-9 with an asterisk are externally provided input signals, which are provided in pseudodementia storage device 1.

Original clock signal ICLK has a low level, as illustrated in Fig.7. ICLK is supplied in column multiplexes/demultiplexes 3-10, illustrated in figure 3. When ICLK is low, P-channel transistors 39 to 41 and 42 to 44 in each of the column multiplexers/demuxers are conductive. All pairs of bit buses, therefore, pre-charged, to supply voltage VCC. This pre-charge bit bus is the original and the major mode.

Because the read operation must be performed, a case of double-bit address RADR[1:0] read is placed in two lines 45 and 46 of the input read address pseudodiaptomus memory 1, and the signal CSAN sample when reading is confirmed on line 47 input pseudodiaptomus memory 1. Because the write operation must also be performed, a case of double-bit address WADR[1:0] record is placed in two lines 48 and 49 enter the address of record pseudodiaptomus memory 1, and the signal CSBN sampling when recording is confirmed on line 50 input pseudodiaptomus memory 1. Eight-bit value DATAIN[7:0] data to be written during a write operation, served on eight lines 51-58 input pseudodiaptomus memory 1. Lines 45 and 46 of the input read address, line 59 input clock reading and lines 60-67 output data are the first port (port read only) pseudodiaptomus storage device 1. Lines 48 and 49 enter the address of record, line 68 input clock recording and lines 51-58 input data are the second port (port write-only) pseudodiaptomus storage device 1.

After the information on the lines 45-58 and 68 of the input set for a period of time, the first input clock signal ACLK on line 47 input and the second input clock signal BCLK on line 50 input p is rehadat to a high level simultaneously at time T1 (see Fig.7).

When the first input clock signal ACLK goes to high level, the signal value CSAN sample when reading is latched in the latch circuit 12 RCLK generator on 6. If CSAN has a low level, the voltage at node 69 of the latch falls to the ground and latched by inverters 70-71 with cross-feedback. If CSAN has a high level, the voltage at node 69 must remain in the previous locked state. As the above figure shows a waveform in Fig.7, CSAN has a low level in the previously described example. Digital low signal, therefore, is latched in the node 69. Digital high signal, therefore, is latched in the node 72. The digital value at the node 72 is the value of the clock signal RCLK read. The clock signal RCLK read, therefore, goes to a high level, as illustrated in Fig.7.

Similarly, the clock signal CSBN sampling when recording is latched in the latch generator 13 clock recording 6. If CSBN has a low level, the voltage at node 73 is lowered to the ground and latched by inverters 74-75 with cross-feedback. If CSBN has a high level, the voltage at node 73 remains in the previous locked state. As the above figure shows the form with the persecuted in Fig.7, CSBN has a low level in the previously described example. Digital low signal, therefore, is latched in the node 73, and a digital high signal is latched in the node 76. The digital value at the node 76 is the value of the clock signal WCLK write. The clock signal WCLK write, therefore, goes to a high level, as illustrated in Fig.7.

In the form of a signal 7 and ACLK and BCLK are initially digital low signals. Because ACLK is a low signal, a digital high signal is present at node 200 generator 17 clock suppression by 6. P-channel transistor 201 is therefore non-conducting. Since the BCLK was at a low level, the digital low signal is present at the node 202 of the generator 17 clock suppression by 6. N-channel transistor 203 is therefore non-conducting. Therefore, the node 204 remains locked in order to maintain its previous digital value. When ACLK goes to high level, as illustrated in Fig.7, the inverter 205 confirms digital low signal at node 200, thereby instructing the P-channel transistor 201 to be conductive and instructing the N-channel transistor 206 to be non-conducting. Therefore, the node 204 is improved to a digital high signal. The inverters 27 and 208 with cross-feedbacks locks, so the voltage at node 209 is a digital low signal. The voltage at node 209 is synchronizing signal SCLK suppression. While ACLK is a digital high signal, the latch generator 17 clock suppression is held in this state, regardless of the values of BCLK. Note 7 that the signal SCLK is a digital low signal at time T1 and remains a digital low signal after it.

Latch input address 4 includes a pair of latches 77 and 78 to lock the two values RADR[0] RADR[1] bits of the read address, respectively. Latch 77 and 78 are transparent when the signal RCLK has a low level, and are latched on the leading edge of RCLK. Therefore, the value RADR[0] is latched in the node 79 in the latch 77 in the front edge RCLK. Therefore, the value RADR[1] is latched in the node 80 in the latch 78 on a leading edge of RCLK.

At time T1 on the graph of the waveform at 7 RCLK has a low level and have not yet switched to the high level. Therefore, the latch 77 is transparent. Therefore, RADR[0] is present in the node 79. Because RCLK has a low level, the logical element 81 AND outputs a digital high signal. Logic circuit 82, therefore, confirms that RCA0 and RCA0N have a high level. Since RCA0 and RCA0N have a high level and lead P-channel tra is thestory of demultiplexes the entries in column multiplexers/demuxers in figure 3, demultiplexes write off, and bit bus is not connected to the line input of the amplifiers of the read column multiplexers/demuxers. The demultiplexer account is disabled because the operation that should be executed next is the read operation.

At time T1 on the graph of the waveform at 7 RCLK has a low level, and the latch 78 is transparent. Therefore, RADR[1] is present in the node 80. Because RWDCLK is a digital low signal, as illustrated in Fig.7, snapped the value RADR[1] at node 80 (see figure 4) is provided through the multiplexer 83 to the node 84. Because ICLK has a low level, the logic circuitry 85 blocks the signal at node 84 from the output lines 86 and 87 output numeric tires. Digital low signals are available on lines 86 and 87 output numeric tires. Because the input transistors of the memory cells in figure 4 are N-channel transistors, low signals WL0 and WL1 do not allow comprovante any input transistors in the array 2.

Latch input address 4 additionally includes a second pair of latches 88 and 89 for latching the two values WADR[0] and WADR[1] bits of the address of record, respectively. The latches 88 and 89 are transparent when the signal WCLK has a low level, and are latched on the leading edge of WCLK. Therefore, the value WADR[0] is latched at the node 90 Veselka 88 on a leading edge of WCLK. Therefore, the value WADR[1] is latched in the node 91 in the latch 89 in the front edge WCLK.

At time T1 on the graph of the waveform at 7 WCLK has a low level and have not yet switched to the high level. Therefore, the latch 88 is transparent. Therefore, WADR[0] is present in the node 90. Because WCLK has a low level, the logical element 92 AND outputs a digital high signal. Logic circuit 93, therefore, enforces WCA0 and WCA0N low. Because WCA0 and WCA0N have a high level and lead N-channel transistors demultiplexes in column multiplexers/demuxers in figure 3, demultiplexes off, and bit bus are not connected to the lines of DIN[7:0] and DINN[7:0] input data column multiplexers/demuxers.

At time T1 on the graph of the waveform at 7 WCLK has a low level, and the latch 89 transparent. Therefore, WADR[1] is present in the node 91. Because RWDCLK is a digital low signal, as illustrated in Fig.7, the value in the node 91 is not provided through the multiplexer 83 to the node 84.

At time T1 ICLK is low. Transistors 39-44 in column multiplexers/demuxers 3-10 are therefore conductive. Bit bus each pair of bit buses are connected together and connected to the supply voltage VCC. Therefore, the AK say, bit bus is pre-charged.

Further externally supplied to the first input clock signal ACLK and externally supplied to the second input clock signal BCLK is transitioned to a high level. Two clock signal ACLK and BCLK is transitioned to a high level at the same time.

Before switching signal ACLK signal ACLK was a digital low signal. CSAN was a digital low signal, as indicated by the waveform in Fig.7. The logical element 94 OR NOT Fig.6, therefore, filed a digital high signal to the gate of N-channel transistor 95. When ACLK goes to a high level, a high signal is present on the gate of N-channel transistor 96. Both N-channel transistor 96 and 95, therefore, are conductive during a short period of time up until the digital high signal ACLK will not be propagated through inverters 97 and 98 and the logical element 94 OR NOT to force to make the voltage on the gate of N-channel transistor 95 is low. The voltage at node 69, therefore, instantly reduced to zero through the transistors 96 and 95. The voltage at node 69 thereby latched to a digital low signal, and the voltage at node 72 is latched to a digital high signal. This is illustrated in the form of a signal 7 through a transition from low to high signal RLK.

This happens in the WCLK generator 13. To transition from low to high signal BCLK, CSAB was a digital low signal, as indicated by the waveform in Fig.7. The logical element 99 OR-NOT 6, therefore, filed a digital high signal to the gate of N-channel transistor 100. When BCLK goes to a high level, a high signal is present on the gate of N-channel transistor 101. Both N-channel transistor 101 and 100, therefore, are conductive during a short period of time up until the digital high signal CLK will not be propagated through inverters 102 and 103 and the logical element 99 OR-NOT to be forced to make the voltage on the gate of N-channel transistor 100 is low. The voltage at node 73, therefore, instantly reduced to zero through the transistors 101 and 100. The voltage at node 73 thereby latched to a digital low signal, and the voltage at node 76 is latched to a digital high signal. This is illustrated in the form of a signal 7 through a transition from low to high signal WCLK.

When RCLK goes to high level, the latch 77 and 78 in figure 4 zamalchivaut value RADR[0] RADR[1] read address in the nodes 79 and 80, respectively. This is illustrated in the waveform marked LATCHED AADR[1:0] figure 7 by the vertical dotted line is. Because RCLK has a high level, and RWDCLK has a low level, the logical element 81 AND outputs a digital low signal. Logic circuit 82, therefore, does not specify RCA0 and RCA0N high level as before. The value RADR[0] in the latch node 79 is shown as RCA0, and its addition is output as RCA0N. The address values of the columns read are served in the column multiplexes/demultiplexes 3-10 in preparation for the upcoming reading. It is presented in Fig.7 by the waveform labeled COLUMN TO ADR COL MUX. As can be seen in figure 3, addresses RCA0 and RCA0N columns read instruct the multiplexer 24 reader to choose one of the pairs of bit bus and to connect the selected pair to the line input of the amplifier 25 is read.

When WCLK goes to high level, the latch 88 and 89 at 4 zamalchivaut values WADR[0] and WADR[1] read address in the nodes 90 and 91, respectively. This is illustrated in the waveform marked LATCHED BADR[1:0] 7 by vertical dotted lines. Because the signal RWDCLK is a digital high signal, however, the logical element 92 OR NOT figure 4 continues to output a digital high signal, and a logic circuit 93 continues to push values WCA0 and WCA0N address columns low to their inactive States. Is WADR[1] address, which is recorded in the bonds of the e 91, is blocked from the output in numeric tire WL because RWDCLK is a digital low signal, and selects the upper input line of multiplexer 83.

Returning to Fig.6, the transition from high level to low in the node 69 is fed to the bottom line of the input logic element 104. The logical element 104 AND IS NOT, therefore, finds that the internal clock signal ICLK has a high level. It presents 7 through a transition from low to high signal ICLK. When ICLK goes to high level, the pre-charge bit buses array 2 stops. Transistors 39-44 preliminary charge in figure 3 become non-conducting in preparation for the upcoming read operations.

When ICLK goes to high level, the logic circuit 85 for 4 more explicitly specifies the digital logic level low signal in both numeric tire. Latched in the latch the value of the address RADR[1] read in the node 80, therefore, appears on line 86 numeric output bus WL1. The addition of the values of the read address is output on line 87 numeric output bus WL0. Therefore, a digital high signal is present on one of the numeric tire WL0 and WL1. This is presented in the form of a signal 7 through a transition from a low to a high signal form, marked as WL (ONE OF WL0 AND WL1). As can be seen in f is Data2, a high value in numeric bus instructs all input transistors of all of the associative memory cells of the associated row of sixteen memory cells become conductive. One full shestnadtsatimetrovogo is derived from the array 2 in the eight column multiplexers/demuxers. Eight column multiplexers 3-10 choose one eight-bit value to output on the line of the output data memory based on the values of RCA0 and RCA0N addresses are read. The differential voltage on the selected pairs of bit buses are connected through the column multiplexer/demultiplexer and the line input amplifiers of the read column multiplexers/demuxers. The resulting eight-bit value is displayed on line 60-67 output of the storage device 1. Conclusion eight-bit data values is illustrated in Fig.7. at time T2 in the waveform labeled DOUT[7:0](READ).

Referring to Fig.6, the circuit 105 disposable trigger detects a transition from low to high signal ICLK. After a delay circuit 105 single actuation outputs the high pulse of the RESET signal. This is illustrated in Fig.7. by means of the first high pulse in the waveform labeled RESET. Figure 7 the dashed arrow marked A, represents the delay introduced by the circuit 105 disposable cf is batawana.

Pulsating high RESET signal instructs RCLK go to low level, because the high value of the RESET button present on the top line of the input logic element 106 AND NOT 6. RDWCLK is a digital low signal, so that the digital high signal is also present on the bottom line of the input logic element 106. The logical element 106 AND IS NOT, therefore, outputs a digital low signal, thereby instructing the P-channel transistor 107 to become conductive. The node 69 is translated to a high level, because 69 is connected to VCC through the transistor 107. Signal RCLK at node 72, therefore, goes to a low level. This is illustrated in Fig.7 by the transition from low to high of the signal RCLK. Therefore, it is seen that the multiplexer 14 with a time delay and circuit 105 single actuation function together in order to clear the signal RCLK to a low level at the end of the read operation.

Digital high signal is present on the top line of the input logic element 104 AND IS NOT figure 6. Therefore, ICLK is low. When the voltage at node 86 goes to a high level, the digital high signal is also present on the bottom line of the input logic element 104. The logical element 104 AND IS NOT, therefore, outputs a digital low signal. This is illustrated n the 7 through a transition from low to high of the signal RCLK. Transistors 39-44 preliminary charge in column multiplexers/demuxers, therefore, again made conductive to start the operation of pre-charging for the next write operation.

Before the data output of the storage device can be changed due to the pre-charge signal SENS reading is fed into the latch of the read amplifiers in the column multiplexers/demuxers. The transition from low to high signal SENS causes the snap latches in the column multiplexers/demuxers and preservation of data values that are read, lines 60-67 output of the storage device 1. The scheme is one-time operation (not shown) generates a signal SENS and sends the pulse signal SENS to a high level on the trailing edge of the signal ICLK when RWDCLK has a low level. The latch output is the end of the read operation.

The RCLK transition to the low level when WCLK is a digital high signal, instructs the digital low signal to be present on both input lines of logic element 108 OR NOT the multiplexer 14 with a time delay by 6. The logical element 108, OR IS NOT, therefore, outputs a digital high signal. This signal propagates through the inverters 109 and 110. After vetelino, RWDCLK goes to high level, as illustrated in Fig.7 by the transition from low to high in the waveform marked RWDCLK.

Returning to figure 4, the transition from low to high signal RWDCLK instructs the values of the address-of-record output from the latch input address 4. High RWDCLK instructs a digital low to present on the top line of the input logic element 81. The logical element 81 OR IS NOT, therefore, outputs a digital high signal. This instructs the logic circuit 82 is forced to assign RCA0 and RCA0N digital high value. Forced job RCA0 and RCA0N high instructs the multiplexer 24 is read in the column multiplexers/demuxers in figure 3 do not connect bit bus to the read amplifiers.

Returning to figure 4, high RWDCLK instructs the logical element 92 AND does NOT output a digital high signal. Therefore, logic circuit 93 is no longer blocks the value WADR[0] address entries recorded in the latch 88 from the output WCA0 and WCA0N. Is WADR[0] address of a record column, therefore, is passed through the logic circuit 93 in the demultiplexer 26 entries in the column multiplexer/demultiplexer in figure 3. The input data value DIN[7:0] and DINN[7:0], therefore, transmitted through the demultiplexer record starcoveredparty.piczo.com/demultiplexes the selected set of eight pairs of bit buses. What set of eight pairs is selected, is determined by the values WCA0 and WCA0N. Figure 3 data values are transmitted through the demultiplexer entries in the memory array 2, so that data values can be written in the row of memory cells identified by values WL0 and WL1 address numeric tires.

Returning to Fig.6, the transition from low to high RWDCLK continues to spread through the inverters 111 and 112 and the top line of the input logic element 113. Since SCLK is a digital low signal, the inverter 210 in scheme 18 suppression outputs a digital high signal on the bottom line of the input logic element 211. Because WCLK is a digital high signal, the logical element 211 AND outputs a digital low signal, and the inverter 212 confirms that the signal SWCLK has a high level. Accordingly, when SCLK is low, the clock pulse WCLK write strobiles through the circuit 18 suppression and displayed as SWCLK.

Because the digital high signal SWCLK is present on the bottom line of the input logic element 113 AND the multiplexer 14 with a time delay, the transition from low to high on the top line of the input logic element 113 AND instructs the logical element 113 AND does NOT output a digital low signal which is inverted by the inv the Torah 114. Digital high signal, therefore, is confirmed on the upper line of the input logic element 115. Digital high signal is already present on the bottom line of the input logic element 115 AND IS NOT due to a low RESET signal, instructing the logical element 116 schema generator 13 WCLK output a digital high signal. Therefore, the logical element 115 AND outputs a digital low signal, thereby instructing the logical element 104 AND IS NOT to confirm ICLK at a high level. This delay in distribution from front RWDCLK to the leading edge of ICLK shown in Fig.7 by the dashed arrow labeled B. the leading edge of ICLK signal completes a preliminary charge of write operations.

Returning to figure 4, the leading edge of ICLK is supplied to a logic circuit 85. Therefore, logic circuit 85 is no longer specifies WL0 and WL1 at a low level, and instead allows the output values WADR[1] address entries in the node 84 on line 86 numeric output bus WL1. The value of the address entry that is locked in the node 91, is multiplexed in the node 84 due to the fact that the value RWDCLK is a digital high signal during the write operation. The result is that the value WADR[1] address record appears on line 86 o WL1, and its addition is displayed on line 87 output WL0. This is illustrated in Phi is .7 by navigating to a signal form, marked WL (ONE OF WL0 AND WL1).

Values WADR[0] and WADR[1] address-of-record, therefore, are used to address the memory array 2 during write operations. It is presented on Fig.7 with a label WCA, which is displayed in the waveform labeled COLUMN TO ADR COL MUX. Data in eight addressable memory cells can switch at time T3, as illustrated in Fig.7.

Returning to Fig.6, the transition from low to high ICLK re-detected through a scheme 105 one-time operation. After a delay, represented 7 by the dashed arrow labeled C, the circuit 105 single actuation outputs the high pulse of the RESET signal. High pulse RESET signal is confirmed on the upper line of the input logic element 116. Because RWDCLK has a high level, there are digital high signals on both input lines of logic element 116. The logical element 116 AND leads digital low signal to the gate of P-channel transistor 117, thereby Sasakawa digital high signal at node 73 scheme 13 WCLK generator. Signal WCLK node 76, therefore, goes to a low level. This is illustrated in Fig.7 through the transition from high to low of the signal WCLK. The multiplexer 14 with a time delay and circuit 105 single actuation, SL is therefore cause the reset signal WCLK to a low level at the end of the write operation.

The transition of WCLK to the low level instructs the logical element 221 AND IS NOT in the schema 18 canceller output a digital high signal. The inverter 212, therefore, forced transfers SWCLK to the low level. WCLK, therefore, strobiles through the circuit 18 suppressor, because the signal SCLK suppression is at a low level.

The transition SWCLK to low level instructs the logical element 113 AND the multiplexer 14 with a time delay to output a digital high signal. The inverter 114 outputs a digital low signal, thereby instructing the logical element 115 AND does NOT output a digital high signal. Because RCLK is a digital low signal, the voltage at node 69 scheme 12 RCLK generator is a digital high signal. There are digital high signals on both input lines of logic element 104 AND, thereby instructing the logical element 104 AND IS NOT to confirm ICLK at a low level. This is illustrated in Fig.7. by the second transition from the high level to the low signal RCLK.

The transition SWCLK to low also instructs a digital high signal to appear on the bottom line of the input logic element 108 OR NOT 6. The logical element 108 OR does NOT output a digital low signal, which distributed trahaetsya through the inverters 109 and 110, thereby instructing RWDCLK go to the low level at the end of the write operation. This is illustrated in Fig.7 through the transition from high to low level waveform marked RWDCLK. At this point initiated a preliminary charge-bit bus of the memory array 2 for subsequent operation of the memory access.

Consequently, we discovered that pseudodementia storage device 1 performs a read operation followed by a write operation. The completion of the read operations and the beginning of the write operation does not depend on the trailing edge of the input clock signal. Instead, the asynchronous delay spread through the logical schema and the schema of the single trigger is used to synchronize the control signals required to perform the first write operation, pre-charge bit memory bus and to perform the second write operation. Periods of time delay A, delay B and C delay can be increased or decreased during the design of the storage device to change the relative time interval, which is available for read operations, in comparison with the write operation.

Figa is a simplified block diagram of waveforms for case 1. Rear front ACLK and BCLK is the same. SCLK remains low and Niko is Yes not goes to a high level. Scheme 18 suppressor in Fig.6, therefore, always passes the value WCLK to be the value SWCLK. The signal SWCLK fed into the multiplexer 14 with a time delay instead of WCLK. The multiplexer 14 with a time delay, therefore, takes RCLK and SWCLK (which have the same synchronization as WCLK) and generates a signal RWDCLK with a time delay, in order to perform a read operation after a write operation.

In the above scenario should be executed and the read operation and the write operation. In the script, which should only be performed by a read operation, RCLK must be clicks into place at a high level, RWDCLK should be forcibly transferred to a low level for a read operation, the circuit 105 single operation must then be reset RCLK is low, but the CLK should not be clicks into place at a high level. Therefore, RWDCLK should not be forcibly transferred to a high level at the end of the read operations, and should not be second read operations.

Similarly, in scenarios in which only the write operation should be performed, WCLK must be clicks into place at a high level, but RCLK should not be clicks into place at a high level. Therefore, RWDCLK should be forcibly transferred at a high level for a write operation, the circuit 105 disposable after this operation must Sposi the WCLK to a low level upon completion of the read operations, but there should be a second memory operations.

Consider a situation in which WCLK clicks into place at a high level, when RCLK is not yet clicks into place at a high level. The multiplexer 14 with a time delay must confirm the high level RWDCLK for a write operation, the write operation must be initiated as described above, in the mode in which the write operation should be performed, but the read operation should not be performed. If RCLK then clicks into place at a high level (as in case 3) in the case of read attempts from the first port, the logical element 108 in the multiplexer 14 with a time delay to output a digital low signal, low signal must propagate through inverters 109 and 110, and RWDCLK should be confirmed as low. Confirmation of low level RWDCLK until the completion of the write operation, however, may cause incorrect operation pseudodiaptomus storage device. The generator 17 clock suppression and circuit 18 suppressor prevent such a situation by suppressing confirmation of a high level WCLK, as it appears in the multiplexer 14 with a time delay (WCLK is presented to the multiplexer 14 with a time delay as SWCLK), as long as the signal RCLK is not switched to the high level. Suppression of WCLK thus prevent reset incorrect operation, which otherwise would have happened, if RCLK was confirmed soon after initiated the write operation.

Fig is a diagram of waveforms illustrating the operation pseudodiaptomus storage device 1 in the case 2. In case 2, the first input clock signal ACLK, served in the first memory port, confirmed by the high level again at time T1A. Values CSAN and AADR[1:0], therefore, snapped into memory shortly after the time T1A. The second input clock signal BCLK, which is attached to the second memory port, confirmed some time after time T1B. Values CSBN and BADR[1:0], DATAIN[7:0], therefore, snapped into memory shortly after the time T1B.

Because the read operation must be performed before a write operation, the early increase ACLK instructs the confirmation of RCLK. RCLK, in turn, initiates a read operation to the leading edge BCLK. When the read operation is completed, as determined by A delay distribution and the subsequent trailing edge RCLK, the multiplexer 14 with a time delay by 6 confirms RWDCLK to initiate a write operation. The clock signal WCLK account, which is confirmed at this time, strobiles through the circuit 18 suppressor and supplied to the multiplexer 14 with a time delay is Oh in the form SWCLK. When the read operation is completed, the multiplexer 14 with a time delay, therefore, initiates a write operation.

Figa is a simplified block diagram of waveforms for case 2. The leading edge of ACLK precedes the leading edge of BCLK. SCLK remains at a low level and never goes to a high level. Scheme 18 suppressor in Fig.6, therefore, did not suppress WCLK. WCLK strobiles through the circuit 18 suppressor and supplied to the multiplexer 14 with a time delay as SWCLK. Because the signal SWCLK record is present in the multiplexer 14 with a time delay in the time when the read operation is performed, the multiplexer 14 with a time delay initiates a write operation in the same way as in case 1.

Fig.9 is a diagram of waveforms illustrating the operation pseudodiaptomus storage device 1 in case 3. In case 3, the second input clock signal BCLK, which is supplied to the second memory port, the first confirmed at time T1A. Values CSBN and BADR[1:0], DATAIN[7:0] for write operations, therefore, are latched in the memory shortly after the time T1B. The first input clock signal ACLK, which is fed to the first port memory, confirmed some time after time T1A. Values CSAN and AADR[1:0] for read operations, therefore, are latched in the Amati shortly after the time T1A.

Because the write operation should be performed after a read operation, the early increase BCLK cannot be resolved in order to confirm the high level SWCLK, so that the write operation was initiated. Clock SCLK pulse suppression, therefore, confirmed at a high level during the initial period (approximately between the time T1B and time T1A) up until the clock ACLK pulse reading will not go to a high level. During this initial period SCLK suppresses clock pulse recording, which is served in the multiplexer 14 with a time delay (clock WCLK pulse recording is supplied to the multiplexer 14 with a time delay as SWCLK). Suppression SWCLK during this initial period prevents initiation through multiplexer 14 with a time delay write operations to read operations.

The formation of a clock pulse SCLK suppression is illustrated in connection with 6. ACLK at this time has a low level. Therefore, the inverter 205 outputs a digital high signal to the node 200. P-channel transistor 201 is therefore non-conductive and N-channel transistor 206 is energized. BCLK is initially low, and then goes to a high level. Therefore, the inverters 213-215 original output digital the new high signal to the gate of N-channel transistor 216. Therefore, the transistor 216 is initially conducting, but the node 204 is not connected to the earth, because the N-channel transistor 203 is non-conducting. When BCLK goes to high level, the voltage at node 202 goes to high level, thereby making N-channel transistor 203 conductive. However, for high signal at the node 202 need time to propagate through inverters 213-215, to force the transfer gate N-channel transistor 216 to low level to turn off transistor 216. Consequently, within a short period of time after the leading edge BCLK all three N-channel step-down transistor 203, 216 and 206 are conductive, and the node 204 at the moment is connected to the ground potential. Instant connection to the ground potential latches digital low signal at node 204. Clock SCLK pulse suppression in the node 209, therefore, confirmed at a high level. This is illustrated in figures 9 through the leading edge of the waveform marked SCLK.

Even if WCLK rises for a short time after time T1B, the high value of the clock pulse SCLK suppression suppresses the clock signal SWCLK records supplied to the multiplexer 14 with a time delay. This state lasts as long as the input synchronize the second signal ACLK port reading not go to a high level. When ACLK goes to high level, the inverter 205 outputs a digital low signal at node 200. P-channel Overdrive transistor 201 becomes conductive, and the node 204 is latched and maintained at a high level. Therefore, SCLK is latched and maintained at a low level, thereby completing the initial period of time when the clock pulse SCLK suppression is confirmed. Front fronts RCLK and SWCLK, therefore, are submitted to the multiplexer 14 with a time delay almost simultaneously.

Figa is a simplified block diagram of waveforms for the case 3. The leading edge of ACLK precedes the leading edge of ACLK. The leading edge of BCLK when ACLK is low, instructs the latch in the generator 17 clock suppression by 6 to latch the digital low signal at the node 204, thereby Sasakawa clock signal SCLK suppression at a high level. Scheme 18 suppressor in Fig.6, therefore, suppresses SWCLK and supports SWCLK at a low level during the time when SCLK is high. When ACLK goes to high level, the digital high signal is latched in the node 204 of the generator 17 clock pulses, thereby Sasakawa SCLK low. So SWCLK is no longer supported at a low level through a scheme 18 suppressor. The value of the sync pulse is Lisa WCLK write is the value SWCLK for the remaining operations read and write. The multiplexer 14 with a time delay and circuit 105 single actuation trigger the read operation and the write operation, as in cases 1 and 2.

Figure 10 is a simplified block diagram of waveforms illustrating operation pseudodiaptomus memory 1 when ACLK has a higher frequency than the BCLK. The first leading edge of ACLK occurs at the same time as the first leading edge of BCLK. This is the situation in Fig.7. The first write operation after the first read operations. In the case in figure 10 there is no front BCLK during the time of the second leading edge ACLK. The second leading edge of ACLK figure 10, therefore, leads to the second reading. In the third example the leading edge of ACLK occurs at the same time as the second leading edge of BCLK. This is the situation in Fig.7. The second write operation follows after the third read operations.

11 is a simplified block diagram of waveforms illustrating operation pseudodiaptomus memory 1 when the leading edge of BCLK occurs for the first time in the course of the low level of ACLK. The leading edge of BCLK instructs confirmation SCLK, thereby suppressing SWCLK to the third front ACLK. Therefore, the write operation is delayed until after the third read operations.

Fig is a simplified block diagram of waveforms illustrating operation pseudodiaptomus memory in case when the leading edge of BCLK occurs more than three gate delay to the trailing edge ACLK. BCLK, therefore, increases over time, when ACLK has a high level. In this case, ACLK has a high level and holds the node 204 high to VCC, when the leading edge of BCLK tries to instantly lower the node 204 to the ground. Since N-channel transistor 206 is non-conducting, the node 204 is not reduced to the ground, and SCLK is not latched at a high level. So SWCLK not suppressed during the initial period. Therefore, SWCLK illustrated the challenge to high level soon after BCLK goes to a high level. It instructs a write operation to be carried out immediately after the second reading. The second read operation in the form of a signal Fig is a read operation, due to the second cutting edge of ACLK.

Periods of time delay A, delay B and C delay can be increased or decreased during the design of the storage device to change the relative proportion of time that is available for read operations, in comparison with the write operation. The completion of the read operations can overlap the beginning of the write operation time. In some implementations, the storage device read operations can be provided more times is, than write operations. In other implementations, the write operation may be given more time than read operations. Problems, associative associated with initiating a write operation using the trailing edge of the external clock signal, where the back the front has an undesirable large amount of jitter, are excluded, because the falling edge of the externally supplied clock signal is not used in order to complete the first read operation and/or to start the second write operation.

Although certain specific embodiments of the above-described illustrative purposes, the present invention is not limited to them. The management scheme pseudodiaptomus memory can be used in the variants of implementation, where the first operation of the memory access is a write operation and the second operation of the memory access is a read operation, where the first operation of the memory access is a write operation and the second operation of the memory access is a write operation, and where the first operation of the memory access is a read operation and the second operation of the memory access is a read operation. Therefore, various modifications, adaptations and combinations of various features described specific embodiments can be used n the practice without deviation from the scope of the invention, set forth in the claims.

1. Pseudodementia memory containing:
an array of memory cells, each memory cell of the array represents a memory cell with six transistors;
the first port containing a first set of input lines and address lines of the input sync pulses, with the first transition from low to high of the first input clock signal on input line sync pulses of the first port causes the latching of addresses in the first set of input lines of the address in pseudodiaptomus memory and initiates the first call to a memory array of memory cells; and
the second port containing a second set of lines of the address input and the line input sync pulses, with:
in the first case: the transition from low to high of the second input clock signal on input line sync pulses of the second port during the first time period causes the latching of addresses in the second set of lines, enter the address in pseudodiaptomus memory and causes the initiation of the second memory access of the array of memory cells after the first access to the memory and to the second transition from low to high of the first input clock signal, and
in the second case: the transition from low to high, the second the output clock signal on input line sync pulses of the second port during a second period of time causes a delay of the second memory access of the array of memory cells until the time after the second transition from low to high of the first input clock signal, and the end of the first period of time coincides with the beginning of the second period of time, and thus the second memory access is delayed by the delay introduced by element time delay.

2. Pseudodementia memory according to claim 1, in which the first input clock signal goes to a high level at the first transition from low to high, then remains at a high level during the first time interval, then goes to low level, and then remains at a low level during the second time interval, and then goes to a high level when the second transition from low to high of the first input clock signal, and the first transition from low to high of the first input clock signal coincides with the beginning of the first time period and the first period of time coincides with the first a time interval.

3. Pseudodementia memory according to claim 1, in which the first input clock signal has a duty cycle, and in which the first memory access has a certain length and a certain length of the first memory access does not depend on the duty cycle of the first input synchronisierung the signal.

4. Pseudodementia memory according to claim 1, in which the first port is a port for reading and the second port is a port write-only.

5. Pseudodementia memory according to claim 1, in which in the first case, a memory access is initiated immediately after the first access to memory.

6. Pseudodementia memory according to claim 1, in which the second memory access includes the initial period of pre-charge and the subsequent period during which the information is written in the memory cell array.

7. Pseudodementia memory according to claim 1, additionally containing:
a multiplexer with a time delay, which is the input line of the clock signal reading line input suppressed clock signal recording and line output control signal, and the output line of the control signal of the multiplexer with a time delay transmits the control signal, which determines addressed if the array of memory cells for the first access to the memory or the second memory access;
the clock read that has a line input and line output, the first input clock signal present on the input line, the output line is connected to the input line, a clock signal reading multiplex the RA with a time delay;
clock recording, which has a line input and line output and the second input clock signal is present on input line; and
scheme suppressor clock entries, with the first line of input, a second line input, a third line input and line output, the first input clock signal is present on the first line of input, the second input clock signal is present on the second input line, the third line of input is connected to the line output clock recording, the output line is connected to the line input of suppressed clock signal multiplexer with a time delay, the circuit suppressor clock record or transmits a signal on the third input line to the output line, or suppresses the signal on the third input line from the transmission to the output line, and in this scheme suppressor clock inhibit signal on the third input line from the transmission to the output line in the second case, during the period of time beginning with the transition from low to high of the second input clock signal to the second transition from low to high of the first input clock signal.

8. Pseudodementia memory according to claim 1, in which the element of temporary detention is key contains a multiplexer with a time delay.

9. Pseudodementia memory according to claim 1, in which the first period of time starts at the moment of transition from low to high of the first input clock signal, and in which the first period of time ends at the moment of transition from the high level to the low of the first input clock signal.

10. Pseudodementia memory according to claim 1, in which the second time period begins before the first transition from low to high of the first input clock signal.

11. How to access pseudodiaptomus memory containing phases in which:
take the first clock signal input line, a clock signal of the first port pseudodiaptomus memory, with the first input clock signal goes to a high level at the first transition from low to high, then remains at a high level during the first time interval, then goes to low level when moving from high to low level, and then remains at a low level during the second time interval and then goes to a high level when the second transition from low to high;
take the second clock signal input line, a clock signal of the second port pseudodiaptomus memory;
perform the first operation handling the memory in response to the first transition from low to high of the first clock signal, when this first operation of the memory is initialized during the first time interval, and the first operation of the memory access is a reference to an array of cells pseudodiaptomus memory, each of the memory cells is a memory cell with six transistors, and the first operation of the memory has a first duration, the first duration is not dependent on the first interval of time; and
perform the second operation of the memory access in response to a transition from low to high of the second clock signal, while the second operation of the memory access is a reference to an array of cells pseudodiaptomus memory, and the second operation of the memory is initialized immediately after the completion of the first operation of the memory access, if the transition from low to high of the second clock signal is in the first time period and the second operation of the memory is not initialized immediately after the first access to the memory, but instead is initialized after the second transition from low to high of the first clock signal, if the transition from low to high of the second clock signal is in the second time period and the second operation circulation the memory trigger after a delay, insertion element time delay at the end of the first period of time coincides with the beginning of the second period of time.

12. The method according to claim 11, in which the first period of time is the same as the first time interval, when the first clock signal remains at a high level, and in which the second time period is the same as the second time interval.

13. The method according to claim 11, in which the first port is a port for reading and the second port is a port write-only.

14. The method according to claim 11, in which the transition from the high level to the low of the first clock signal is not used to control when the first operation of the memory access is completed, and in which the transition from the high level to the low of the first clock signal is not used to control when the second operation of the memory access is initiated.

15. The method according to claim 11, in which the second operation of the memory access includes the initial period of pre-charge and the subsequent period during which the information is written in the memory cell array.

16. The method according to claim 11, further comprising stages, which are:
install the latch in the clock reading at the first transition from low to high Pervov the clock signal, moreover, the latch outputs the clock signal readout;
install the latch in the clock records the transition from low to high of the second clock signal, and the latch outputs the clock signal recording;
pass the clock signal to the write-through scheme agent, the scheme agent displays the suppressed clock signal recording, with suppressed clock signal recording is identical to the clock signal recording, if the input clock signal suppression is not confirmed, and thus suppressed clock signal recording is suppressed, if the input clock signal suppression is confirmed;
install the latch in the clock suppression, when the first clock signal has a high level, and resets the latch in the clock suppression, if the second clock signal goes to a high level when the first clock signal has a low level, the clock suppression outputs the input clock signal suppression in the suppression scheme, the input clock signal suppression is high, if the latch is in the generator synchronizing them is alsow suppression installed, moreover, the input clock signal suppression is low, if the latch is in the clock suppress reset;
take the clock signal reading and suppressed clock signal recording multiplexer with a time delay, and a multiplexer with a time delay outputs a control signal which determines addressed if the array of memory cells to the first operation of the memory access or is addressed to a second operation of the memory access.

17. The method according to item 16, further comprising stages, which are:
output signal for pre-charging of the multiplexer with a time delay, the signal for pre-charging has a first transition during the first operation of the memory access signal for pre-charging has a second passage in a second operation of the memory access;
use the diagram single operation to form a first reset pulse in response to the first transition of the signal for pre-charging, the first reset pulse clears the latch to the clock reading; and
use the map one-time operation to generate the second reset pulse in response to a second transition signal for pre-charging, the second reset pulse, ocide the latch in the clock entry.

18. The method according to claim 11, in which the element time delay provides the multiplexer with a time delay.

19. The method according to claim 11, in which the first time period begins at the time of the first transition from low to high of the first clock signal, and in which the first period of time ends at the moment of transition from the high level to the low of the first clock signal.

20. The method according to claim 11, in which the second time period begins before the first transition from low to high of the first clock signal.

21. A memory containing:
an array of memory cells, each memory cell of the array represents a memory cell with six transistors;
the first port containing a first set of lines of the input address and the input line of the clock pulse, the first clock signal is present on input line sync pulses of the first port, the first clock signal goes to a high level at the first transition from low to high, then remains at a high level during the first time interval, then goes to low level when moving from high to low level, and then remains at a low level during the second time interval and then goes to a high level when the second transition from the low level is high;
the second port containing a second set of lines of the input address and the input line of the clock pulses and the second clock signal is present on input line sync pulses of the second port; and
initiation means the first access to the memory array in response to the first transition from low to high of the first clock signal on input line sync pulses of the first port, the first memory access has a certain length and a certain length does not depend on the time interval when the first clock signal remains at a high level, this tool is also used for:
in the first case: the initiation of the second address to the memory array immediately after the first access to the memory, if the transition from low to high of the second clock signal detected by the funds during the first period of time, and
in the second case: the initiation of the second address to the memory array of the second transition from low to high of the first clock signal if the transition from low to high of the second clock signal detected by the funds during the second period of time, with the end of the first period of time coincides with the beginning of the second period is the time and thus the second memory access is delayed by the delay introduced by element time delay.

22. Memory for item 21, in which the first period of time approximately coincides with the first time interval.

23. Memory for item 21, in which in the second case, when the first address to the memory, there is a delay, and then the tool initiates the second memory access.

24. Memory for item 21, in which the first port is a port for reading and the second port is a port write-only.

25. Memory for item 21, and the memory is pseudodiaptomus memory.

26. Memory for item 21, in which the second memory access includes the initial period of pre-charge and the subsequent period during which the information is written in the memory cell array.

27. Memory for item 21, in which the element time delay provides the multiplexer with a time delay.

28. Memory for item 21, in which the first period of time starts at the moment of transition from low to high of the first clock signal, and in which the first period of time ends at the moment of transition from the high level to the low of the first clock signal.

29. Memory for item 21, in which the second time period begins before the first transition from low to vysokonapornogo input clock signal.

30. Pseudodementia memory containing:
an array of memory cells, each memory cell array includes multiple transistors;
the first port containing a first set of input lines and address lines of the input sync pulses, with the first transition from low to high of the first input clock signal on input line sync pulses of the first port causes the latching of addresses in the first set of input lines of the address in pseudodiaptomus memory, and initiates the first call to a memory array of memory cells; and
the second port containing a second set of lines of the address input and the line input sync pulses, with:
in the first case: the transition from low to high of the second input clock signal on input line sync pulses of the second port during the first time period causes the latching of addresses in the second set of lines, enter the address in pseudodiaptomus memory and causes the initiation of the second memory access of the array of memory cells after the first access to the memory and to the second transition from low to high of the first input clock signal, and
in the second case: the transition from low to high of the second input clock signal on input line with hranitelyami pulses of the second port during a second period of time causes a delay of the second memory access of the array of memory cells until the time after the second transition from low to high of the first input clock signal, while the second memory access is delayed by the delay introduced by element time delay, and thus the end of the first period of time coincides with the beginning of the second period of time.

31. Pseudodementia memory according to item 30, in which the element time delay provides the multiplexer with a time delay.

32. Pseudodementia memory according to item 30, in which the first period of time starts at the moment of transition from low to high of the first input clock signal, and in which the first period of time ends at the moment of transition from the high level to the low of the first input clock signal.

33. Pseudodementia memory according to item 30, in which the second time period begins before the first transition from low to high of the first input clock signal.

34. How to access pseudodiaptomus memory containing phases in which:
take the first clock signal input line, a clock signal of the first port pseudodiaptomus memory, while the first clock signal goes to a high level at the first transition from low to high, then remains at a high level during the first time interval, then goes to low level when moving from you which will be about the low level then remains at a low level during the second time interval and then goes to a high level when the second transition from low to high;
take the second clock signal input line, a clock signal of the second port pseudodiaptomus memory;
perform the first operation of the memory access in response to the first transition from low to high of the first clock signal, the first operation of the memory is initialized during the first time interval, and the first operation of the memory access is a reference to an array of cells pseudodiaptomus memory, each of the memory cells includes many transistors, and the first operation of the memory access has a certain length and a certain length does not depend on the first interval of time; and
perform the second operation of the memory access in response to a transition from low to high of the second clock signal, while the second operation of the memory access is a reference to an array of cells pseudodiaptomus memory, and the second operation of the memory is initialized immediately after the completion of the first operation of the memory access, if the transition from low to high of the second clock signal carries out the I in the first period of time, and the second operation of the memory is not initialized immediately after the first access to the memory, but instead is initialized after the second transition from low to high of the first clock signal if the transition from low to high of the second clock signal is in the second period of time, while the second operation of the memory access initiated after a delay introduced by element time delay, and thus the end of the first period of time coincides with the beginning of the second period of time.

35. The method according to clause 34, in which the element time delay provides the multiplexer with a time delay.

36. The method according to clause 34, in which the first time period begins at the time of the first transition from low to high of the first clock signal, and in which the first period of time ends at the moment of transition from the high level to the low of the first clock signal.

37. The method according to clause 34, in which the second time period begins before the first transition from low to high of the first clock signal.



 

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