Method of electrically insulated silicon regions formation in bulk of silicon wafer

FIELD: electricity.

SUBSTANCE: method involves notching in bulk of a silicon wafer and silicone removing from the wafer back to uncover notch bottoms. Notching enables silicone pattern formation to represent hollow cell walls that is followed with wall-through oxidation to form a dielectric SiO2 conduit system. Silicon removing from the back of the wafer can be conducted by the deep plasma etch process.

EFFECT: high strength of the insulating element which can be used for manufacturing various MEMS devices in bulk of a standard silicon wafer.

2 cl, 13 dwg

 

The invention relates to devices for micro-Electromechanical systems (MEMS), in particular in their manufacture. The invention consists in a method of forming electrical isolation between elements of the MEMS devices during their manufacture in volume of silicon wafers.

For the manufacture of various MEMS devices (microgyroscope, microaccelerometer, microactuator) needs to create micromechanical moving parts that must be electrically isolated from the static elements. For the manufacture of such devices are commonly used plate-type silicon-on-insulator (SOI), which represent the two silicon wafers, fused through an intermediate dielectric layer (SiO2). Methods of making electrically isolated parts of MEMS devices using SOI-wafer-based processes of deep plasma etching of grooves in the instrument silicon wafer to the dielectric layer. When this separation occurs at the instrument side of the SOI wafer to electrically isolated region of the silicon on insulator, separated from each other by an air gap (see N.Maluf. An introduction to microelectromechanical system engineering, Artech House, Boston, 2000, P.68). The intermediate dielectric layer is often used as a sacrificial layer that is removed from under the future of mobile elements in the process fluid is local operations liberation (hanging). However, due to the high cost of SOI wafers are methods of forming isolated regions in a conventional silicon wafer. Currently there are several known methods for the production of MEMS devices on standard silicon wafers. In them, as in SOI-technology for the formation of structural elements used a process of deep plasma etching of silicon.

In one of these ways in the first silicon wafer of n-type conductivity with orientation (111) is formed structural elements of the device vertical etching grooves in a plasma process. Surface grooves legarrette boron and is a stop layer for liquid provide the Etchant of silicon of n-type. The next stage of the grooves deepen, in the amount of silicon that is not doped with boron. Next is a liquid etching of silicon, which is parallel to the surface of the plate Si (111). Thus, multiple procedures deep plasma etching and doping for marking the future of mobile elements. In this way electrical isolation is provided by the p-n-transitions that occur in structural elements (in this case spring suspensions actuator), which consist of fully doped with boron silicon (see Julius Ming-Lin Tsai, Huai-Yuan Chu, Jerwei Hsieh and Weileun Fang. The BELST II process for a silicon high-aspect-ratio micromachin vertical comb actuator and its applications. // J. Micromech. Microeng. 2004. V.14. P.235-241). The disadvantages of this method include the technological complexity and the problem of sticking of movable parts of the device characteristic of the liquid ways of posting.

In another method uses only the plasma etching of a silicon wafer. The method consists in forming on the surface of the bridges of the deposited dielectric and subsequent removal of the material of the plate under the bridges in open areas. Thus, formed is separated from the volume of the silicon plate movable area, suspended on thin film jumper, which is formed by a dielectric mask for plasma etching of grooves (see Bertz, A.; Küchler, M.; Knöfler, R.; Gessner, T. A novel high aspect ratio technology for MEMS fabrication using standard silicon wafers. Sensors and Actuators A 97-98 (2002) 691-701). The disadvantages of this method are the low mechanical strength of the suspensions and high parasitic capacitance formed hung out parts and the substrate.

Closest to the claimed method (prototype) is a method of forming electrical isolation in the volume of the silicon wafer by performing it grooves, in which conformally deposited dielectric (SiO2) and then filling them with polyctenium. Then is anisotropic liquid etching silicon from the back side of the plate to the opening of the bottom for anenih grooves, in the resulting insulating element consisting of two layers of SiO2film on the walls of the groove with a layer of polysilicon between them. When designing the topology of a MEMS device structural elements is positioned so that during their formation they were mechanically linked to the levels of silicon wafers only through an insulating elements (Zhu Y., Yan G., Fan J., Zhou J., Liu X., Li Zh., Wang Y. Fabrication of keyhole-free ultra-deep high-aspect-ratio trench isolation and its applications. // J. Micromech. Microeng. 2005. V.15. P.636-642). The mechanical strength of this design depends on the adhesion SiO2film to the silicon and polysilicon. The disadvantages of this method are the low mechanical strength and the complexity of the process of filling deep grooves polyctenium.

The technical problem solved by the present invention:

1. Creating a mechanically strong, electrically isolated elements in the wafer of monocrystalline silicon using the method of plasma etching.

2. Create electrically isolated structural elements of the MEMS devices on both sides of a silicon wafer, which significantly extends the capabilities and variety of types of MEMS devices.

3. The creation of sensors and actuators, having a small parasitic capacitance.

The technical result is achieved by the fact that in the known method of forming electrically isolated is the R regions of the silicon in the volume of the silicon wafer by performing it grooves and remove silicon from the back side of the plate for opening the bottom of the groove, grooves in silicon perform for the formation of silicon structures that represent the walls of hollow cells, with subsequent oxidation of the walls of the thickness and the education system dielectric SiO2jumpers.

The distinctive feature of the proposed method is that the grooves in silicon perform for the formation of silicon structures that represent the walls of hollow cells, with subsequent oxidation of the walls of the thickness and the education system dielectric SiO2-jumpers.

An additional difference is that the removal of the silicon from the back side of the plate are a method of deep plasma etching.

To obtain the electrically isolated regions of silicon in the volume of the silicon wafer to form an insulating elements in the form of SiO2-jumpers. Stages of formation of the insulating elements of the following:

- fabrication of silicon structures by the method of deep plasma etching of grooves in silicon. Etching of silicon is carried out through a mask with a pattern in a grid: - open it Windows of various shapes, which are located at a given distance from each other. As a result of etching is obtained silicon structure representing a wall of hollow cells. The thickness of the wall is determined by the distance between the grooves and the height of the cells is the depth of t is Alenia;

- treatment of silicon structures by the method of thermal oxidation to achieve oxidation of the silicon walls on all their thickness throughout the height of the cells. In the complete oxidation of the thickness of the walls of the cell increases more than 2 times, and the cavity of the cell is narrowed.

Increasing the mechanical strength of isolated areas when using the presented method of manufacture in volume of silicon wafers due to the fact that the insulating element in the form of SiO2-jumpers is formed entirely of original material by oxidation. The size, shape and number of cells and the thickness of their walls is chosen so that the oxidation did not occur clamping cavity cells until complete oxidation of the walls and ensure minimal mechanical stress in the dielectric layer.

Application of method of deep plasma etching during removal of the silicon from the back side of the plate allows you to create additional elements of the MEMS device.

The claimed technical solution is not known from the prior art, which allows to make a conclusion about its novelty. In addition, it is not obvious from the prior art that speaks for its inventive step.

The invention is illustrated by drawings, where figure 1 is given a schematic representation of the stages fo the formation of the insulating element in the form of SiO 2-jumper (11): a - cross section of a wafer after a deep plasma etching of grooves, where 1 - groove, 2 - wall is made of silicon between the grooves 101 - the silicon wafer; b - same, after a process of thermal oxidation of the walls of the cells, where 3 - SiO2-jumper, 4 - SiO2film.

Figure 2 is a schematic depiction of an isolated region of silicon (103) after removal of the silicon from the back side of the plate for opening the bottom of SiO2-jumper (3), 17 recess in the silicon wafer. Left view from the top plate, on the right in the section a - A.

The invention is illustrated by the example of the method for manufacturing the MEMS device is an electrostatic comb drive (EGP), a plate of monocrystalline silicon.

Example

The purpose of structural elements EGP illustrated by figure 3, which shows the image elements EGP with the front side plate: 11 to surround the insulating element in the form of SiO2-jumper (3); 12 - stationary comb structure; 13 - movable comb structure; 14 - spring suspensions of the movable comb structure; 15 - rod. When applying an electric voltage between the fixed and movable comb occurs sucking force that causes the spindle in motion.

The sequence of technological operations in the manufacture of EGP using the proposed method of isolation is explained in figure 4 (left - top view, right - transverse section of the plate).

Manufacturing technology EGP includes four standard contact photolithography for forming a mask for plasma etching of the silicon wafer. In the first photolithography process, the front side plate is made of a resistive mask is patterned in the form of a system of parallel rectangular Windows with a width of 2.5 μm and a length of 70 μm, spaced at intervals of 2.5 μm. Then carry out the process of anisotropic plasma etching of silicon obtained through the mask, the result is a system of grooves (1) in the form of cells and a depth of 40 μm and the thickness of the walls (2) between cells 2 μm. After removing the resist conduct the process of thermal oxidation of the wafer at 1100°C for 14 hours. Thus, you receive a large (300×70×40 μm) insulating element (11) in the form of SiO2-jumper (3). Film SiO2(4) thickness of 2.2 μm, obtained in the oxidation process on both sides of the plate, is used as a mask in the subsequent plasma etching processes

In figure 4,a: 11 - system of SiO2-jumpers in the silicon wafer, 4 - SiO2film on the surface plate 101 is silicon.

In the second and in the third photolithography process to form the resist mask in the form located one above the other rectangular Windows on the front and reverse side of the Plaza is ins with dimensions of 500×500 μm and 600×600 μm, respectively. Then, on both sides of the plate give standard liquid etching SiO2film before the opening of the silicon surface in the area of these Windows, and then the resist is removed. The result of the presented operations illustrated by figure 4,b, where 23 is opened in SiO2-film silicon surface on the front side of the plate 24 is opened in SiO2film silicon surface on the back side of the plate.

The next step on the front surface of the plate put a layer of metal (Cr) with a thickness of 0.2 μm. In the fourth photolithography process in the resist on the front surface of the plate form the image elements EGP (12-15) and pads (6), which is then transferred to the metal layer. Figure 4,presents the image of a metal mask for forming elements EGP (12-14) and pads (6).

This is followed by plasma etching of silicon: first deep plasma etching of silicon from the back side of the plate (17) until the opening of the bottom insulating element (11). In this form the instrument silicon layer (103) with a built-in insulating element (11). Then carried out through plasma etching epitaxial layer on the front side of the plate and form the elements of the device 12-15. The result of the presented operations schematically illustrated by figure 4,g,where 12-14 - schematic illustration of the elements EGP formed in the instrument silicon layer (103). Stationary comb (12) is mechanically connected with the plate 101 only through an insulating element 11 and is electrically isolated from the volume of the plate. The device operation is guaranteed if the electric voltage to the contact pads of the static and moving parts of the device.

Thus, as follows from the above example, the proposed method allows the manufacture of a MEMS device on a standard silicon wafers.

1. The method of forming electrically isolated regions of silicon in the volume of the silicon wafer by performing it grooves and remove silicon from the back side of a silicon wafer for the opening of the bottom of the grooves, wherein the grooves in silicon perform for the formation of silicon structures that represent the walls of hollow cells, with subsequent oxidation of the walls of the thickness and the education system dielectric SiO2-jumpers.

2. The method according to claim 1, characterized in that the removal of the silicon from the back side of the plate are a method of deep plasma etching.



 

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