Semiconductor integrated circuit (versions)

FIELD: physics.

SUBSTANCE: invention relates to design and technology of manufacturing semiconductor integrated circuits (IC) and can be used in digital, analogue and memory units in microelectronics. The semiconductor IC has a high-resistance monocrystalline silicon layer grown in form of a hollow cylinder in which there are regions with different conduction type, which form bipolar transistors, resistors and capacitors. On the outer surface of the high-resistance monocrystalline silicon layer there are emitter and base contacts adjacent to corresponding regions of corresponding transistors connected to resistors and capacitors by conductive paths formed on the surface of a dielectric placed on the outer surface of the high-resistance monocrystalline silicon layer, and on the inner surface of the high-resistance monocrystalline silicon layer there is a collector contact in form of a hollow cylinder adjacent to the collector regions of the transistors or the adjacent silicon layer.

EFFECT: higher degree of integration of the IC, reduced feature size of the element, lower level of inter-electrode connections, reduction of power consumption by one switching, increased reliability.

3 cl, 1 dwg

 

The invention relates to the field of electronic equipment, in particular to the design and manufacturing technology of semiconductor integrated circuits (IC), and can be used in digital, analog and memory devices of microelectronics.

Known silicon semiconductor integrated circuit of transistor-transistor logic (TTL), made planar epitaxial technology isolating p-n-junction method of collecting insulating diffusion (CED technology), methods "Isoplanar", "Polyplanar" or "V-ATE" and other technologies (Iieiiou, Ieazr. "Fundamentals of microelectronics" (design)" M, High school, 1978, s-298, Iieiiou, Ieazr. "Fundamentals of microelectronics" (physical and technological basis)" M, High school, 1986, s-339).

The disadvantages of semiconductor IP planar-epitaxial structures are low reliability R≤0,98, low marginal degree of integration (equals about N=2,5·107e/cm2), a high level interelectrode connections, volume commensurate with the displacement of the active transistor elements, a high power level on one switch (Rneed to change the≈8·10-8W or quality factor (Q)>10-15J) and other

The closest analogue is unnatural semiconductors silicon the new IP NMOS structure, formed on non-planar spherical substrate of silicon with a diameter of 1-1,2 mm, obtained in a special plasma furnace. On the surface of the silicon politology areas of p-type using stereophotography formed "CHIP" (or gate) of the MOS transistor with an insulated gate, degenerate monocrystalline silicon n+type layers of the drain and source metal contacts, as well as layers of dielectric SiO2on which is formed a metal contact seal (U.S. patent No. 5945725, CL H01L 29/06, publ. 1999).

The disadvantages mentioned silicon semiconductor IP NMOS structures are:

1. The size of the MOS integrated "CHIP" is a significant amount of order Δ≈5 µm;

2. The degree of integration is limited to the surface of a sphere with a diameter of 1-1,2 mm and is equal to N<106e/cm;

3. In the formation of crystals of very large scale, for example, VLSI needed connections between silicon spheres, pellets in blocks using a special mounting on single platforms, significantly different from the standard dimensions of the IC packages, which degrades the reliability indices (P≤0.95 and power dissipation P>10-7W on one switch).

Technical results that may be obtained by carrying out the invention are an increase in the degree of integration of IP, the mind is isenia topological element size, reducing the interelectrode connections, reducing power consumption on one switch, improving the reliability.

This technical result in the first embodiment of the invention is achieved by the fact that contained in the semiconductor integrated circuit of a high-resistance single-crystal silicon layer is grown in the form of a hollow cylinder in which is formed a region of different conductivity type, forming bipolar transistors, resistors and capacitors, on the outer surface of the high resistivity single crystal silicon layer formed by the emitter and base contacts adjacent to the corresponding regions of the respective transistors are connected to resistors and capacitors, conductive paths formed on a dielectric surface, is placed on the outer surface of the high resistivity single crystal silicon layer and on the inner surface of the high resistivity single crystal silicon layer formed in the collector contact in the form of a hollow cylinder, adjacent to the collector regions of the transistors.

In the second variant of the invention the specified technical result is achieved by the fact that contained in the semiconductor integrated circuit of a high-resistance single-crystal silicon layer is grown in the form of a hollow cylinder in which is formed the sphere of the different conductivity type, forming bipolar transistors, resistors and capacitors, on the outer surface of the high resistivity single crystal silicon layer formed collector and base contacts adjacent to the corresponding regions of the respective transistors are connected to resistors and capacitors, conductive paths formed on a dielectric surface, is placed on the outer surface of the high resistivity single crystal silicon layer and on the inner surface of the high resistivity single crystal silicon layer formed in the emitter contact in the form of a hollow cylinder adjacent to the emitter regions of the transistors.

In addition, as in the first and second embodiments of the invention the current-carrying paths, and an emitter, base and collector contacts may be made from two layers of different non-magnetic metals, and the layers are formed so that the layer located at the side of a high-resistance single-crystal silicon layer has a lower conductivity in the direction of flow of electric current than the conductivity of another layer in the same direction.

The drawing shows the IP type TTL on cylindrical silicon substrate.

Semiconductor integrated circuit includes a high-resistance single-crystal silicon p-type layer is, grown in the form of a thin-walled hollow cylinder 1 in which is formed an emitter (n-type) 2, the collector (n-type) 3 and a base (p-type) region 4 forming a bipolar (NPN) transistor, and the field forming passive elements 5 (resistors and capacitors).

On the outer surface of the high resistivity monocrystalline silicon of p-type layer is formed, the emitter 6 and the base 7 contacts adjacent to the corresponding regions of the respective transistors.

The emitter 6 and the base 7 of the contacts is connected to passive elements 5 (resistors and capacitors) interelectrode connections - conductive paths 8, formed on the surface of the insulating dielectric 9 is a layer of silicon dioxide, is placed on the outer surface of the high resistivity monocrystalline silicon of p-type layer.

On the inner surface of the high resistivity single crystal silicon layer formed in the collector contact 10 in the form of a thin-walled hollow cylinder adjacent to the collector regions 3 transistors.

The contact 10 can adjoin to the collector regions 3 transistors directly, but through substrate - silicon layer is p-type.

Conductor tracks 8 and the emitter 6, the base 7 and the collector 10 contacts consist of two layers 11 and 12 of different non-magnetic metals, such as titanium, platinum, gold, who elebra, copper, aluminum, molybdenum or tungsten.

Layers 11 and 12 are formed so that the layer located on the side of the high-resistance single-crystal silicon layer has a lower conductivity in the direction of flow of electric current than the conductivity of another layer in the same direction. This is ensured by the selection of metals for execution layers.

The emitter 2, the base 4 and the collector 3 areas, as well as passive elements 5 formed by the methods of stereophotography or by other known methods.

The principle of the cylindrical semiconductor silicon integrated circuits, such as TTL, is as follows.

With application of an external voltage U0≤5 V input integrated transistor n-p-n-type unit cell TTL integrated circuit passes a large current, and the voltage drop across it is small and has a value of ΔU0≤0,8 Century

In saturation mode, both the p-n junction integrated transistor biased in the forward direction, resulting in areas of the base, and collector are accumulated charges of minority carriers. When the transfer transistor from open to closed, you must spend some time on the resolution of the charges, after which the transistor of the unit cell is switched off, i.e. goes into cutoff mode. Time races is asiania charges plays a major role in determining the time delay of propagation of the input signal, i.e. in the performance schema, it is equal to tC<10 NS with an average power consumption of one cylindrical element IP R≤10-8W, and the product of the delay time on the power Q=P·tCis in the range 10π j<Q<50π j, since the degree of integration increases 2π times on the surface of the cylindrical substrate, and the number of current-carrying paths in the presence of managing internal cylindrical (tubular) contact, due to the cylindrical symmetry is reduced to 2π times.

When serving in the inner cavity of the collector contact 10 of the cooling agent is provided an additional opportunity forced cooling of IP, which leads to increase capacity and reliability.

The second variant of the invention is that in the form of a hollow cylinder 1 grown high resistivity single crystal silicon layer is n-type, in which is formed an emitter (p-type) 2, the collector (p-type) 3 and a base (n-type) region 4 forming a bipolar p-n-p) transistors, and on the inner surface of the high resistivity single crystal silicon layer formed in the emitter contact 10 in the form of a hollow cylinder adjacent to the emitter regions 3 transistors.

1. Semiconductor integrated circuit containing the high-resistance single-crystal silicon layer p-type grown in the de of the hollow cylinder, which formed region of different conductivity type, forming bipolar transistors, resistors and capacitors, on the outer surface of the high resistivity single crystal silicon layer formed by the emitter and base contacts adjacent to the corresponding regions of the respective transistors are connected to resistors and capacitors, conductive paths formed on a dielectric surface, is placed on the outer surface of the high resistivity single crystal silicon layer and on the inner surface of the high resistivity single crystal silicon layer formed in the collector contact in the form of a hollow cylinder adjacent to the collector regions of the transistors or to the adjacent silicon layer p-type.

2. The semiconductor integrated circuit according to claim 1, characterized in that the conductor tracks and the emitter, base and collector contacts consist of two layers of different non-magnetic metals, and the layers are formed so that the layer located at the side of a high-resistance single-crystal silicon layer has a lower conductivity in the direction of flow of electric current than the conductivity of another layer in the same direction.

3. Semiconductor integrated circuit containing the resistance monocrystallic the ski silicon layer is n-type, grown in the form of a hollow cylinder in which is formed a region of different conductivity type, forming bipolar transistors, resistors and capacitors, on the outer surface of the high resistivity single crystal silicon layer formed collector and base contacts adjacent to the corresponding regions of the respective transistors are connected to resistors and capacitors, conductive paths formed on a dielectric surface, is placed on the outer surface of the high resistivity single crystal silicon layer and on the inner surface of the high resistivity single crystal silicon layer formed in the emitter contact in the form of a hollow cylinder adjacent to the emitter areas of the transistors or to the adjacent silicon layer of n-type.



 

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