Dynamic serial functional device

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to micro- and nanotechnology and can be used in designing dynamic memory, two-dimensional control matrices for liquid-crystal displays, high-speed and high-precision scanners, two-dimensional sensors, delay lines etc. The device uses a chain series-connected active functionally integrated cells which can control technologically compatible electric devices. Each cell of the chain is a simple electric circuit consisting of a MOS transistor, resistors and a capacitor. The time used is the delay time for switching off the MOS transistor relative the end of the output signal.

EFFECT: invention speeds up operation of the functional device, simplifies its manufacturing technology, reduces its size and improves its integration.

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The invention relates to micro-and nanoelectronics and can be used, in particular, when creating storage devices, two-dimensional control matrix for liquid crystal displays, high-speed scanners, sensors, delay lines, etc.

Known analogues, i.e. dynamic sequential function device (DPFU), can consistently move the information charge along the chain of the constituent elements of the pixel [1-3], for example, DPFU device consisting of series-connected bipolar [1, 3] (see figure 1) or MOS-transistors [2, 3] (see figure 2), which in the literature is called "fire chain". Wide application in optical receivers image to find DPFU on the basis of series-connected MOS-structures, called "charge-coupled devices (PLD) [3] (see figure 3).

However, these DPFU devices have the serious disadvantage that they are not able to enhance a portable information charge, which ultimately leads to its weakening or complete attenuation. In addition, the pixels of these devices DPFU not able to manage technologically compatible with other electronic devices - transistors, resistors, LEDs, etc.

Another drawback of these DPFU is the need tacti the Finance chain of series-connected pixel to provide travel information charge from pixel to pixel, that requires the use of two or three clock tyres, which significantly complicates the design and construction of DPFU device.

These drawbacks are partially deprived closest in the technological nature of DPFU described in the patent of Russia [4] and PCT application for a patent [5], taken as a prototype. This DPFU (see figure 4) contains a chain of series-connected pixel including input and output bus (terminals), a common bus and the power bus, while the output bus (terminal) of each pixel, except the last, are connected to the input bus (terminal) the subsequent pixel. Each pixel of the chain contains a bipolar transistor, and its collector connected to an output bus and through a resistor to the power bus, the emitter is connected to the shared bus, and the base is connected through another resistor to the common bus and through a capacitor to the input bus, and the data storage time is determined by the time of recombination of minority carriers, which

where tusthe time of saturation, τ0the lifetime of minority carriers, Itoand Ib- current collector and base, respectively, h21 - gain current database.

This device DPFU also not without flaws, which are in low performance due to the use mode "deep" saturation of the bipolar transis the ora, the relative complexity of the bipolar transistor structures, as well as their relatively large size, which does not allow to achieve the maximum level of integration DPFU.

The technical effect of the invention is to improve performance, maintainability, and integration of DPFU.

These effects are achieved by the fact that each pixel of the chain contains not bipolar MOS transistor, a capacitor, a first resistance, the second resistance and the third resistance, and the gate of the MOS transistor is connected through a capacitor to the input bus (terminal) and through the first input impedance to the common bus, its drain connected through a second load impedance to the bus power supply, its gate region through the third additional resistance is connected to the shared bus, and a source connected to a common bus.

At the same time, storing information charge is determined by the delay time turn-off MOSFET (tass), which should exceed the time constant recharge (τp) capacitor (C) through (first) input resistance - R1

tass>C·R1

and the value of the works of the capacitor With the value of the input voltage UIexceed the value of the works gate capacitance - gate region (CRFP)multiplied by the amount which the threshold voltage of the MOS transistor (U T)

UI·C>UT·RFP

To ensure synchronization (which is important for some applications) the first is the input resistance of the pixel of DPFU can be connected to the secondary bus synchronization.

To ensure greater adaptability, the capacitor and the first input and/or (third) of the additional resistance of the pixel can be made on the basis of diodes, the anode of the diode, the replacement capacitor is connected to the gate of the MOS transistor, and the cathode to the input bus (terminal), the anode of diode replacement (first) input resistance connected to the shared bus and the cathode to the gate of the MOS transistor, the anode of diode replacement (third) additional resistance connected to the gate region, and its cathode to the common bus.

To ensure greater reliability, the gate region of the MOS transistor is connected to the additional bipolar transistor, the collector of which is connected to the field of flow, and the emitter - to source of the MOSFET.

To simplify the design of the scheme DPFU, the gate region may be connected to nothing, i.e. to be "floating", i.e. in this case (third) additional resistance is infinity.

Description of electrical circuits

Figure 1 shows the electrical diagram of DPFU type "fire" chain selected is the analogue of the invention, containing the pixel output bus 2 are connected in series with the input tyres 1 subsequent pixel, while the electrodes of bipolar transistors 3 are connected respectively to the emitters to the input bus 1, the collectors to the output bus 2, base via respective capacitors 4 is connected to the reservoir and the odd 5 even 6 tires, respectively.

Figure 2 shows a similar electric circuit, is selected as the similar DPFU type "fire" chain on MOS transistors. Designation in the circuit are identical.

Figure 3 shows the construction of another similar device, called "CCD", device, containing consistently located MOS structure 3.

In CCD devices also have a clock bus 5, 6, 7, however, the input bus-terminal is available only on the first pixel and the output - at last.

Figure 4 shows the electrical circuit of DPFU, taken as a prototype. It contains a series of pixels, each of which contains the input 1 and output 2 bus (terminal), a common bus 3, the power bus 4, a capacitor 5, the first resistor R1 6, the second resistor R2 7, the bipolar transistor 8.

Figure 5 shows the electrical diagram of DPFU corresponding to the first claim. The electrical circuit includes a chain of series-connected pixels, each of which has I is dnow 1 and output 2 bus (terminals), a common bus 3 and bus power supply 4, a capacitor 5, (first) input resistance 6, (second) load resistance 7, (third) additional resistance 8, the MOS transistor 9. In the diagram, the gate of the MOS transistor 9 through a capacitor 5 is connected to the input terminal 1 and through the (first) input resistance R1 6 is connected to the common bus 3, its drain connected to the output bus 2 through a load resistance R2 7 is connected to the power bus 4, the gate region of the MOS transistor 9 through the (third) additional resistance 8 is connected to the common bus 3.

Figure 6 shows the electric circuit of DPFU corresponding to claim 2. The electrical circuit includes a chain of series-connected pixels, each of which has an input 1 and output 2 bus (terminals), a common bus 3 and the rail 4, the capacitor 5, the first resistance 6, the second resistance 7, the third resistance 8, the MOS transistor 9, the gate through which the first resistance R1 6 is connected to the additional clock bus 10, its drain connected to the output bus 2 through the resistance R2 7 is connected to the power bus 4, the gate region of the MOS transistor 9 through the third resistance 8 is connected to the common bus 3.

7 shows the electrical circuit of DPFU corresponding item 3 claims. The electrical circuit includes a chain of succession is entrusted enabled pixel, each of which has an input 1 and output 2 bus (terminals), a common bus 3 and the rail 4, the capacitor 5, the first resistance 6, the second resistance 7, the third resistance 8, the MOS transistor 9 in the diagram, the gate of the MOS transistor 9 is connected to the anode of the diode 11, the cathode of which is connected to the input bus 1 and the anode of the diode 12, the cathode of which is connected to the common bus 3, its drain connected to the output bus 2 through the resistance R2 7 is connected to the power bus 4, the gate region of the MOS transistor 9 through a third resistance connected to the shared bus.

On Fig shows the electric diagram of DPFU corresponding to 4 of the claims. The electrical circuit includes a chain of series-connected pixels, each of which has an input 1 and output 2 bus (terminals), a common bus 3 and the rail 4, the capacitor 5, the first resistance 6, the second resistance 7 third resistance 8, the MOS transistor 9 and the bipolar transistor 13. In the diagram, the gate of the MOS transistor 9 is connected through a capacitor 5 to the input bus 1 and through the first impedance to the common bus 3, its source connected to the common bus 3, its drain connected to the output bus 2 through the resistance R2 7 is connected to the power bus 4, the gate region of the MOS transistor 9 connected to the base of bipolar transistor 13, the collector of which is connected to the output bus 2, and the emic is er - to the common bus 3.

Figure 9 shows the electric diagram of DPFU corresponding to the item to claim 1 of the claims. The electrical circuit includes a chain of series-connected pixels, each of which has an input 1 and output 2 bus (terminals), a common bus 3 and the rail 4, the capacitor 5, the first resistance 6, the second resistance 7, the third resistance 8, the MOS transistor 9, the gate of which is connected through a capacitor to the input bus 1 and through the first resistance is connected to the common bus 3 and the input bus 1, and its drain connected to the output bus 2 through the resistance R2 7 is connected to the power bus 4, the gate region of the MOS transistor 9 no what is not connected (i.e. has a "floating" potential).

DPFU device (see figure 5) is as follows.

When receiving the "long" negative input pulse (UI) at the input terminal 1, as shown in figa, is differentiation at the expense of the R-C chain, formed by the condenser 5 and the resistance R1 6. As a result, the gate of the MOS transistor 9 are formed two "short" pulse: negative and positive, respectively (see figb). This positive pulse opens the MOS transistor 9, which up to this point in the closed state. However, the open state of the transistor (tOTC) can significantly previsit is the time of the positive short pulse (t uti+) and the duration of the input pulse (tuti), i.e. in real transistors there is always a time delay switch-off transistor (tass) in relation to the time of expiry of the input signal (see figv). This phenomenon in the MOS-FET is usually highly undesirable and due to the known physical effects obtained in the literature names: - "kink effect", "bodi-effect", the effect of the parasitic n-p-n transistor. In the proposed wiring diagram of DPFU these parasitic effects are used to remember the fact that pulse to the input pixel by the value of time (tass). In this case, DPFU is used as a device dynamic RAM (tass) is essentially the time information storage charge in the pixel memory.

It is obvious that the receipt of the output signal (Uowith the drain of the MOS transistor of the first pixel on the input of the next pixel of DPFU, for which he will be input, will lead to the same process. Thus, the impulse applied to the first memory cell, will gradually spread through the whole chain of the pixel due to the sequential opening of the MOS transistors of the pixel (see Figg). The input of DPFU several divided by time of the input pulse causes the sequential movement information signals is charges along the chain the pixel, the same as "running line" illuminated signs.

It should be noted that the device DPFU, as well as the CCD device is a functional device, because the technical result is achieved due to the simultaneous use of the original scheme and the specific parasitic effects inherent in the MOSFET structure, which cannot be adequately described by means of the circuit.

It is important to note that the efficiency of the chain the pixel DPFU, possible only when the above ratios

tass>C·Rl,

which specifies a condition acceptable to the differentiation of the input pulse and conditions

UI·≫VT·Cn,

determining a necessary condition for a sufficient opening of the MOS transistor. Usually tasscorrelated with the size of the lifetime of minority charge carriers in the gate region.

The work of DPFA in asynchronous mode modeled using known computer programs "SPACE". B as an example figure 11 shows the time dependence of the output voltage to a chain of from 8 pixel on the entrance of which is filed with single pulse.

For some applications, DPFU important synchronous operation with other electronic devices (for example, in schemes sweep flat TV images), with d the I provide synchronization mode is sufficient supply clock pulses to only one clock bus 10, as shown in Fig.6. Modeled using SPACE program timing diagram of the operation of DPFA in asynchronous mode shown in Fig.

The chain of DPFU possible in case of replacement of the condenser 5 and/or resistor R1 6 diodes 11 and 12, respectively (see Fig.7). In this case, the barrier capacitance diode 11 performs the function of the capacitor, and the presence of the reverse current of the diode 12 provides the required zero potential on the gate of the MOS transistor. This replacement capacitor and resistors R1 and/or R3 provides greater manufacturability of DPFU and its smaller size, i.e. greater integration. It should be noted that as the resistor R2 7 can be used by any element dvukhpolosnykh (led, inductance etc).

In case of using dlinnorazmernyh" MOS transistor in which the above-mentioned parasitic effects are weaker, you can use a combination of the pixel MOS and bipolar transistors, as shown in Fig. In this case, significantly reduced the dependence of the health of DPFU the magnitude and variability of the nominal capacitance and resistance of the resistors of the circuit, as well as from the electrophysical parameters of MOS and bipolar transistors. This circumstance ensures high reliability circuit operation.

Scheme DPFU using MOS transistors with lavasa" gate area (see Fig), differs from previous schemes less performance, because it is the most pronounced spurious effects. However, it has the best integration, because there is no resistance in the gate region (R3), and pin to it. Such DPFU can be easily realized on the basis of technology "silicon on insulator" (SOI (see Fig). This scheme can be used when speed is not a determining parameter.

Practical use

Experienced device (models) DPFU were made based on standard technologies CMOS VLSI on monogrammable and on dielectric substrates. Topology and design of such devices is minimal topological norm of LT~1.5 µm are shown respectively on Fig and 14. Resistor fabricated on polikremnii n--type, respectively, R1=10 Mω, R2=100 kω, the capacitance value of the capacitor C=10-13F, the length and width of the gate of the MOS transistor, respectively, was LK=1.5 mm, W to=10 μm, the capacity of the bolt system WithRFP=10-14F, capacitance drain - sourcewith=Cand~5·10-14F. the size of the Mesa-structure transistor (length and width) were, respectively, LM=20 μm and W~10 μm, the thickness of the gate oxide δ~300 Å. The threshold voltage (UT) MOSFETs were UT~1,0V, the power supply circuit +Uc=5th Century a breadboard model of DPFU showed its stable performance under a wide change of parameters of circuit elements in the range of ±200% and the supply voltage +Uc=2.5 V to the 10th Century

In conclusion, it should also be noted the important advantages of DPFU, which are as follows:

- exceptionally low energy consumption when it is used as a scanning device, since in this case the energy consumption is only one pixel (see Fig);

- extremely high reliability, a high percentage of yield (and thus low cost) are implemented in case of organization of work of DPFU on the principle of "double helix" (see Fig), since in this case the failure of one or many pixels does not result in failure of the entire device.

- for the installation of the crystal (chip) DPFU only requires 2-3-pin package.

Sources of information

1. Sangster F.L. J The Bucket Brigade Delay Line. A Shift Register for Analogue Signals, Philips Tech. Review, 31, 97-110 (1970).

2. Krause G. Analog Speicherketle: Fine Are Schaltung Jum Speichern and Verzoegern von Signalen. Electronics Lett, 3, 544-546 (1967).

3. Carlo H. Sevuin and Michael F. Tompsett Charge Transfer Devices, Academic Press, Inc. New York, San Francisco, London 1975 pp.10-15.

Cseke, Mtomcat. Devices with charge transfer. Out in the World. 1978, p.12-14.

4. Murashev NR. "Dynamic memory". Patent of Russia №2147772, is) from 11.06.1997,

5. Murashev V.N., Saito T. "Serial dynamic functional device. Patent application No. PCT/EN 02/00457 dated July 21, 2003

6. Silicon-on-insulator Techology: Materials to VLSI, 2nd Edition by Jean-Pierre Colinge, Universite catholigye de Louvajn, Belgium. Kluwer Academic Publishers Boston/Dordrecht/London TK7871 35 S, 1997. 651.38.152-dc21 97-35777cip.PP-126, 134, 163.

Dynamic sequential function device containing a chain of series-connected cells, comprising a common bus, the power bus, the input and output, and the output of each cell is connected to the input subsequent to her cell, each cell includes a transistor, the capacitor, the first input impedance, the second load resistance, characterized in that the transistor cell is a MOS transistor, the gate of the MOS transistor is connected through a capacitor to the input of the cell and through the first input impedance to a common bus, its drain connected to the output of the cell and through the second load impedance to the bus power supply, its gate region a third additional resistance is connected to the shared bus, and a source connected to a common bus; during this delay time the activation of the MOS transistor (tass) exceeds the time constant of the charging capacitor (C) through the first input resistance (R1), i.e.,
tass>·R1,
and the value of works value of the capacitor (C), multiplied by ve is ichino input voltage (U I)exceeds the value of works value of the capacitance formed by the gate and substrate of the MOS transistor (CRFP), the value of the threshold voltage of the MOS transistor (UT)
UI·≫UT·RFP.



 

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