Double-port cell of random-access memory

FIELD: information technologies.

SUBSTANCE: device comprises two CMDS inverters, two recording transistors of n-type, two transistors for reading of n-type and reading transistor of p-type. Output of the first CMDS inverter is connected to input of the second CMDS inverter, to gate of the first reading transistor of n-type and via the first recording transistor is connected to direct data bus. Output of the second CMDS inverter is connected to input of the first CMDS inverter, to gate of reading transistor of n-type and via the second recording transistor of n-type is connected to complementary data bus. Gates of recording transistors of n-type are connected to address recording bus. The first and second reading transistors of n-type are connected serially between shift bus and reading bus. Reading transistor of p-type is connected parallel to the first reading transistor of n-type, and gate of the second reading transistor of n-type is connected to address reading bus.

EFFECT: improved efficiency of device.

1 dwg

 

The invention relates to the field of computer engineering and can be used to implement RAM in microprocessor systems

Known multiport cell RAM (U.S. Patent No. 6909662, Fig 1, G11C 8/00, 7/00, 8/16, NCI 265/230 .05, from 21.06.2005)containing two inverter with feedback, write port two MOS transistors are n-type with control of the address bus record and two data bus and an independent port reading, containing bus read and two series-connected transistor of the n - and p-types of control valves from one of the inverters and address bus read. Lack of memory is not a high performance due to the limited current reading through the p-type transistor. The closest technical solution to offer is a dual port memory cell (U.S. Patent No. 6917560, Fig.11, G11C 8/00, 8/16, NCI 365 /230.05, 12.07.2005). This device is adopted for the prototype contains two CMDP inverter with feedback, two transistors record n-type with control gates of the address bus record and two data bus and two of the read transistor of n-type, which are connected in series between the bus read and bus bias-controlled gates from one of the inverters and address bus read. The disadvantage of this device is limited to the performance, due to insufficient amount of current reading, since the current Citywest is determined by the transistor, which is on the gate load of the inverter and, therefore, increase of the size of the transistor to increase the current reading and increase reading speed leads simultaneously to decrease the recording speed.

The technical problem to be solved in the invention is to improve the performance of your device.

This objective is achieved in that the dual-port memory cell containing two CMDP inverter connected between the power bus and the bus of the earth, two transistors record n-type, the gates of which are connected to the address bus write, and the first and second read transistors of n-type, which are connected in series respectively between the tire offset and tire of reading the output of the first CMDP inverter connected to the gate of the first transistor of the read n-type, to the input of the second CMDP inverter and through the first transistor of the write-n-type is connected with a direct data bus, the output of the second CMDP inverter connected to the input of first CMDP inverter and a second transistor of the write-n-type is connected with the complementary data bus, the gate of the second transistor of the read n-type is connected to the address bus read, contains the read transistor p-type, which is included in parallel with the first tra what SISTROM read n-type and the gate of which is connected to vygodoi second CMDP inverter

Salient features in the specified set of features is the presence of the read transistor is p-type, which is included in parallel with the first transistor of the read n-type and the gate of which is connected to the output of the second CMDP inverter.

The presence of the proposed device, the above essential features provides a solution to a technical problem - improving the performance of your device.

Indeed, in the known device ports read and write are implemented on independent transistors are n-type. The write speed is determined by the largest capacitive load of the inverter, the output of which is connected to the gate of the read transistor of n-type. The current reading is determined by the read transistors of n-type, one of which is the gate load of the inverter, and hence increase the size of this transistor to increase the current and the speed of reading leads odnovremenno to increase the capacitive load of the inverter and reduce the write speed. In the inventive device with the same read transistors of the n-type current reading is increased due to the launch of the read transistor is p-type, which creates additional capacitive load only the inverter with the least load. When equal to the size of the read transistors of both types the largest p is recluseya load inverters is not increased and the performance on the recording is not reduced. Parallel connected transistors of the read n - and p-types not only provide more current reading than one n-type transistor, but in the reading process, provide a more constant value, which in General leads to an increase reading speed without reducing the recording speed. New balance sizes (downward) of the read transistors of the n - and p-types leads to higher performance as when writing and when reading.

The drawing shows a schematic diagram of the inventive dual-cell memory. The device comprises a first 1 and second 2 CMDP inverters, the first 3 and second 4 transistors record n-type, the first 5 second 6 the read transistors of n-type and the read transistor p-type 7.

CMDP inverters 1 and 2 connected between the power bus 8 and bus lands 9. The output of the first CMDP inverter 1 is connected to the input of the second CMDP inverter 2 to the gate of the first transistor of the read 5 of n-type and through the first transistor entries 3 is connected with a direct data bus 10. The output of the second CMDP inverter 2 is connected to the input of the first CMDP inverter 1, to the gate of the read transistor p-type 7 and through the second transistor recording 4 n-type is connected with the complementary data bus 11. The gates of transistors entries 3 and 4 of n-type is connected to the address bus write 12. The first 5 and second 6 the read transistors of n-type enabled the latter is therefore respectively between the tire offset 13 and the bus reading 14. The read transistor 7 of p-type is connected in parallel with the first transistor of the read 5 of n-type and the gate of the second transistor of the read 6 of n-type is connected to the address bus read 15.

Transistors entries 3 and 4 of n-type address bus write 12 and the data bus 10 and 11 make up the port of entry. The read transistors 5 and 6 of n-type and the read transistor 7 of p-type together with the address bus 15 and read bus read 14 represent the port are read.

The device operates as follows. In the status information storage outputs of the inverters 1 and 2, is enabled by the latch circuit, are two-rail static state. When writing 1 to direct the data bus 10 is formed of a single potential power rail, and the complementary data bus 11 - zero potential bus of the earth. On the address bus write 12 is fed to a single potential and transistors entries 3 and 4 of n-type open. The direct current from the data bus 10 nodal capacitance of the output of the first inverter 1 is charged to unit potential and current to the complementary data bus 11 nodal capacitance of the output of the second inverter 2 is discharged to 0. When writing 0 to a single potential is formed on the complementary data bus 11 and to direct the data bus 10 to the zero potential.

The reading mode is carried out in the preliminary formation on the bus reading 14 potential is high in the anti-shudder performance. On the address bus read 15 is also fed a high potential. A second read transistor n-type 6 opens. If the memory cell was recorded 1, the first read transistor 5 of n-type is open from output of the first inverter 1, and the read transistor 7 of p-type is open from output of the second inverter 2. Thus is formed a conductive circuit between bus 14 and read bus offset 13, consisting of a transistor 7 and parallel mccanny transistors 5 and 7. Current reading through this transistor circuit capacity of a bus read 14 is discharged to the potential of bus offset 13 that the read command is latched differential amplifier readout. The positive potential bus offset 13 other than 0 allows to reduce the difference of potentials on the bus reading 14 and to maintain a positive bias on the current electrodes of the transistors of the read n-type 5 and 6 to reduce their tanks, which amount also increases reading speed. Parallel connected transistors of the read n - and p-types 5 and 7 not only provide more current reading than one n-type transistor, but in the reading process, provide a more constant value, which in General leads to an increase reading speed without reducing the recording speed.

If the memory cell has been written to 0, the first read transistor 5 n-type C is open, since the output of the first inverter zero potential, and the read transistor 7 of p-type closed, as the output of the second inverter high potential. The initial bus state read 14 with high potential will not change.

Dual port memory cell containing two CMDP inverter connected between the power bus and the bus of the earth, two transistors record n-type, the gates of which are connected to the address bus write, and the first and second read transistors of n-type, which are connected in series respectively between the tire offset and tire of reading the output of the first CMDP inverter connected to the gate of the first transistor of the read n-type, to the input of the second CMDP inverter and through the first transistor of the write-n-type is connected with a direct data bus, the output of the second CMDP inverter connected to the input of the first CMDP inverter and through the second the transistor of the write-n-type is connected with the complementary data bus, the gate of the second transistor of the read n-type is connected to the address bus read, characterized in that it contains the read transistor p-type, which is included in parallel with the first transistor of the read n-type, and the gate of which is connected to the output of the second CMDP inverter.



 

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