Methods and device for reading complete scanning memory matrix

FIELD: information technology.

SUBSTANCE: complete scanning memory matrix includes several local bit lines and a global bit line. The method of launching the global bit line involves a step for connecting several local bit lines with the global bit line through several tristate devices, generation of a global selection signal for allowing operation of one of the several tristate devices and selection of the corresponding local it line for launching output of the tristate device allowed to operate. That way, the global bit line is statically launched so that serial bit reading having the same value read on the global bit line does not lead to switching of the state of the global bit line.

EFFECT: reduced power when reading the said matrix.

13 cl, 9 dwg

 

The technical field to which the invention relates.

The present invention relates, generally, to improvements associated with the reading matrix memory full scan, and, in more detail, to useful technologies for static run total (global) bit lines in the matrix memory full scan.

The level of technology

Matrix memory full scan uses a dynamic pre-charge and discharge when reading bits written in the memory cell. This standard technology is usually divided into two levels in order to minimize the capacity of the scattering introduced bit lines within the matrix memory full scan. The first level of the matrix memory full scan includes memory cells, pass transistors and the local bit line. A memory cell stores a binary value. The pass transistor is triggered digital reading (reading words) in order to discharge the local bit line, based on the contents of the memory cell. The local bit line is typically shared by multiple numeric tire of reading. The local bit line pre-highly charged so that the transition to the read memory could be detected. The local bit is the line provides the entrance to the second level.

The second level of the matrix memory full scan usually includes a number of inverters and a matching transistor pairs, each pair provided with entrance through one of the local bit lines. Matching transistors are connected dynamically pre-charged global bit line. This matrix memory called the matrix memory full scan, because the local and global bit lines must be run to ground, to recognize the value 0 is written in the memory cell. Reading sequential values 0 of the memory cell, the standard matrix memory full scan requires the prior charge and discharge the local and global bit lines. A preliminary charge of local and global bit lines must occur before it is approved by the numeric signal bus read. This discharge occurs because the value 0 is passed through the second level. Thus, the power consumed at the preliminary charge and discharge both local and global bit lines in the read process, while sequential values 0 are transmitted through the global bit line.

In addition, in the standard memory array full scanning scheme latching (holding circuit) or the dynamics-stat is ical Converter is usually added to the output of the global bit line, to ensure that the output will hold the estimated value of the global bit line. This additional circuit is the actual size of silicon crystal, which is the matrix of memory.

The invention

When considering its several aspects, the present invention recognizes the problem of additional power consumption caused by a precharge and discharge the global bit line in the standard matrix full scan over successive reads of memory cells that have a value of 0. To this end variant of implementation of the present invention includes a statically switching global bit line. This technology reduces the power consumption for sequential reads values 0 and makes this method which eliminates the need for retaining the scheme or the scheme of dynamic to static Converter on the output.

In one embodiment, the invention disclosed a method of running a global bit line. This method includes a stage on which to connect multiple local bit lines and global bit line through a variety of devices with three States. This method further includes the steps, which generated a total (global) signal selection, permitting work is one of many devices with three-state and choose the corresponding local bit line to run the output of allowed devices with three States. Thus, the global bit line statically launch so that sequential reads of bits having the same value read global bit line, would not the state transition of the global bit line.

A more complete understanding of the present invention, as well as additional features and advantages of the invention will be apparent from the subsequent detailed description and the attached drawings.

Brief description of drawings

Figure 1 shows an example wireless communication system, which can mainly be used in embodiments of the invention.

Figure 2 - circuit diagram of the read part of the system matrix memory full scan in accordance with one embodiments of the invention.

Figure 3 - timing diagram showing the static nature of the global bit line 2 in accordance with this embodiment of the invention.

Figure 4 shows details of one suitable device with three States presented in figure 2.

5 is an alternative implementation of the reading part of the system matrix memory full scan, presented at IG in accordance with this embodiment of the invention.

6 shows details of a device with three-state, suitable for use in figure 5.

Fig.7 shows an example of an alternative scheme for generating global select signal in accordance with an additional embodiment of the invention.

Fig is a block diagram showing the way static switch global bit line in accordance with the embodiment of the invention.

Fig.9 is a block diagram showing a method of reducing power, when sequentially read bits having the same value, the global bit lines within the memory in accordance with the embodiment of the invention.

Figure 2 - circuit diagram of the read part of the system 200 of the matrix memory full scan in accordance with the embodiment of the invention. This reading of the system 200 of the matrix memory full scan includes additional sets of master devices 210A-210B numeric bus read, distributed, dynamic member, OR 220 and the matrix memory 230 full scan, modified according to the invention. Sets specifies the devices 210A and 210B numeric bus read receive active-low, fully decoded signal numeric bus read and respectively connected with distributed dynamic is Kim element OR 220 and the sensor 230 memory full scan. Distributed dynamic element OR 220 connects to the matrix memory 230 full scan. Sets specifies the devices 210A-210B numeric tire of reading are optional, if the numeric signal bus read highly active.

For simplicity, only the set of master devices 210A numeric bus read and distributed dynamic element OR 220 will be described here in detail. A set of master devices 210A numeric tire of reading includes up to eight inverters, such as inverter 215. The inverter 215, for example, receives a signal 205 numeric bus read, and active-low signal 205 numeric bus read inverted and transmitted in a distributed dynamic element OR 220 and the matrix memory 230 full scan. Distributed dynamic element OR 220 includes sixteen matching of transistors, such as matching transistor 222, with eight of matching transistors 222 finish their outputs at a common point 227A branching, and eight other matching transistors 222 connect their outputs to a common point 227B branching and with four load transistors A, B, A, W. The outputs of the load transistors A, A end at a common point 227A branching. The outputs of the load transistors V, W end at a common point 227B branching. Distribution is lenny dynamic element OR 220 also includes a logical element AND-NOT 228. The logical element AND-NOT 228 is connected in parallel with transistors A, B hold. The General point 227A and 227B branching are connected with the logical element AND-NOT 228, which generates, as its output signal, the global select signal on the global line 250 of choice.

Distributed dynamic element OR 220 receives as input the voltage pre-charged impulse 223 low level for pre-charging the common point 227A branching through the load transistor A. As a General point of branching 227A pre-charged, and the signal 223 goes to a high level, the transistor A retention supports a common point of branching A in the logical 1 state so that you can recognize the transition state in the active logic 0.

On the other hand, the General point 227A and 227B branching can be disconnected by replacing the logical element AND-NOT inverter 228, as shown in the alternative embodiment described in figure 5. However, as will be recognized when discussing the case for figure 5, when connecting common points 227A and 227B branching through the logical element AND-NOT 228 the number of global lines of choice will be reduced by half. However, it is recognized that other connections between more than two distributed dynamic elements OR to reduce the number of global lines selection is also discussed in the present invention and that other logic designs can be implemented, in order to achieve the same results as these ideas.

It should be noted that the composite dynamic elements, OR such as composite dynamic element OR 220 may be made of silicon, to accommodate shared branching points 227A and 227B, interacting with each other, as shown in figure 2. Thus, a single channel wiring Vitruvian by matching the length of the run, which is useful to reduce the total number of channels of distribution.

Matrix 230 memory full scan includes a cell matrix memory c random access (RAM), such as cell 235 RAM. Each row of RAM cells connected to the same numeric bus read. A RAM cell in the column of RAM cells connected with other numerical tire of reading. As shown in figure 2, the column of the eight cells of the RAM ends of the local bit line 240A. Similarly the second column of the eight cells of the RAM is attached to another set of numeric tire of reading and ends in the local bit line 240B.

Matrix 230 memory full scan also includes a number of load transistors, such as a load transistor 245, a number of devices with three-state, such as logical element AND-NOT 255 tristate, and additional cell 260 retention. Load Tran the STO 245 receives the pulse 243 low level, pre-charging the local bit line, in order to pre-charge the local bit line 240A. The load transistor 245 supports the local bit line 240A in the logical state 1, subject to the availability of the preliminary charge, up until the logic state 0 is not read from the RAM cell. Devices with tri-state transmit output to the global bit line 253. These devices tristate receive input from two local bit lines, such as the local bit line 240A and 240B. These local bit lines transfer the contents of the read RAM cell when the corresponding numeric bus read is activated. Devices with three States permit operation corresponding global selection signals. For example, the logical element AND-NOT 255 tristate accordingly enables the global signal 250 selection.

The number of devices with three States used in the matrix memory full scan, according to the invention varies in accordance with the size of the memory full scan and the number of RAM cells, resulting in a device with three States. In General, the total number of devices with three-state, ntcan be expressed as follows:

nt=(RC)/bsub> r,(1)

where R is the number of rows of the matrix memory full scan, C - number of columns of the matrix memory full scan and brthe number of RAM cells, resulting in a device with three States. For example, in any embodiment, the logical element AND-NOT tristate 3232 system matrix memory full scan ntwould equal 32 bits 32 rows of columns divided by 16 RAM cells on the logical element AND-NOT with three States, and a total of 64 devices AND IS NOT tristate. For the configuration of the matrix memory full scan 6432 would be used to 128 devices AND IS NOT tristate. The number of devices AND IS NOT tristate used in a special column, ncexpressed as follows:

nc=R/br.(2)

Incidentally, ncalso equals the number of global selection lines used in this system.

Assuming that figure 2 shows a 6432 configuration, the matrix memory 230 full scan would contain 64 bus read, where each set of master devices numeric tire of reading has eight inverters to connect with eight numeric tire of reading, thus, in total amounts of the eight sets of eight sets of devices numeric tires. Two sets of master devices numeric tires would have joined with the respective dynamic element OR having sixteen matching transistors, and with sixteen rows 32 of the RAM cells. The local bit line would connect the eight cells of the RAM. Each column of the matrix 230 memory full scan would contain eight local bit lines, thus, in total 256 local bit lines. Each column of the matrix 230 memory full scan also would contain one global bit line for, in total, 32 global bit lines, each global bit line connected with eight local bit lines through four logical element AND-NOT tristate. It should be noted that other configurations of the size of the system matrix memory full scan supported without limiting embodiments of the invention.

When reading the number of the memory of one of the numeric signal bus read approved as signal 205 numeric tire of reading. For example, the inverter 215 inverts the signal 205 numeric bus reads and transmits this inverted signal 225, which is an active high signal with respect to the matching transistor 222, in order to consider the appropriate number of RAM cells, including the cell 235 RAM. Assuming, for example, h is about a common point 227A branching was initially pre-charged through the load transistor A, matching transistor 222 is activated, which reduces the overall point of branching A to ground or logic 0. Assuming that at most only one numeric bus read active at any time and, thus, the overall point 227B branching captures a logical 1, the logical element 228 AND does NOT transmit a logical 0 from a common point A branching to a logical 1 to unlock the logical element 255 AND NOT tristate.

At the same time the contents of the cell RAM 235 is transmitted to the local bit line 240A. Assuming that the load transistor 245 pre-loaded local bit line 240A through signal 243 preliminary charge and that if the contents of the cell 235 RAM has a logical 0, the local bit line is discharged to a logical 0. Unlocked the logical element 255 AND NOT tristate then passes the logical 0 from the local bit line 240A to a logical 1 on the global bit line 253. The inverter in the cell 260 retention inverts a logical 1 to logical 0 and transmits a logical 0, the output of 265. If you receive the next signal readout, which uses the global bit line 253, resulting reads the RAM cell containing a logical 0, then the global bit line 253 remains in the logical 1 state, without the need to power the, thus saving power consumption. The mode of operation of the readout part of the system matrix 200 memory full scan will be described in more detail when discussing Fig 3.

Figure 3 - timing diagram 300 showing the static nature of the global bit lines, such as the global bit line 253 figure 2 in accordance with the embodiment of the invention. The timing diagram 300 shows five signals, including signal 225 numeric bus read signal 243 pre-charging the local bit line (LBL), the signal 240A local bit line (LBL), global global select signal line 250 of choice and signal 253 global bit line (GBL).

For example, figure 3 will be described together with figure 2 for the situation where two logical 0 is sequentially read from the matrix memory 230 full scan. First load transistor 245 pre-fully charge the local bit line 240 in the logical state 1 at time 305. Similarly, the load transistors A, B pre-charged fully, the General point 227A and 227B branching in the logical 1 state. Numeric tire 225 reading now been approved during the 310, which leads to two dierent cases. First: the General point 227A branching brought to a logical 0 by discharge through a matching transistor 222. W is Roy: the contents of the cell RAM 235, which, as suggested, is a logical 0, is read, discharging LBL 240A to a logical 0.

Returning to the first case, the logical element 228 AND receives as an input device is a logical 0 from a General point of branching 227A, and as a common point of branching 227B has not been discharged, it remains in the logical 1 state. Thus, while signal 315 global select 250 is active to unlock the logical element 255 AND NOT tristate after LBL 240A was evaluated during 312.

Now, when the logical element 255 AND NOT tristate unlocked and he receives as an input device, a logical 0 on the local bit line 240A, and since no numeric bus reading corresponding to the set of master devices 210B numeric tires that have not been activated, the local bit line 240B remains in the logical 1 state. Therefore, while 320 global bit line 253 state is a logical 1 and the output 265 of the data RAM state is logic 0, to match the contents of the cell RAM 235.

During signal 321 250 selecting the global bit lines is impossible before pre-charged signal 243 local bit line will be unlocked during 322. During 323 local bit line 240A finished the pre is satisfactory charging through the load transistor 245, thus, it is pre-installed in the logical 1 state to the next active signal numeric tire of reading. During 325 activated subsequent numeric signal bus read, which again leads to two dierent cases. First: the General point of branching 227A given in the logical 0 state. Second: the contents of the cell 235 RAM, which continues to be able to logical 0, is read, discharging the load transistor 245 and translating LBL 240A in the state of logic 0 during 330.

Returning to the first case, the logical element 228 AND receives, as an input device logical 0 from a General point of branching 227A and, as a load transistor V was not discharged, it receives a logic 1 from a General point of branching 227B. Thus, during the 333 is an active global signal selection 250 to unlock the logical element 255 AND NOT tristate. The output of logic element 255 AND does NOT remain in the logical 1 state. Thus, the global bit line 253 remains in the logical 1 state, no transition, as it did during the 320, which leads to savings in power between subsequent reads by the same global bit line, where the value read is 0. This mode of operation, the global bit line 253 refers to the hundred and the practical operation. On the contrary, the local bit line 240A, as well as standard global bit line, dynamically switches each reading thanks to the pre-charging and discharging capacity of the local bit line regardless of the previous data read.

It should be noted that although the above example has been described in the context of two consecutive reads of the same RAM cell, the global bit line 253 will remain high for sequential reads any RAM cell with the same data that end in any logical element AND-NOT tristate connected to the same global bit line.

Figure 4 shows details of one suitable option implementation logic element 255 AND NOT tristate presented in figure 2. The logical element 255 AND NOT tristate includes inverters 405, the logical element 410 OR logical element 420 AND-NOT logical element, And 430, and an output transistor package including a load transistor 440 and the matching transistor 450. As described above, the logical element 255 AND does NOT receive, as input signals, the global signal selection 250 and the local bit line 240A and 240B and creates its output to the global bit line 253. The global bit line 253 is connected with the load is cnym transistor 440 and a matching transistor 450.

The load transistor 440 is connected to the output device logic element 420. The logical element 420 AND IS NOT connected to the output of logic element 410 OR the global signal 250 of choice. The logical element 410 OR connected with an inverter 405. The inverters 405 are connected to the local bit lines 240A and 240B.

Matching transistor 450 is connected with the output of logic element 430 I. Logical element 430 And is connected to the global signal selection 250 and the local bit lines 240A and 240B. The global bit line 253 has a status of a logical 1, or when the local bit line 240A or 240B are set to logical 0, and the global signal selection 250 has a logical 1 state. The global bit line 253 has a status of a logical 0 when the local bit line 240A and 240B and the global signal selection 250 are set to logical 1. In any other combination of values entered in the logical element 255 AND IS NOT, the value of the global bit line 253 will be determined unlocked logical element AND-NOT, which is also connected with it. If none of the logical elements AND IS NOT connected to the global bit line 253, not unlocked, the global bit line 253 will maintain the last value read from her cell 260 hold.

When using output the aqueous set, includes two transistors, the physical sizes of these transistors is smaller for a given load global bit line than the standard output sets with more than two output transistors. This advantage reduces the size of the PCB and a private capacity to the global bit line through the output transistors devices with three States.

Figure 5 - alternative implementation of the reading part of the system 200 of the matrix memory full scan in accordance with another embodiment of the invention. Reading part of a system 500 of the matrix memory full scan includes a setting device 510 numeric bus read dynamic elements 520 and OR matrix 530 memory full scan, modified according to the invention. Setting device 510 numeric bus read connect with dynamic element OR 520, and matrix 530 memory full scan. Dynamic element OR 520 is connected with the matrix 530 memory full scan through the global line 550 of choice.

The system matrix 500 memory full scan differs from the system matrix 200 memory full scan one set of master devices 510 numeric tires that provide input signals to a dynamic element 520 OR. One locale is th bit line 540 is connected to the global bit line 553 through the inverter 555 with three States and a separate global line selection, such as the global line 550 of choice used for each local bit line. The mode of operation of the system matrix 500 memory full scan is similar to the system matrix 200 memory full scan. If reference numbers are replaced to match the elements in figure 5, the discussion of the timing diagram in figure 3 is applicable also to figure 5.

6 shows details of a device with three-state, suitable for use as inverter 555 tristate presented on figure 5. The inverter 555 tristate includes an inverter 605, the logical element 620 AND-NOT logical element 630 And a load transistor 640 and the matching transistor 650. The inverter 555 tristate receives, as input signals, the global select signal 550 and the local bit line 540 and generates its output signal to the global bit line 553. The global bit line 553 is connected with the load transistor 640 and the matching transistor 650.

The load transistor 640 is connected with the output of logic element 620. The logical element 620 AND IS NOT connected to the output of the inverter 605 and the signal 550 global choice. The inverter 605 is connected to the local bit line 540. Matching transistor 650 is connected with the output of logic element 630 I. Logical element 630 And connected to the global signal is crimson 550 choice and the local bit line 540.

The global bit line 553 has a status of logical 1 when the local bit line 540 has a logical 0 state, and the global signal selection 550 has a logical 1 state. The global bit line 553 has a status of a logical 0 when the local bit line 540 and the global signal selection 550 are set to logical 1. In any other combination of values entered on the inverter 555 with three States, the value of the global bit line 553 will be determined unlocked inverter with three States, such as the inverter 555 with three States, for example, which is also connected to the global bit line 553. If none of inverters with three-state connected to the global bit line 553, will not be unlocked, the global bit line 553 will maintain the last value read from her through the cell 560 retention.

Fig.7 shows an example of an alternative arrangement for generating a global signal selection in accordance with the embodiment of the invention. An alternative implementation can be used to generate a global select signal using the encoded memory address and not the decoded address and dynamic elements, OR 2 and 5. A variant example of implementation, presented in Fig.7, while the reading indicates the part of the 3232 system 700 matrix memory full scan. The system 700 includes a 532 decoder 705, a set of master devices numeric tire of reading, such as setting the device 710 numeric bus, and a 3232 matrix 730 memory full scan, modified according to the invention.

The decoder 532 connects with sets of sets of devices numeric tire of reading. To simplify the display, only one set of master devices 710 numeric tires presented on Fig.7. Sets specifies the device numeric bus read are connected to the matrix 730 memory full scan. 532 decoder receives the encoded memory address, S5-S1bit. The most significant bit, for example, S5connected with the logical element 755 AND NOT three-state through the inverter 720 to generate a signal global select global line 750A choice. Although not presented, the global (total) line 750A choice is also connected with the logical element AND-NOT with three States corresponding to the other bit 31 in a series of 32 bits, in order to transfer all the word of 32 bits, when only numeric bus read is activated. The logical element 755 AND NOT tristate is connected to the two local bit lines, each local bit line supports eight RAM. Global line 750A selection enables the logical element AND-NOT tristate, supporting Junior order, S5=0.16 ranks of memory.

The most significant bit, S5also directly connected with the logical element 758 AND NOT with three States, which is also connected to the global line select 750V. It should be noted that the global line select 750V also connects with the logical elements, AND NOT with three States, not represented, which correspond to another 31 bit in the string of 32 bits. Also, the global line select 750V unlock logic elements AND NOT with three States, which support higher order S5=1.16 rows of memory.

It should be noted that other logical combinations encoded address bits to generate a global selection signals are assumed by the present invention and may vary according to other configurations of the matrix memory full scan. For example, 6432 matrix memory full scan would have used 664 decoder. Using a variant implementation of the logical element AND-NOT with three States, such as in figure 2, the two most significant bits of the six encoded address bits 664 decoder would be used to run all the logic gates AND tristate. In General, the number of most significant address bits required to control the logical elements AND NOT with three States, , is determined by the expression:

n=log2(R/br),(3)

where R is the number of rows of the matrix memory full scan and br- the number of RAM cells serviced by the device with three States. For example, in the embodiment, the logical element AND-NOT tristate 6432 system matrix memory full scan n would equal a log2(64 number/16 RAM cells on the logical element AND-NOT three-state), which is 2 bits. Through option exercise inverter tristate 6432 system matrix memory full scan n would equal a log2(64 series/8 RAM cells on the logical element of the inverter with three-state), which is 3 bits.

Fig algorithm, showing the method 800 static switch global bit line in accordance with the embodiment of the invention. At step 810 a lot of local bit lines connected to the global bit line through a variety of devices with three States. In figure 2, for example, two local bit lines are connected through the logical element AND-NOT with three States with the global bit line. Figure 5, for example, one local bit line is connected through an inverter with three States with the global bit line. At step 820, the global signal of the selection gene is associated, to allow the work to one of the many devices with three States. In figure 2, for example, the global signal selection for the logical element AND-NOT tri-state is generated when one of the numeric bus read from two sets of master devices numeric bus is activated. Figure 5, for example, the global signal selection for the inverter with three States is generated when one of the corresponding set of numeric tire of reading is enabled.

At step 830, the corresponding local bit line is selected to start the output device enabled device with three States. In the embodiment 2 AND IS NOT tristate distributes active local bit line as described. In the embodiment, figure 5 inverter with three-state distributes the corresponding local bit line, as described.

Fig.9 is an algorithm illustrating a method of reducing power in sequential reading of bits having the same value on the global bit lines within the memory in accordance with the embodiment of the invention. At step 910, the global signal selection is generated to translate the global bit line to the first level. As for time 315 figure 3, for example, the global signal selection 250 moves to the active high ur the level, to enable the logical element AND-NOT tristate 255, after the local bit line 240A was evaluated during 312. At step 920 the first bit read from the memory. As for time 320 figure 3, for example, the global bit line 253 is transferred to a high value after the logical element AND-NOT 255 was evaluated. At step 930, the second bit is read from the memory. The value of the second bit has the same value as that of the first read bit. As for time 333 figure 3, for example, the global signal selection 250 moves to the active high level to re-enable the logical element AND-NOT tristate 255. At step 940, the global bit line is maintained at the first level during the second reading bits without a transition. As for time 333 figure 3, for example, the global bit line 253 remains on the same level as it was during the 320.

While the invention disclosed in the context of a variety of embodiments, it will be recognized that a wide variety of implementations may be used ordinary specialists in the field of technology related to the above discussion and the claims which follows.

1. Way to run a common bit line of the matrix memory full scan containing phases in which
with whom are United by a number of local bit lines with a common bit line through a variety of devices with three States;
generate a common select signal to enable one of many devices with three States and
choose the corresponding local bit line to run the output of allowed devices with three-state, whereby sequential reads of bits having the same value read from the shared bit line, does not lead to a change of status General bit line.

2. The method according to claim 1, in which the output of the common bit line connected to the cell in the hold.

3. The method according to claim 1, wherein the step of generating further comprises the steps on which
link multiple transistors, ending at a common point of branching;
receive the signal read in one of the many transistors and
skip shared branching points for the resolution of one of the many devices with tri-state in response to receiving the signal read.

4. The method according to claim 1, wherein the step of generating further comprises the step on which
use bits from the encoded memory address for generating a common signal selection.

5. The method according to claim 1, wherein the selected device with tri-state is a logical element AND-NOT tri-state.

6. The method according to claim 1, wherein the selected device tristate inverter is three SOS is ojaniemi.

7. The method according to claim 1, wherein a device with three States from a variety of devices tristate includes an output transistor with a set of two transistors.

8. A method of reducing power reading when reading consecutive bits having the same value for the common bit lines within the memory containing phases in which
generating a common signal SEL to move the shared bit line on the first level, and the select signal enables operation of the device with three States;
read the first bit of memory that has some value;
read the second bit of the memory having the same value as the first bit; and
support a common bit line at the first level during the second reading bits without a transition to the second level.

9. The method of claim 8 in which the step of generating further comprises the steps on which
link multiple transistors, ending at a common point of branching;
receive the signal read in one of the many transistors and
skip shared branching points to activate common signal selection.

10. The method of claim 8 in which the step of generating further comprises the step on which
use bits from the encoded memory address for generating a common signal selection.

12. The method according to claim 8, in which the selected device tristate inverter is three-state.

13. The method of claim 8, wherein the logical element AND-NOT tristate includes an output transistor with a set of two transistors.



 

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