Memory device

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering and automation and can be used in memory devices made from large width memory units. The memory device enables use in the memory field of the memory units of large information capacity and large memory width L>1 with pre-packaging of the array of K bit data words after their transformation into an array of N bit code words and their recording in the memory field. The memory device has a corrector for correcting errors in bit words, N memory units with number of data outputs in each equal to L, a common address bus, N separate buses for recording L-bit words, an operation mode common bus and an initialisation common bus, a switch, port registers, port control decoder and an internal dataway.

EFFECT: design of a multiport device, increased reliability of the device, detection and correction of errors in its memory field.

2 dwg, 1 tbl

 

The invention relates to computer technology and automation and can be used in a storage device, executed by the memory of a large capacity.

Known storage device in which the recording, storage and reading of data words of bit K [1-4]. Where the field memory of these devices is performed on the blocks of memory capacity L=1 using for detection and correction of single error converting data word bit in the code word bit N (N>). However, in a storage device, a field memory which is executed on the memory capacity L>1, the application of a Hamming code is not used.

The closest in technical essence to the proposed device is a memory device on the memory blocks with width L=1 [2], allows the detection and correction of single errors using Hamming code. In these storage devices is the parity of certain groups of bits of the code word, and the number of control bits, providing the localization space errors using the error syndrome, satisfy the following relations :

N-K≥log2(N+1),

where N is the number of bits of the code word;

K is the number of bits of the information word;

(N-K) - the number of control bits.

In General SL the tea is a storage device with correction of single errors contains memory blocks with width L=1, register of information words, the convolution blocks certain groups of digits included in the concealer and implement the summation of the digits of the information word modulo 2 to determine the key bits. The code word is formed from known information word and the received control bits. The generated code word of N bits is written to the register code words and can be used for transmission or storage in the absence of errors.

Check code words for errors by using convolution blocks included in the corrector, the same groups of bits of the code words modulo 2 together with the corresponding control discharge and the formation of the syndrome of the error indicating the location of the error. The Hamming code is applied in the case when the most likely single errors.

Functional scheme of permanent and semi-permanent mass storage devices, large data capacity, a field memory which is arranged on a memory of a large capacity (L>1, typically L=8), described without the use of a Hamming code [3, 4]. However, to apply the Hamming code in a storage device, a field memory which is arranged on a memory of a large capacity L>1, in a traditional building cannot, as it can be damaged, losing its efficiency, the entire memory block, which will lead to the WSS turn errors of multiplicity L, fix that by using Hamming code is impossible.

In modern management techniques and information processing systems, information redundancy and information redundancy is used to improve many of the technical characteristics and above all the reliability of their functioning, their precision and performance [5].

Ways of incorporating information redundancy diverse. These methods include:

- redundancy internal information of the language devices of the processing, transmitting and storage of data using error correcting codes;

- redundancy of data arrays in the structure of the data files;

- redundancy of the file structure in the memory of computers, automated and automatic control systems and information processing, etc.

Without data redundancy in one form or another, it is impossible to organize information process. The situation is further complicated by the fact that information without redundancy, you cannot use other types of backup. For example, structural redundancy in the automated control systems and information processing requires duplication of information stored in the operating registers and other operating units of the main processor; it is especially important to provide secure storage for Tannoy and operational information in a storage device, subsystems and systems large information capacity. The importance of reliable processing, transmission and storage of information increases significantly with the increasing complexity of tasks and switching in the nanosecond region of manufacture and use.

Information redundancy with special packaging information storage devices, subsystems and systems reduces:

streams of failures and malfunctions, as not all the faults and failures of their elements become failures and failures of complex products. If the consequences of the refusal or failure of the item cannot fix due to information redundancy, they are not considered failures and failures of complex products;

- the recovery time by reducing the amount of work impaired by the refusal or failure. This reduces the time spent on repetition impaired part of the work, and significantly increases the time to failure or failure of the product;

- the recovery time by reducing the detection time and Troubleshooting.

The technical result of the invention is to provide a multiport mode of the device, increasing its reliability, detection and correction of errors in the field memory, uses a block of memory large capacity L>1 with a preliminary transformation of the array of data words of width K in the array of code words is Otradnoe N, their packaging and writing in the field memory. In each memory block are written the same bits of the array of code words, allowing detection and error correction using Hamming code.

The technical result of the proposed resolution is achieved in that in the storage device, having in its composition concealer, N memory blocks with the number of information outputs each equal to L, the total line address N individual routes of entry of L-bit words, the common line and the common line initialization, connected to the memory blocks, put the switch registers ports, additional decoder control ports and the internal data highway, L outputs of each memory block is connected to the switch with L groups of N-bit outputs, each of which is connected with the corresponding port register input initialization which is connected to one of the L outputs of the additional decoder control ports, all equipped with private address input and its input initialization is connected with the common line initialization, the N-bit outputs of each of the L registers ports connected to the internal data highway, which is connected to the input of the corrector, the input initialization which are connected to a common line initialization.

Use of information the th redundancy with special packaging permanent and operational information, used in the proposed device, and outlines new directions for building products with the ability to correct errors greater multiplicity, and not just a single error.

The substance of the proposed solution is illustrated by figure 1 and figure 2 and table 1.

Figure 1 presents a functional diagram of a storage device that uses memory blocks with L information outputs, when L>1. The number of memory blocks is equal to N.

Figure 2 shows a functional diagram of the storage device when N=7 and L=4, i.e. applied (7, 4) code.

The proposed storage device (1) comprises a corrector 1, N memory blocks 2 bit depth L. the memory Blocks 2 are connected to a common line address 3. Each memory block 2 is associated with one of N individual routes of entry of L-bit words 4. The composition of the storage device includes highway mode 5 and the common line initialization 6 connected to each memory block 2.

L outputs of each memory block 2 is connected to the switch 7. The switch 7 is equipped with L groups of outputs N bits each. The outputs of each group of outputs of the switch 7 is connected to the corresponding port register 8, the input initialization 9 which is connected to one of the additional outputs of the decoder control ports 10. Input initialization 11 additional decoder pack is Alenia port 10 is connected with the common line initialization 6 of the storage device. Additional decoder control ports 10 are connected to an individual line address select 12 registers of port 8.

N outputs of each register port 8 are connected to the internal data highway 13, connected to the corrector 1, input initialization 14 which is connected with the common line initialization 6.

The device operates as follows.

Writing information to the memory blocks 2 technical means of storing operational information will be provided as usual in the composition of these products. Writing information to a memory 2 for storing different kinds of permanent information produced or by the manufacturer or user, or in a normal mode in the hardware. The overall highway initialization 6 signal initialization, preparing for the work of the memory blocks 2, additional decoder control ports 10 and corrector 1.

On a shared line mode 5 comes the signal recording mode. When entering code address on the General line of the address 3 in each block memory 2 select memory elements that store individual routes of entry of L-bit words.

In the reading mode on the General highway initialization 6 signal initialization, preparing for the work of the memory blocks 2, additional estimator control ports 10 and corrector 1.

On a shared line mode 5 signal arrives read mode. When entering the code addresses on the shared line address 3 L outputs of each memory block is formed of L-bit word input to the switch 7, the outputs of which are formed of L N-bit words.

The generated N-bit words are only in the port register 8, input initialization 9 which is the initialization signal received from the corresponding output of the additional decoder control ports 10.

The corresponding port register 8 select additional decoder control ports 10 for admission on his individual line of address 12 code address port register 8.

On the N outputs of the selected register port 8 is formed of an N-bit word supplied to the internal data highway 13, and with the last - corrector 1. Corrector 1 checks the code of the N-bit word received on it for errors. In the absence of errors the code word output from the offset 1 is used for the purpose. If there are errors corrector 1 localizes space errors, corrects them, preparing a code word to use. Corrector 1 forms a word in the presence of the input initialization 14 signal initialization.

It is appropriate to consider the implementation of the proposed solutions to specific p is the iMER, for example, when N=7 and L=4 (figure 2). You may want to record the following information words: 1101, 0011, 1010, 1001. After conversion of the information words will get the following code words:

The symbol "-" denotes the digits of the three groups of code words, each of which is determined by the check bits by summing the marked bits of a certain group of code words in module 2. Moreover, the number of control bits of the code word corresponds to 2jwhere j=0, 1, 2.

The remaining code words obtained in this way are of the form:

This example corresponds to a storage device with four ports, as shown in figure 2, which depicts seven memory blocks 2 (N=7), each of which has four outputs (L=4). The outputs of the memory blocks 2 labeled DO-digit number in which the high order bit represents the number of memory block 2, and the younger the number of its output.

The switch 7 has seven groups of four inputs of each discharge and four output groups of seven bits. The outputs of the switch 7 are marked in a similar way, but with the difference that the value of them will be different in accordance with the operation of the switch 7. In table 1 the numbers of outputs of the memory blocks 2, their values after the recording of the code words in the memory blocks and 2 and values of outputs of the switch 7.

Each group of seven outputs of the switch 7 is connected to the corresponding port register 8, the initialization which is performed by the initialization signal at the input of the initialization 9 with the corresponding output of the additional decoder control ports 10.

Before readout mode let on a particular code addresses in each memory block 2 is written the same bits of code words (see table 1 and figure 2 from top to bottom, i.e. in the memory 2 will be the words:

in the first - 0000, the second - 1110, in the third - 1101, in the fourth - 0101, the fifth - 0110, in the sixth - 1000, in the seventh - 1011.

When entering on the General line of the address 3 of the corresponding code address from the outputs of the switch 7 in the absence of single errors are formed four code words of seven bits:

These code words are received at the inputs of the registers of port 8, but recorded only in one of them according to the initialization signal received at the corresponding input initialization 9 selected register port 8. The initialization signal is generated on one of the additional outputs of the decoder control ports 10.

The code word from the selected register port 8 through the internal data highway 13 is supplied to the corrector 1. Corrector 1 analyzes the received code word errors, producing the syndrome of the error. what if the syndrome of the error is equal to zero, the code word is output offset 1 for use.

The definition of the syndrome of the error for each code word is performed by the corrector 1 through summation of discharges of certain groups modulo 2, together with their control discharge. The process of computing the syndrome of the error of each code word can be illustrated as follows, keeping in mind that the least significant bit of a particular group of bits of the code word of it and control the discharge of this group is to the right in the controlled group, and senior level group on the left. Moreover, the number of control digit is equal to 2jwhere j=0, 1, 2:

Now suppose that each codeword has an error in one category and code words have the form:

After receipt of these code words corrector 1 for each word formed by the syndrome of the error indicating the number of the category in which there was an erroneous symbol (1 or 0). The code word is corrected by inverting the erroneous discharge. After that, the code word is output corrector 1 and can be used for the purpose.

The process of defining the syndrome of the error can be illustrated as follows:

The error syndrome indicates the number of the discharge, which occurred about the flexible, counting from right to left, meaning that the number of low-order code word is equal to 1.

After correcting errors in each code word used for the purpose.

At a constant address input 12 additional decoder control ports 10 and receive a new code addresses on the shared line address 3 output previously selected register port 8 will see the following code word.

The new address input 12 additional decoder control ports 10 under the old code of the address on the common bus of the address 3 is selected, the corresponding port register 8 and its output will form another code word.

The above example illustrates the possibility of using Hamming code for detecting and correcting single errors in the multiport memory storage device, is performed on the memory blocks 2 with a large number of information outputs (L>1), opening new possibilities for the development of reliable devices, subsystems and systems for storing information and other technical means with a large number of information channels.

Sources of information

1. Potemkin Istinctively nodes of digital automation. - M.: Energoatomizdat, 1988, s, 141-146.

2. Prospects for the development of computer technology. 11 kN.: Ref. the textbook /Under the editorship Usmerava. KN: Technology is mnikowie storage device/ Abikini, Veeranam, Gdiii, Cry. - M.: Higher. HQ., 1989, p.7, 57, 98, 136-140.

3. Semiconductor LSI storage devices; Guide /Rev, Nowbeen, Ajugoides and others; Ed. by Aeuginosa and Ungerova. - M.: Radio and communication, 1986, p.57-58.

4. Petrosyan O.A., Trump IA, Koledov L.A., Schetinin SCI Circuitry permanent storage devices. - M.: Radio and communication, 1987.

5. Circassians GN. Reliability of hardware-software complexes. The tutorial. - SPb.: Peter, 2005, 108-109.

Table 1
The designation of the outputs of the memory blocks 2, 2The value of the bits at the outputs of memory blocks 2, 2The value of the bits at the outputs of the switch 7, 2
Group 1Group 2Group 3Group 4
D01100
D01200
D01300
D01400
D02111
D02211
D02311
D02400
D03111
D03211
D03300
D03411
D04100
D04211
00
D04411
D05100
D05211
D05311
D05400
D06111
D06200
D06300
D06400
D07111
D07200
D073 11
D07411

A storage device, having in its composition corrector of errors in bit words, N memory blocks with the number of information outputs each equal to L, the total line address N individual routes of entry of L-bit words, the common line and the common line initialization, connected to the memory blocks, characterized in that the device has entered the switch, the port registers, the decoder control ports and the internal data highway, L outputs of each memory block is connected to a switch having N groups of L-bit inputs and L groups of N-bit outputs, each of which connected to the corresponding port register input initialization which is connected to one of the L outputs of the decoder control ports, equipped with their own line address, and its input initialization is connected with the common line initialization, the N-bit outputs of each of the L registers ports connected to the internal data highway, which is connected to the input of the offset errors in bit words, the progress of the initialization of which are connected to a common line initialization moreover, the L-bit words read from the code addresses that came on the General line of the address, at the same time into N groups of L-bit inputs switch simultaneously forming L N-bit code words that appear simultaneously on the N-bit outputs of the switch, the code word is recorded only in the port register, the input of which initialization signal initialization with one of the outputs of the decoder control ports in accordance with the address code, which came with its own line address decoder control ports.



 

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