Integrated power supply voltage converter

FIELD: electrical engineering.

SUBSTANCE: integrated power supply voltage converter is intended for efficient conversion of power supply voltage for low-capacity and low-voltage devices that operate from batteries and accumulators to voltages that are less than voltages of chemical power supply sources. Circuit of integrated power supply voltage includes the following components: substrate for circuit arrangement, output unit connected to power supply source and generating output signal, control unit, which controls output unit by means of feedback, unit of low-frequency filter, function of which is to level output signal received from output unit, control unit is equipped with source of reference voltage, voltage divider, clock signal generator and error detector, besides voltage divider transforms signal from reference voltage source and sends it to input of error detector, where signal is also supplied from output unit as well, and further from error detector control signal arrives to permitting input of clock signal generator, and output unit is arranged as based on switched capacitors in the form of two cascades connected in parallel, the first of which comprises capacitor (17), one p-channel transistor (18) and three n-channel transistors (19, 20, 21), the second cascade comprises capacitor (22), p-channel transistor (23) and three n-channel transistors (24, 25, 26), besides transistors of output unit cascades are controlled by two paraphrase signals from clock signal generator "input 1" and "input 2" so that "input 2" signal is sent to transistors (18, 20, 21) and (24), and signal "input 1" is sent to transistors (19, 23, 25, 26), transistors are connected so that depending on level of "input 1" and "input 2" signals, which may either be high or low, at the moment of time, when "input 1" signal is of high level, and signal "input 2" is of low level, current passes through transistors (18, 19) and capacitor (17) from power supply source to output, besides capacitor (17) is in charging phase, and through transistors (25, 26) and capacitor (22) from common bus to output, besides, capacitor (22) is in discharging phase, and at the moment of time, when "input 1" signal is of low level, and signal "input 1" is of high level, current passes through transistors (20), (21) and capacitor (17) from common bus to output, besides, capacitor (17) is in discharging phase, and through transistors (23, 24) and capacitor (22) from power supply source to output, besides capacitor (22) is in charging phase, and at the same time, both in charging or discharging phase of capacitors (17) and (22) current flows in one direction towards outlet of output unit.

EFFECT: achievement of low output voltages and improved efficiency factor at low energy consumption.

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The invention relates to computing, and in particular to integrated circuits of the inverter supply voltage.

Integrated voltage Converter power supply is designed for efficient conversion voltage low-power low-voltage devices that operate on batteries and accumulators, to voltages that are lower than the voltage of the chemical power sources. Modern devices powered by batteries, such as any Autonomous sensors operate at supply voltages of less than 1 V. the existing converters supply voltage is not designed to convert voltage to such low values. An example of such a Converter is the Converter DC uses to convert lithium batteries [1]. Unfortunately, [1] chemical sources is not possible to obtain a voltage lower than voltage sources, i.e. less than 1 Century

Closest to the invention, the technical solution is the schematic of the DC-to-DC [2], including:

the substrate, on which runs the scheme,

- output unit connected to the power source and generates an output signal that is performed on the group of n-channel MOS field effect transistors, connected in parallel with a common gate, drain and source,

- the control unit is sending the output unit via feedback contains a source of reference voltage, a voltage divider, the clock generator, the determinant of the error, the pulse width modulator,

block shaper connected between the control unit and the output unit and affecting the output block under the action of the control unit contains a bipolar transistor, comprising a group of n-channel MOS field effect transistors of the output block, and one n-channel MOS field effect transistor, the switching-off group of the n-channel MOS field effect transistors of the output block,

the fuse that disables the scheme in excess of the permissible values of voltage, current, temperature.

Functional diagram of the DC Converter according to the prototype [2] is illustrated in figure 1, where 1 control unit, 2 - unit shaper, 3 - output unit 4 to the external power supply, 5 - fuse. Figure 2 shows the output block, and figure 3 - control unit, where 6 is the source of reference voltage, 7 - voltage divider, 8 - clock generator, 9 - detection of errors, 10 - modulator the pulse width.

The lack of technical solutions used in the prototype [2], is the high range output voltage - 2-4, high power consumption, the value of which follows from the functional circuit and is not less than 10 mW, the efficiency is less than 50%, since the output unit vypolnjaete the transistors using an external inductance.

The present invention is to obtain a technical result consists in achieving low output voltages up to 1 and increasing efficiency above 50% at low power consumption - less than 1 mW, due to the use of the output block, performed on switched capacitors failure in the control unit from the use of the pulse width modulator, and add a block of low-pass filter.

The well-known purpose of the low - pass filter smoothing of the signal [3].

To achieve the mentioned technical result in the Converter circuit DC [2], including:

the substrate, on which runs the scheme,

- output unit connected to the power source and generates an output signal

control unit, managing the output unit through feedback add:

- unit low-pass filter whose function is to smooth the output signal derived from the output of the block

the control unit complete source of reference voltage, a voltage divider, the clock generator and the determinant of the error, and the voltage divider converts the signal from the source of reference voltage and transmits it to the input of the determinant of the error, to which is fed the signal from the output unit, and further determinant of Osh is the side by the control signal at the enable input of the clock generator,

- and the output unit performs on switchable capacitors in the form of two stages connected in parallel, the first of which contains a capacitor 17, one of the p-channel transistor 18 and three n-channel transistor 19, 20, 21, the second stage includes a capacitor 22, the p-channel transistor 23 and three n-channel transistor 24, 25, 26, while the transistors of the cascade output unit controlled by two two-rail signals from generator signals "WH" and "uh" so that the transistors 18, 20, 21, and 24 signal WH", and the transistors 19, 23, 25, 26 signal VH", the transistors included so that depending on the level of the signals VH" and "WH", which can be either high or low, at the time when the signal "WH high level, and the signal "VH low level, current flows through the transistors 18, 19 and the capacitor 17 from the power source to the output, the capacitor 17 is in the form of charging, and through the transistors 25, 26 and the condenser 22 from the shared bus to the output, the capacitor 22 is in the form of discharge, and at the time when the signal "VH low level, and the signal "WH high level, current flows through the transistors 20, 21 and the capacitor 17 from the shared bus to the output, the capacitor 17 is in the form of discharge, and through the transistors 23, 24 and capacitor 22 from the power source to the output, the capacitor 22 is located phase charging, and at the same time and in phase charging, and in the phase of discharge of the capacitors 17 and 22, the current flows in one direction on the output of the output block.

Functional diagram of an integrated inverter power proposed in the invention, depicted in figure 4, where 11 is the control unit, 12 - output unit 13 is a low-pass filter 4 to an external power source.

Figure 5 illustrates an output unit for switching the capacitor, consisting of two stages, where 14 is the first stage including a capacitor 17, three n-channel MOS transistors 19, 20 and 21 and a p-channel MOS transistor 18, 15 - second stage comprising a capacitor 22, three n-channel MOS transistors 24, 25 and 26 and one p-channel MOS transistor 23.

Figure 6 depicts a functional diagram of the control unit, where 6 is the source of reference voltage, 7 - voltage divider, 16 - clock generator, 9 - detection of errors.

Figure 7 shows the timing diagram of clock signals VH and VH removed from the clock generator 16. The signals VH" and "WH" have the same frequency and amplitude but are out of phase and do not overlap.

The device according to the present invention operates as follows.

The voltage divider 7 of the control unit 11 converts the signal from the reference-voltage source 6 and passes it to the input identifier error 9 on the W signal V output with the output of block 12, and then the control signal with the identifier error 9 is supplied to an enable input of the clock generator 16.

Transistors 18, 19, 20, 21, 23, 24, 25, 26 the output unit 12 switches the clock signals VH" and "WH" (7)received from the clock generator 16 of the control unit 11. At the time when the signal "VH low level, and the signal "VH respectively high, the capacitor 17 cascade 14 is in the phase of the discharge and the condenser 22 cascade 15 - phase charging. When this capacitor 17 connected in parallel low-pass filter 13, and a capacitor 22 connected in series low-pass filter 13. At the time when the signals VH" and "WH change levels on the opposite, the capacitor 17 of the first stage 14 moves into a phase of charge and is included consistently low-pass filter 13, and the capacitor 22 of the second cascade 15 shifts the phase of the discharge and is connected in parallel low-pass filter 13. Thus, in each time interval between switching signals VH" and "WH the capacitor of one of the cascades charging a capacitor and another cascade discharging, transferring accumulated during the phase of charging energy to the load, while in the case of charging, and in the case of discharge of the capacitors 17 and 22, the current flows in one direction on the output of the output unit. Output current (current PE is eavey to the load) is twice the input current, transmitted power source and the output voltage V - two times less than the input voltage V. If the output voltage V drops below the preset level corresponding to the voltage at the voltage divider 7, the determinant of errors 9 outputs a signal including the clock generator 16. If the voltage at the output V exceeds the voltage at the voltage divider 7, the determinant of errors 9 outputs a signal that disables the clock generator 16, the efficiency of the integrated inverter supply voltage is determined only by the current of the determinant of the error.

The ability to create an integrated voltage Converter power supply with high efficiency and low power consumption at low output voltages is provided by execution of the output block on switched capacitors unlike the prototype, where the output unit is operating on external inductance, requiring high currents control. Also winning efficiency is achieved by turning off the clock generator 16 and the output unit 12 in the absence of output current.

Literature

1. Patent Application Publication No WO 2007/141722 A1.

2. United States Patent No 5610503, Mar.11, 1997.

3. Art circuitry. Horowitz P., hill, U., M.: Mir, 1998.

Integrated inverter supply voltage, comprising a substrate, on which runs the scheme, given the th block, connected to a power source and generates an output signal, the control unit, managing the output unit through the feedback, wherein the add block low-pass filter whose function is to smooth the output signal derived from the output unit, the control unit complete source of reference voltage, a voltage divider, the clock generator and the determinant of the error, and the voltage divider converts the signal from the source of reference voltage and transmits it to the input of the determinant of the error, to which is fed the signal from the output unit, and further with the determinant of the error control signal is supplied to an enable input of the clock generator, and the output unit performs on switchable capacitors in the form of two stages connected in parallel, the first of which contains a capacitor (17), one p-channel transistor (18) and three n-channel transistor (19, 20, 21), the second stage includes a capacitor (22), the p-channel transistor (23) and three n-channel transistor (24, 25, 26), while the transistors of the cascade output unit controlled by two two-rail signals from generator signals "WH" and "uh" so that the transistors 18, 20, 21, and 24 signal VH", and the transistors 19, 23, 25, 26 signal VH", the transistors included so that depending on the level of the signals VH" and "WH", which can be either high or low, at the time when the signal "WH high level, and the signal "VH low level, current flows through the transistors 18, 19 and the capacitor 17 from the power source to the output, the capacitor 17 is in the form of charging, and through the transistors 25, 26 and the capacitor 22 from the shared bus to the output, the capacitor 22 is in the form of discharge, and at the time when the signal "VH low level, and the signal "VG" high level current flows through the transistors (20, 21) and a capacitor (17) from the shared bus to the output, and the capacitor (17) is in the phase of discharge, and through the transistors (23, 24) and the condenser (22) from the power source to the output, and the capacitor (22) is in the phase of charging, and at the same time and in phase charging, and in the phase of discharge of the capacitor (17) and (22) the current flows in one direction on the output of the output unit.



 

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