Integral system and manufacture method

FIELD: machine-building.

SUBSTANCE: invention related to flowing media ejection device and to the device control electrical chain. Half-conductor system contains an undercoat, which has first surface, first insulation material, located on at least the first surface segment, and first insulation material contains many holes, which forms a route to the first surface, a first conducting material, located on the first insulation material, in a way that many holes basically are free of the first conduction material, a second insulation material, located on the first conduction material and partly on the first insulation material, in a way that many holes basically are free of the second insulation material, and second conduction material, located on the second insulation material and inside of the many holes, in a way that some part of the second conduction material, located on the second insulation material, has electrical contact with the undercoat.

EFFECT: invention has higher technical requirements at manufacturing cost decrease.

60 cl, 9 dwg

 

Cross references to related applications

[0001] This application claims the priority of provisional application U.S. No. 60/613871, filed September 28, 2004

Background of the invention

[0002] the Market of electronic devices requires constant increase performance while reducing costs. To meet these requirements, it is desirable to produce components that contain a variety of electronic devices, more effectively, and in accordance with the higher technical requirements of the design.

[0003] One type of electronic device is a device on the transistor with the structure of a metal-oxide-silicon. These devices are transistors with the structure of a metal-oxide-silicon are formed in large quantities on a single substrate such as a silicon substrate. The problem during the operation of such devices at high voltages is that continuous operation may cause the formation of a number of electron-hole pairs at the junctions of the transistor, for example, the transition drain-gate. Electron-hole pairs, if they form a fairly large concentration of charge can reduce the threshold voltage of the transistors, or may lead to the inclusion formed in the substrate parasitic lateral bipolar transistor.

[0004] Two warring the factors in the design and manufacture of electronic devices are improved performance and reduced cost. Often these two factors are directly opposite each other, since the formation of more accurate geometries and additional structures requires additional processing and masks, which increases the cost of the devices. On the other hand, the reduction processing and masks can cause problems with performance or failure to provide work within operational requirements, because some patterns can be excluded from the electronic device.

Brief description of drawings

[0005] the Professionals in the art will easily understand the features of the invention from the following detailed description of exemplary variants of the embodiment illustrated in the attached drawings, on which:

[0006] figure 1 shows a view in section of the device of ejection of the fluid according to one variant embodiment;

[0007] figure 2 shows a view in section of the device of ejection of the fluid according to other variant embodiments;

[0008] figure 3 shows a disassembled view in section of the device ejection of the fluid of figure 1 according to one variant embodiment;

[0009] figure 4 shows a circuit diagram of a circuit used to selectively control the ejection of the fluid according to one variant embodiment;

[00010] figure 5 shows the block diagram of the process Faure is investing device ejection of fluid according to one variant embodiment;

[00011] figure 6 shows the block diagram of the process of forming the device ejection of fluid according to other variant embodiments;

[00012] figure 7 shows the block diagram of the process of forming the device ejection of fluid according to other variant embodiments;

[00013] in Fig shows a top view of the device of the ejection of the fluid according to one variant embodiment;

[00014] figure 9 shows the node ejection of fluid according to one variant embodiment.

Detailed description of drawings

[00015] Referring to figure 1, there is shown a view in section of the device of ejection of the fluid according to one variant embodiment. The semiconductor device 5 is formed on and/or in the substrate 10, which is preferably silicon, but can be used and other substrates known to specialists in this field. The substrate 10 is processed using traditional methods of processing semiconductor for forming one or more zones 12 and 14 having different concentrations of impurities, for example, active regions, which form a transistor or diode. In this variant embodiment, where the semiconductor device 5 includes field-effect transistors with the structure of a metal-oxide-semiconductor (MOS) transistors or MOSFET), the active zone may include formed in the substrate 10 of the area with the eye and the source.

[00016] Over the surface of the substrate 10 is a layer 15 of gate oxide. On top of the layer 15 of gate oxide is a semiconductor layer 20, for example, formed of polysilicon. In some areas over the semiconductor layer 20 is a passive layer 25, for example phosphorothioate glass. In other areas over the semiconductor layer 20 is conductive layer 30. However, there may be used, and other structures with a conductive layer.

[00017] In a variant embodiment, shown in figure 1, conductive layer 30 includes a resistive material such as tantalum-aluminum material, which is a conductive material, for example aluminium. It should also be noted that the conductive layer 30 is also located on top of pestiviruses layer 25. In addition, the materials used to form the resistive material and/or conductive material can vary and depend on the application and specifications.

[00018] the Passivating layer 40 is located on top of the conductive layer 30 to isolate and protect the conductive layer 30. Passivating layer 40 may be formed from one or more of silicon carbide and silicon nitride, or of multiple layers of each of them, or their combinations. In addition, for pestiviruses layer 40 can be used with other materials or combinations thereof,

[00019] In the layer 15 of gate oxide, the semiconductor layer 20, pestiviruses layer 25, the conductive layer 30 and pestiviruses layer 40 is formed with a number of holes 45, which allows conducting layer 50, which is also located on top of pestiviruses layer 40, in contact with the surface or if the surface is partially removed, other portions of the substrate 10. In one variant embodiment of the conductive layer 50 is in contact with areas of the body of transistor devices formed in the substrate 10. In these embodiments, the embodiment of the body area may be p-doped region, however, may be used and other ways of doping.

[00020] In one variant embodiment, the holes 45 formed in them, the contacts are formed as close as possible to the active areas or devices formed in the substrate, without affecting the operation of this device or active areas. Accurate positioning may depend on substrate type and concentration of dopant in the active areas. In addition, the number of contacts depends on the number of active regions or devices formed in the substrate. In one embodiment, the embodiment may have one contact on each formed in the substrate device. In some embodiments of embodiment No. of contacts may be a function of power is formed in the substrate of the device, the concentration of dopant in the active regions and the substrate material.

[00021] the Criterion of direct contact with the body of the MOS transistor can be used to avoid increasing the number of electron-hole pairs at the interface of the drain/gate, which, in turn, may reduce the likelihood that a field MOS transistor switches in the open state due to small leakage currents, secured at its gate.

[00022] In some embodiments of the incarnation direct contact can be made between one or more transistors formed in the substrate 10. In these embodiments, the embodiment of the contact can be made near the area of origin of one or more transistors. In these embodiments, the embodiment of the contact area of the source and the body can be performed at the same or at different times. In a variant embodiment, where the semiconductor device 5 is a device ejection (ejection) of the fluid, direct contact may exist between the transistor logic circuit and a transistor control circuit, which result in the ejection elements.

[00023] the Resistor 60 and passivating layer 40 is protected from damage due to, for example, the collapse of bubbles in the chamber 75 of the fluid after the ejection of the fluid from the nozzle 80 cavitat the traditional layer 85, which is located on top of pestiviruses layer 40. In some embodiments, embodiments of the cavitation layer 85 contains a metal selected from the group consisting of tantalum, tungsten and molybdenum.

[00024] To create a chamber 75 and the nozzle 80 through which can actinovate (discarded) fluid is provided to allow the layer 70, as shown in the form of a barrier layer 72 and the layer 74 of the nozzles. Usually all the other layers disposed on the substrate 10 prior to the application nozzle layer 70. Allow the layer 70 can be a single or multiple layer(s) of polymers, epoxies, metals, etc. are Known several methods, materials and structure to create a nozzle layer 70, and they can be used with the structure of figure 1.

[00025] Referring to figure 2, there is shown a view in section of the device of ejection of the fluid according to other variant embodiments. The device ejection of the fluid of figure 2 is essentially similar to shown on figure 1. However, in some areas the surface of the substrate 10 is a protective oxide 90. Protective oxide 90 is provided near the regions 95 of the contact through which the conductive layer 50 may contact the substrate 10. Protective oxide 90 usually provides a greater barrier to diffusion than the gate oxide 15.

[00026] Although figures 1 and 2 provide descriptions of the variants of embodiment of the device is ist ejection of the fluid, however, you can use other semiconductor devices and structures that have similar configurations and designs. For example, such structures will have to allow the layer 70, and the cavitation layer 85, and piscivorous structure, which is different in structure and/or material from pestiviruses layer 40.

[00027] Referring to figure 3, there is shown a disassembled view in section of the device ejection of the fluid of figure 1 according to one variant embodiment. The hole 45 extends from the upper surface pestiviruses layer 40 to the surface of the substrate 10. Conductive layer 50, which contains a resistive layer 115 and the conductive layer 120 located on top of the resistive layer 115 is in contact with the surface of the substrate 10. You can see that some areas of the conductive layer 50, which lie on top of pestiviruses layer 25, the conductive layer 30 and pestiviruses layer 40 are in electrical contact with those areas of conductive layer 50, which are in physical contact with the surface of the substrate 10. Essentially can be created stable contact with the substrate, which provides advantages in terms of spurious inclusion of devices formed in the substrate 10.

[00028] Additional structural feature of the variant embodiment shown in figure 3, is that the resistive layer 105, routashi layer 110 and a passive layer 40 form a stepped design (topography), if you look at the perspective view in section. This allows to simplify production. In other embodiments, embodiments may use other configurations.

[00029] Referring to figure 4, it shows the schematic circuit 150 is used to selectively control the ejection of the fluid according to one variant embodiment. Ejection element 100 is connected to the power source 105 and the drain of the transistor 110. The source of transistor 110 is connected to ground 115. The gate of the transistor 110 is connected to the source of transistor 122 and the drain of the transistor 125. The source of transistor 125 is connected to ground 115. The gate of the transistor 125 is connected for admission to him first signal 130 management. The gate of the transistor 122 is connected to the admission to it of the second signal 135 management, and its gate connected for receiving his signal 140 addressing.

[00030] In some embodiments, the embodiment can be formed in contact with areas of the body area between the source of transistor 110 and the area of origin of any of the transistors 122 or 125. In some embodiments of the incarnation, where each ejection element is driven using circuit 150 depicted in figure 4, the contact with the body can be performed in each circuit 150 or some of the circuits 150.

[00031] Referring to figure 5, there is shown a block diagram of the process for the formation of the project for a device ejection of fluid according to one variant embodiment. The substrate, for example, the substrate 10 may be doped p-impurity in the case of the process of forming the n-channel MOS structure (NMOS), the block 200. However, the substrate can be doped n-impurity in the case of the process of forming the p-channel MOS structure (PMOS). Then over the surface of the substrate provide the material of gate oxide, block 205. After ensuring material gate oxide provide a semiconductor material such as polysilicon, on top of this material gate oxide, block 210. On top of a semiconductor material to provide an insulating material such as phosphorothioate glass block 215.

[00032] After providing the insulating material in the insulating material to form one or more through holes (interconnects), block 220. For example, one or more through holes can be formed in those areas where it may be desirable to form contact with the body of the transistor. Through holes can be erased to the surface of a semiconductor material provided in block 215. After forming one or more through holes to provide a first conductive layer over the insulating material and one or more through holes, the block 220. One or more through holes then pietraviva so that removes not only navigating the th material in one or more through holes, but semiconductor material that lies under one or more through-holes, the block 230. In this variant embodiment is formed the gate oxide still remains in the through holes. In one variant embodiment of the process of protravlivanija is a process of reactive ion etching.

[00033] After the conductive material and the semiconductor material is removed, the conductive material provide a passivating material, block 235. In some embodiments, embodiments of passivating material does not provide one or more through holes. In other embodiments, the embodiment of passivating material is applied in the through holes and then removed. Then the gate oxide remaining in the through holes, etched, so that the through holes were opened to the substrate, the block 240. Then provide a second conductive material which is in contact with the substrate in the through holes, block 245. Then provide additional layers, which are necessary to form the semiconductor device unit 250.

[00034] Referring to Fig.6, there is shown a block diagram of the process of forming the device ejection of fluid according to other variant embodiments. The substrate, for example, the substrate 10 may be doped p-impurity in the case of NMOS process block 260. However, the substrate can be also doped with n-impurity in the case of PMOS process, as described with reference to figure 5.

[00035] On the substrate to form one or more areas of contact, block 265. One or more areas of contact can be formed, for example, causing the semiconductor material on the gate oxide, which is located on the surface of the substrate. Then next to the contacts provide a protective oxide, block 270. Alternatively, the protective oxide may be provided so that the holes remain where may be formed contacts.

[00036] Over the contacts and the protective oxide provide an insulating material such as phosphorothioate glass, block 275. Then form one or more through holes through the insulating material, the block 280. Through holes form lying on top of one or more contact areas. Thus, the through holes can correspond to those areas where you need to perform contact with the substrate or with areas where there should be shaped contacts of the transistor.

[00037] After forming the through holes provide a conductive material atop an insulating material in the through holes, block 285. Conductive material in the through holes and, optionally, other areas etched, block 290. In one variant embodiment, when the etching of the conductive material in the through-hole is also etched, at least, h is the terrain of contacts. Etching at least part of the contacts can be made, for example, by protravlivanija using the process of reactive ion etching. In some embodiments the embodiment of the process of the second etching can be used after the first etching in order to remove any remaining material of the contact.

[00038] After etching the conductive material to provide a second insulating material on the first conductive material, the block 295. In one variant embodiment of the second insulating material provide so that it does not fill the through holes or is not included in them. In other embodiments, the embodiment of the second insulating material may be provided in the through holes, together with the provision of the first conductive material. The second insulating material provided in the through-holes can then be removed using known processes.

[00039] After providing the second insulating material to provide a second conductive material atop the second insulating material in the through holes, the block 300. The second conductive material to provide pass-through holes so that the areas of the second conductive material provided in the through-holes are in contact with the substrate and provides electrical contact area and the second conductive material, lying on top of the second insulating material. Then may be provided with an additional passivating material over the second conductive material and other parts of the device, block 305.

[00040] the Variant of the embodiment represented in figure 5, can be changed, eliminating unit 255 and using only the protective oxide. In this variant embodiment, the block 260 is to provide a protective oxide over the entire area of the substrate, where it is necessary to form patterns. In addition, the block 280 may include pietrapiana the first conductive material so that the etched beneath the through holes of the protective oxide, providing contact with the substrate. Alternatively, it may be a single unit process for oxide removal prior to providing the first conductive material and the standard etching process used in block 180.

[00041] Referring to Fig.7, there is shown a block diagram of the process of forming the device ejection of fluid according to another variant embodiment. In the variant embodiment in 7 blocks 320-340 essentially identical blocks 200-215 and 225 described with reference to figure 5. However, instead of forming the through hole in the first insulating material before providing the first conductive layer, as in figure 5, a through hole is formed by etching the via, the first conductive layer and the first insulating layer in one unit process, i.e. block 345. After forming these through holes of the blocks 330 to 340 essentially identical blocks 235-245 described with reference to figure 5.

[00042] As can be seen from figure 4-6, number of processing units do not need to increase, and in fact the number of blocks are essentially the same. In addition, since it can be used the process of protravlivanija, in some embodiments the embodiment of the actual processes used to form the structure in contact with the body, are the same as without it. In addition, since the formation of the holes not used for further processing, i.e. other than the etching of the conductive layer, there is less likelihood of what will happen inaccurate alignment or diffusion in the substrate, which would be the case if he used the additional processing for the formation of contact with the substrate.

[00043] In some embodiments, embodiments of the methods described with reference to figure 4 and 6, pietrapiana may be such that the portions of the substrate are removed together with the conductive semiconductor layer and a layer of gate oxide. This approach can be used, for example, in the case when the contact with the body of the substrate through the region of the device, which was doped as the area of the source of the transistor. Then may be secured second Provo is AMI the layer so so he was in contact with the body area of a substrate, where the substrate was etched.

[00044] In Fig shows the enlarged view in perspective of a variant embodiment of the printhead 400. Printhead 500 in this variant embodiment has numerous features, including regional ledge 505 for the regional supply of fluid to the resistors (or extractors fluid) 510. The printhead may also have a recess 515, which is partially formed into the surface of the substrate. This printhead also shows the slot or channel 520 for supplying fluid to the resistors 510 and/or the number of holes 525, feed the fluid to the resistors 510. In one variant embodiment, thermal printhead 500 may be at least two of the described features of figure 1. For example, the printhead 500 is formed only feed holes 525 and the slot 520, while the marginal ledge 505 and/or the recess 515 no. In another variant embodiment in printhead 520 formed regional ledge 505 and the slot 520, while the recess 515 and/or the feed holes 525 are missing. Can also be provided by different combinations of these features with other features or completely different features.

[00045] figure 9 shows a schematic illustration of an exemplary print cartridge 600,which can be used in the exemplary printing device. Print cartridge consists of a printhead 602 and the housing 604 of the cartridge, which supports the printhead. Although this print cartridge 600 is used only one printhead 602, other variations of the embodiment may include the use of multiple print heads on a single cartridge.

[00046] the Print cartridge 600 is made with self-contained (built-in) the source of fluid or ink in the housing 604 of the cartridge. Other configurations of the print cartridge may alternatively or additionally be configured to receive fluid from an external source. Specialists in this field will be clear to other exemplary configuration.

[00047] Described herein patterns of a semiconductor device applicable to a wide range of semiconductor devices and can be made of various semiconductor materials. Therefore, although in the above description describes several variants of embodiment of a semiconductor device implemented on silicon substrates described herein and depicted in the drawings, the methods and structures can also be implemented in gallium arsenide, Germany and other semiconductor materials. Accordingly, described herein and depicted in the drawings, the methods and structures are proposed on the found those devices made on a silicon semiconductor materials, and will include those devices fabricated in one or more of the available semiconductor materials and technologies available to specialists in this field of technology.

[00048] in Addition, although in the illustrated embodiments, the embodiment shown the presence of specific areas of the p - type and n-type, it is important to understand that the basic principles of the invention are equally applicable to semiconductor devices in which the conductivity types of the various regions were the opposite, for example, to provide a device complementary illustrated device.

[00049] in Addition, although the illustrated variants of the embodiment shown in the two-dimensional types, where different regions have a depth and width, it is important to understand that these regions are illustrations of only a portion of a single cell of a device that may include a number of such cells arranged in a three-dimensional structure. Accordingly, when manufacturing on a real device, these areas will have three dimensions, namely length, width, and depth.

[00050] it Should be noted that the drawings are not to scale. In addition, in the drawings, the highly doped region (usually with concentrations of impurities at IU is 1×10 19the impurity atoms/cm3marked pole (for example, n+or p+), and low-alloy region (usually at concentrations of less than about 5×1016the impurity atoms/cm3) - a minus sign (for example, p-or n-).

[00051] the Component of the active zone, for example the source and the drain, isolation MOSFET (field-effect transistor with a structure of metal-oxide-semiconductor) is traditionally made using two mask layers, islet layer and the sealing layer. Islet layer is used for forming a hole in a thick protective oxide "grown" on the substrate. The sealing layer is used to create a gate of the transistor and forms samoobladanie and separate active zones (source and drain) of the transistor within the islet holes thick protective oxide.

[00052] Although the principles of the invention have been described expressions, characteristic structural features and method-related steps, it should be understood that the appended claims is not limited to the described specific signs or stages. On the contrary, the specific features and steps are disclosed as preferred forms of implementing the principles of the invention.

1. A semiconductor structure that contains
a substrate having a first surface;
the first insulating m is a material predetermined, located on at least a part of the first surface, and the first insulating material contains many holes, forming a path to the first surface;
the first conductive material located on the first insulating material and the first conductive material is located so that the number of holes, essentially free from the first conductive material;
the second insulating material located on the first conductive material and the areas of the first insulating material and the second insulating material is located so that the number of holes, essentially free of the second insulating material; and
the second conductive material located on the second insulating material and within a set of holes so that some portion of the second conductive material located on the second insulating material is in electrical contact with the substrate.

2. Semiconductor structure according to claim 1, additionally containing gate oxide and polysilicon material lying below the first insulating material, whereas the number of holes, essentially free from polysilicon material and the gate oxide.

3. Semiconductor structure according to claim 1, additionally containing a protective oxide beneath the first insulating material, if e is ω many holes free of the protective oxide.

4. Semiconductor structure according to claim 1, in which the second conductive material includes tantalum.

5. Semiconductor structure according to claim 1, in which the second conductive material includes a resistive section and a transfer section located on this resistive section.

6. Semiconductor structure according to claim 1, additionally containing multiple doped regions formed within the substrate, each of the multiple apertures formed near one of the various doped regions.

7. Semiconductor structure according to claim 6, in which the multiple doped regions forming the transistors.

8. Semiconductor structure according to claim 1, additionally containing a slot of the control fluid medium between the said first surface and second surface of the substrate.

9. Semiconductor structure according to claim 1, in which the second insulating material contains phosphorothioate glass.

10. Semiconductor structure according to claim 1, in which the first conductive material includes a resistive section and a transfer section located on this resistive section.

11. Semiconductor structure according to claim 1, in which a number of holes form a path to the area under the first surface of the substrate.

12. The method of forming a semiconductor device, which includes
forming the first is of insulating material over the first surface of the substrate;
forming at least one hole in the first insulating material, and the hole forms a path to the substrate;
forming a first conductive material over the first insulating material;
etching the first conductive material so that the hole, forming a path to the substrate is essentially free of the first conductive material and the first insulating material;
forming a second insulating material over the first conductive material; and
forming a second conductive material over the second insulating material, the second conductive material is formed in the hole and is in contact with the substrate.

13. The method according to item 12, further comprising before forming the first insulating material forming a third insulating material and polysilicon material on the substrate and below the first insulating material, thus forming the aforementioned at least one hole includes forming holes through the polysilicon material to the third insulating material.

14. The method according to item 13, in which the etching of the first conductive material comprises etching the third insulating material.

15. The method according to item 13, further comprising etching the first conductive mater is Ala and includes etching the third insulating material after etching the first conductive material.

16. The method according to item 12, further comprising forming a third insulating material and polysilicon material on the substrate and below the first insulating material, thus forming the hole includes forming the holes so that the path is between the third insulating material and the upper surface of the first insulating material.

17. The method according to item 12, in which the formation of the second conductive material includes forming a resistive area and a conductive area on this resistive section.

18. The method according to item 12, further comprising forming a protective oxide on the substrate before forming the first insulating layer.

19. The method according to item 12, in which the etching of the first conductive material includes reactive ion etching the first conductive material.

20. The method according to item 12, in which the substrate contains a number formed of transistors, forming at least one hole in the first insulating material includes forming the aforementioned at least one hole between two of the multiple transistors.

21. The method according to item 12, in which the substrate contains an area that has a first dopant concentration, and another area that lies beneath this region and the other region has a second, different dopant concentration, and the etching of the first conductive material so that the hole forms a path of the substrate includes etching the mentioned areas so that there is a path referred to another area.

22. The method according to item 12, in which the etching of the conductive material includes etching the first conductive material so as to form a path to the region of the substrate beneath the first surface.

23. The method of forming a semiconductor device, which includes
the formation of many areas of contact over the surface of the substrate;
forming insulating material over many areas of contact;
forming at least one hole through the insulating material and the site at least one contact from a variety of areas of contact;
forming a first conductive material over the first insulating material so that the said at least one hole, essentially free from the first conductive material;
forming a second insulating material over the first conductive material; and
forming a second conductive material over the second insulating material, the second conductive material is formed in the hole and forms an electrical contact with the substrate.

24. The way the about item 23, in which the formation of the mentioned at least one hole includes forming the aforementioned at least one hole after forming the first conductive material, so that the said at least one hole formed in the first insulating material and the first conductive material.

25. The method according to item 23, in which the formation of the second conductive material includes forming a resistive section and the third conductive area located on this resistive section.

26. The method according to item 23, in which the formation of areas of contact includes forming a third insulating material and polysilicon material on a substrate.

27. The method according to p, in which the formation of the insulating material and the polysilicon material includes forming these insulating material and polysilicon material on essentially the entire surface of the substrate.

28. The method according to item 23, in which the substrate contains a number formed of transistors, and thus the formation of the mentioned at least one hole in the first insulating material includes forming the aforementioned at least one hole between two of the multiple transistors.

29. The method according to item 23, in which the formation of contact areas includes the formirovanie third insulating material and polysilicon material in those areas, where it is necessary to form the aforementioned at least one hole, and the formation of protective oxide in areas near the third insulating material and polysilicon material.

30. The method according to item 23, in which the substrate contains an area that has a first dopant concentration, and other area lying below the area, and another area has a second, different concentration of dopant, forming at least one hole includes removing the field, so that a path referred to another area from the upper surface of the insulation material.

31. The method of forming a semiconductor device, which includes
forming insulating material over the first surface of the substrate;
forming a first conductive material over the first insulating material;
etching the first conductive material for forming at least one hole, which forms a path to the substrate, which is essentially free of the first conductive material and the first insulating material;
forming a second insulating material over the first conductive material; and
forming a second conductive material over the second insulating material, the second conductive material form in which the opening and the contact regions of the substrate.

32. The method according to p, further comprising before forming the first insulating material forming a third insulating material and polysilicon material on the substrate, and etching the first conductive material comprises etching the polysilicon material.

33. The method according to p, in which the formation of the second conductive material includes forming a resistive section and the third conductive area located on this resistive section.

34. The method according to p, further comprising before forming the first insulating layer, the formation of protective oxide on the substrate.

35. The method according to p, in which the etching of the first conductive material includes reactive ion etching the first conductive material.

36. The method according to p, in which the substrate contains a number formed of transistors, and forming at least one hole in the first insulating material includes forming the aforementioned at least one hole between two of the multiple transistors.

37. The method according to p, further comprising forming one or more nozzle layer over the second conductive material.

38. The method according to p, in which the substrate contains an area that has parvo the concentration of dopant, and another area that lies beneath this region, and another region has a second, different dopant concentration, and the etching of the first conductive material so that the hole forms a path of the substrate includes etching the mentioned areas so that there is a path referred to another area.

39. The method according to p, in which the etching of the conductive material includes etching the first conductive material so as to form a path to the region of the substrate beneath the first surface.

40. The device ejection of fluid containing
a substrate having a first surface;
the first insulating material located on at least a part of the first surface, and the first insulating material contains a number of holes formed to the first surface;
the first conductive material located on the first insulating material and the first conductive material is located so that the number of holes, essentially free from the first conductive material;
the second insulating material located on the first conductive material and the areas of the first insulating material and the second insulating material is located so that the number of holes, essentially free of the second insulating material;
the second conductive material is, located on the second insulating material and within a set of holes so that some portion of the second conductive material, located on the second insulating material is in electrical contact with the substrate;
the number of chambers formed in the material on the surface of the substrate; and
multiple holes formed to provide passage of fluid from these chambers through the many holes.

41. The device ejection of fluid by p, in which the first insulating material contains a gate oxide, and the structure further comprises a polysilicon material located on the material of the gate oxide and polysilicon material is so many holes, essentially free from polysilicon material.

42. The device ejection of fluid by p, in which the first insulating material includes a protective oxide, and the portions of the first insulating material formed where each hole of the many holes that contain the gate oxide.

43. The device ejection of fluid by p, in which the second conductive material includes tantalum.

44. The device ejection of fluid by p, in which the second conductive material includes a resistive section and a transfer section located on this resistive participants who that is

45. The device ejection of fluid by p, optionally containing multiple doped regions formed within the substrate, and each of the many holes formed near a variety doped regions.

46. The device ejection of fluid by p, optionally containing a slot of the control fluid medium, which flow associated with many cameras.

47. The device ejection of fluid by p, in which the second insulating material contains phosphorothioate glass.

48. The device ejection of fluid by p, in which the first conductive material includes a resistive section and a transfer section located on this resistive section.

49. The device ejection of fluid by p, in which many holes form a path to the area under the first surface of the substrate.

50. The device ejection of fluid containing
substrate;
the first insulating material atop at least part of the first surface, and the first insulating material is composed of a number of holes between sites, ensuring contact with the substrate;
the first conductive material atop at least part of the first insulating material and the first conductive material is located so that many holes, what about the fact, free from the first conductive material;
the second insulating material atop at least part of the first conductive material and areas of the first insulating material and the second insulating material is located so that the set of holes is essentially free of the second insulating material;
the second conductive material atop at least part of the second insulating material and located within a set of holes so that some portion of the second conductive material, located on the second insulating material is in electrical contact with the substrate; and
many elements-resistors made with the possibility of heating the fluid in response to the passage of current, and the set of resistors is connected with the first conductive material so that the first conductive material is current.

51. The device ejection of fluid on item 50, optionally containing gate oxide and polysilicon material lying below the first insulating material, and many holes are essentially free from polysilicon material and the gate oxide.

52. The device ejection of fluid on item 50, optionally containing protective oxide beneath the first insulating material, and the set of holes is obody from the protective oxide.

53. The device ejection of fluid on item 50, in which the second conductive material includes tantalum.

54. The device ejection of fluid on item 50, in which the second conductive material includes a resistive section and a transfer section located on this resistive section.

55. The device ejection of fluid on item 50, optionally containing multiple doped regions formed within the substrate, and each of the multiple apertures formed near one of the various doped regions.

56. The device ejection of fluid under § 55, in which multiple doped regions forming the transistors.

57. The device ejection of fluid on item 50, optionally containing a number of chambers of a fluid medium, each of which is located above one resistor from a variety of resistors, and a nozzle arranged to enable the ejection of fluid from the chamber of the fluid through the nozzle.

58. The device ejection of fluid on item 50, in which the second insulating material contains phosphorothioate glass.

59. The device ejection of fluid on item 50, in which the first conductive material includes a resistive section and a transfer section, lying on top of this resistive section.

60. The device ejection of fluid on item 50, wherein a set of open the second form the path to the realm below the surface of the substrate.



 

Same patents:

FIELD: physics; radio.

SUBSTANCE: invention relates to microelectronics. The method of making self-aligned transistor structures involves formation of a buried layer of second type conductivity in a semiconductor substrate of first type conductivity, formation an epitaxial layer of second type conductivity on the semiconductor substrate, formation of a first dielectric, doping the epitaxial layer through the first dielectric with impurities of first type conductivity, formation of a second dielectric layer, opening windows in the first and second dielectrics at the site of the future collector contact to the buried layer, at the site of the future contact to the inactive region of the base, at the site of the future emitter region, formation of a third separating dielectric on vertical walls, formation of screening layers in windows, formation of a fourth dielectric, opening windows in the first, second and fourth dielectrics under a deep insulating region and a window in the fourth dielectric over the screening layer lying at the site of the future collector contact to the buried layer, formation of an etching slit in the window of the epitaxial, buried layers and partially of the substrate under the insulating region, and in the window at the site of the future collector contact to the buried layer, by etching the screening and epitaxial layers, formation of a first dielectric in the slit, formation of opposite-channel regions at the bottom of the slit, formation of a third dielectric in the slits, local etching of the first and third dielectrics with the bottom of the slits under the contact to the substrate and collector contact to the buried layer, filling the slits with polysilicon, planarisation of polysilicon to the fourth dielectric lying on the horizontal surface of the substrate, local doping of the polysilicon contact to the substrate with an impurity of first type conductivity, local doping of the polysilicon collector contact to the buried layer with an impurity of second type conductivity, formation of a dielectric on the polysilicon, local etching of the fourth dielectric on the horizontal surface of the substrate, local removal of the fifth dielectric on the polysilicon at the site of the collector contact to the buried layer and the contact to the substrate, local doping with an impurity of first type conductivity of the polysilicon contact to the substrate and screening layer at the site of the contact to the inactive region of the base, local doping with an impurity of second type conductivity of the polysilicon collector contact to the buried layer and screening layer at the site of the emitter region, thermal annealing of the structure to form regions of the structure, wiring the structure with polycide of a high-melting metal.

EFFECT: higher packing density of transistor structures due to self alignment of the regions of the transistor structure and self alignment of insulating regions with the contact to the substrate and self alignment of the latter with regions of the transistor structure; completely self-aligned technology also increases reproducibility of device parametres.

3 cl, 8 dwg, 1 ex

FIELD: chemistry.

SUBSTANCE: invention relates to the technology of making power silicon transistors, specifically to methods of treating carbide-silicon pipes used in high-temperature processes in diffusion furnaces. Impurities are removed from carbide-silicon pipes by using a solution containing hydrofluoric acid HF, hydrochloric acid HCl and deionised water H2O in ratio of 1:1:3.5. Treatment time is 20±5 minutes. At the end of treatment, the pipes are washed in deionised water at room temperature for 30±5 minutes. Quality of treatment is determined using indicator paper.

EFFECT: complete removal of different impurities and contaminants.

3 ex

FIELD: physics; conductors.

SUBSTANCE: invention relates to the technology of making power silicon transistors, specifically to methods of processing silicon crystals. In the method of processing silicon crystals, the said crystals are processed in an etching agent after high temperature processes, where the etching agent consists of nitric acid HNO3, hydrofluoric acid HF and acetic acid CH3COOH, with components in ratio of 3:2:8, temperature of the solution of 25°C, and duration of processing of 8±2 minutes. At the end, the crystals are washed in deionised water at room temperature for 25±5 minutes. Percentage yield of crystals is 98%.

EFFECT: invention provides for complete removal of different impurities and pollutants, cuts on time and temperature of processing.

FIELD: physics; conductors.

SUBSTANCE: invention relates to the technology of making power silicon transistors and semicoductor devices, particularly to methods of processing silicon-carbide tubes, used in high-temperature processes in diffusion furnaces. The method of primary annealing silicon-carbide tubes involves two-step processing: at the first step, temperature - T=400°C, nitrogen consumption - N2 - 600 l/h, time - τ=90 minutes, temperature increase - T=1200°C, nitrogen consumption - N2 - 600 l/h, rate of temperature increase - 5°C per minute; at the second step temperature - T=1200°C, oxygen consumption - O2 - 600 l/h, hydrochloric acid HCl - 20 l/h, processing time - τ=8 hours, temperature fall - T=850°C, nitrogen consumption - N2 - 600 l/h, rate of temperature fall -3°C per minute. At the end of processing, the tubes are put into a solution of hydrofluoric acid and deionised water in ratio components: HF: H2O = 1:10 at room temperature for 10 minutes, after which the tubes are washed in deionised water for 15-20 minutes. Quality of processing is determined using indicator paper.

EFFECT: invention allows for removing different impurities and preventing formation of defects on a silicon-carbide tube.

FIELD: physics; electronics.

SUBSTANCE: invention relates to microelectronics and can be used in making semiconductor devices and integrated circuits. The method of seating a silicon chip onto the base of a housing for a semiconductor device involves successive deposition of metal layers onto the seating surface of the chip and soldering the chip to the base of the housing. Two metals - titanium and germanium are deposited on the seating surface of the chip. The process is carried out in a single fabrication cycle, and the chip is soldered to the base of the housing at temperature ranging from 300 to 320°C.

EFFECT: more reliable contact between the chip and the base of the housing and stability of the soldering process.

2 ex

FIELD: physics; conductors.

SUBSTANCE: invention relates to making semiconductor devices and can be used in assembling semiconductor chips in a housing for semiconductor devices through lead-free soldering. The method of lead-free contact-reaction soldering a semiconductor chip to a housing with formation of an Al-Zn eutectic involves depositing aluminium or tin on the soldered surfaces of the chip and housing respectively and placing a zinc foil between the chip and the housing and soldering to the base of the housing. Aluminium metal coating is deposited on the base of the housing. A solder foil containing 20Zn/80Sn (wt %) is placed between the chip and the housing, and soldering is carried out in a shielding medium at temperature between 420 and 430°C.

EFFECT: reduced labour input during manufacturing and increased maximum permissible temperature of semiconductor devices during their operation.

FIELD: physics; conductors.

SUBSTANCE: invention relates to semiconductor micro- and nanoelectronics and can be used in making integrated circuits, in making electrodes in transistors and capacitor plates, in making contacts and conduction regions on a silicon surface, as conducting, thermostable and barrier layers in metallisation systems. The method of making a thin-film metal structure of tungsten on silicon involves making a nanometer sublayer of an adhesion promoter on a silicon substrate and subsequent deposition of a thin film of tungsten through gas-phase chemical deposition through reduction of tungsten hexafluoride with hydrogen at low pressure. The adhesion promoter used is tungsten silicide W5Si3.

EFFECT: invention improves quality of the obtained metal structure of tungsten on silicon with simplification of the process at the same time.

3 cl, 1 dwg, 3 ex

FIELD: physics.

SUBSTANCE: invention relates to the technology of semiconductor devices and microchips. Method of forming complete dielectric insulation of elements in a semiconductor involves formation of a dielectric layer around the surface of elements through its deformation shift relative the solid semiconductor after irradiation with ions of gaseous atoms and post-radiation burning in a chemically active medium.

EFFECT: invention increases packing density of elements due to reduction of the thickness of the insulating layer, simplifies the method by doing away with several operations and sophisticated equipment, and also improves electrical characteristics of the microchips due to complete dielectric insulation of the bulk of the elements.

6 cl, 4 dwg

FIELD: physics.

SUBSTANCE: invention can be used in depositing and analysing thin-film structures, especially during production and controlling semiconductor microchips through dry etching. The device for controlling process of dry etching the structure-forming layer of a microchip in a vacuum chamber has a light source and a light beam formation system, which is based on a reflected light microscope, fitted with a monochromatic high-resolution digital video camera which is connected to a computer. The optical microscope is mounted outside the vacuum chamber with possibility of normal illumination of the section of the surface of the etched layer and reception of reflected light beam by its objective lens through an optical window which is built into the vacuum chamber. The device also has a microcontroller and a light-emitting diode driver. The light source is a pulsed lighter, which is based on a multicolour light-emitting diode, connected to the control output of the microcontroller through the light-emitting diode driver, and the control input of the microcontroller is connected to the output of frame synchronous pulses of the video camera.

EFFECT: increased accuracy and reliability of the device.

4 cl, 4 dwg

FIELD: physics.

SUBSTANCE: method of making a semiconductor device involves successive formation of active regions of the semiconductor device, silicon dioxide and deposition of an aluminium film. The formed semiconductor structure is exposed to photons with energy ranging from 20 to 35 eV with intensity of the photon beam ranging from 1011 to 1012 cm2 s-1, with subsequent thermostabilising burning at temperature ranging from 300 to 400°C for 30 to 50 s.

EFFECT: increased adhesion in semiconductor structures, technological effectiveness, improved parametres, increased reliability and increased percentage yield.

FIELD: technological processes, typography.

SUBSTANCE: method for making components for jet printing head consists of the following stages: making case, with upper surface, making several apertures in the indicated upper surface, passing into the case, and an actuating structure inside each of the apertures. Each actuating structure remains fixed to the body frame during operation. The actuating component for the jet printer with formation of drops under request, has a case with an upper surface, an aperture in the upper surface, passing into the case along the axis of the aperture, a convex actuating structure inside the aperture, and electrodes, which are positioned such that, they can apply a field to the actuating structure in such a way that, the actuating structure is deformed. Electrical voltages applied to the walls do not give rise to deviation of the walls and emission of drops through the nozzle.

EFFECT: fast propulsion, without loss of accuracy and piezoelectric material settles uniformly, actuating mechanisms have same channel separation along matrix.

36 cl, 69 dwg

FIELD: production methods; jet printing.

SUBSTANCE: method of high speed creating of multicolor printings during steam processing is foreseen: providing as minimum two steam printings heads, working on high operational frequency, and the printing heads, working on high operational frequency, allow to process the ink with phase changing; providing as minimum two kinds of oil going trough them, and the passing of the base under the printing heads with the speed of 1000 foots per minute; where on the base is formed as minimum one illustration during the process of steam processing. The method of providing high speed, resistant to coloring and other surfaces under the touching of print during the process of material steam processing with using of inks with phase changing is overseen: the providing as minimum one set of printing heads, allowing to use ink with phase changing, with frequency 20kHz, the material providing; the providing of the system for transporting of the material, which allows to transportate the material under the printing heads; providing of great amount of inks with phase changing; transportation of material over the printing head sets with the speed 1000 foots/minute, ejection of ink as minimum from two printing heads to the material, for illustration forming. The method of providing high speed, resistant to coloring and other surfaces under the touching of print during the process of material steam processing with using of inks with phase changing is overseen: the providing as minimum one set of printing heads, allowing to use ink with phase changing, with frequency 20kHz, providing of porous material; providing of transportational system of material, which allows to transportate the material under the printing heads; providing of great amount of inks with phase changing; transportation of material over the printing head sets with the speed 1000 foots/minute, ejection of ink as minimum from two printing heads to the material, for illustration forming; on the stage of ejecting of inks its formed the illustration, which has up to 200 points/printing head/ liner inch.

EFFECT: under the decreasing of the costs it is decreasing the amount of trash and increased the efficiency.

33 cl, 1 dwg

FIELD: power engineering.

SUBSTANCE: device comprises housing structure that defines the central plane, a number of passages for discharging droplets that pass through the housing structure parallel to the central plane, nozzle for discharging droplets, means for generating sound wave within the passage, and collector that is extended throughout the housing structure parallel to the central plane and perpendicular to the passages. The passages passing through the central plane are shifted perpendicular to the central plane with respect to the adjacent passages. Each nozzle is in communication with the appropriate passage. The collector crosses the passage so that the reflection coefficient of the sound wave of the boundary between each passage and collector is the same for all passages. According to the second version, the device has first group of passages shifted with respect to the central plane in the first direction perpendicular to the central plane, second group of passages shifted with respect to the central plane in the second direction perpendicular to the central plane, and drives. According to the third version, the device has additional means for generation of sound wave and discharging droplet through the nozzle. The collector intersects each passage of the first group whose reflection coefficient differs from that of the second group of passages, first circuit for generating first exciting signal that excite the passages of the first group, and second exciting circuit for generating the second exciting signal that excites the passages of the second group. The first and second group of passages are excited alternatively.

EFFECT: improved design.

21 cl, 21 dwg

FIELD: typewriters, printing devices; drop precipitation components, drop precipitation plates with nozzles.

SUBSTANCE: the method for forming a component of plate contains operations: forming of the body using first material, where aforementioned body has periphery, forming of the cover using second material, around the aforementioned body, in such a way that the cover extends at least across a part of the periphery of aforementioned body, and forming of the nozzle, which passes through aforementioned body. The method for forming a plate, when the plate with nozzles is limited to the plane of plate with nozzles and contains a plate, which has at least one layer of plate with nozzles and a set of nozzles, where each nozzles passes through plastic placed within an aperture in the plate with nozzles, contains operations for forming a set of individual bodies of polymeric material, distributed across the plane of plate with nozzles, and forming of at least one metallic layer of plate with nozzles by galvanoplastic application around aforementioned bodies of polymeric material. The method for forming a component of the plate contains following operations: creation of a layer of first photo-resistive material on a substrate, selective development and removal of photo-resistive material on the substrate to form a mesh of separate bodies of first material on the substrate, creation of first metallic cover around aforementioned bodies to form metallic plate with nozzles, having apertures, each one of which contains a body of aforementioned first material, and creation of a nozzle, which passes through each body.

EFFECT: an improved method is suggested for manufacturing the component meant for usage in a device for drop precipitation.

3 cl, 12 dwg

FIELD: printing devices.

SUBSTANCE: cartridge comprises compact structure of electrical connections, which includes a number pairs of matrix-columns of electrical contact areas arranged over the back side of the cartridge and connected with the droplet generators.

EFFECT: enhanced reliability.

13 cl, 18 dwg

FIELD: jet printing.

SUBSTANCE: device 100 has three column matrices 61 of drop emitters, configured for multi-pass color printing with printing resolution, having a step of carrier axis points, which is less, than step of columnar nozzles of ink drop emitters. Jet printing head has resistors of high resistance heater and effective control circuits, which are configured to compensate alteration of parasite resistance, caused by power routes (86a, 86b, 86c, 86d).

EFFECT: compactness of jet printing head with large number of ink drop emitters.

20 cl, 11 dwg

The invention relates to the technique of inkjet printing and can be used in inkjet printers and other printing devices

Microinjector // 2146621

FIELD: jet printing.

SUBSTANCE: device 100 has three column matrices 61 of drop emitters, configured for multi-pass color printing with printing resolution, having a step of carrier axis points, which is less, than step of columnar nozzles of ink drop emitters. Jet printing head has resistors of high resistance heater and effective control circuits, which are configured to compensate alteration of parasite resistance, caused by power routes (86a, 86b, 86c, 86d).

EFFECT: compactness of jet printing head with large number of ink drop emitters.

20 cl, 11 dwg

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