Parallel-conveyor device for vectorisation of aerospace images of earth surface

FIELD: information technologies.

SUBSTANCE: invention may be used to build vector description of urban development elements on the basis of aerospace images of Earth surface in creation of electronic maps for geoinformation systems. Device comprises processor module, comprising control processor and unit of vectorisation, information interface, main memory controller, main memory, the first graphical module, comprising the first graphical processor and the first buffer memory, the second graphical module, comprising the second graphical processor and the second buffer memory, the third graphical module, comprising the third graphical processor and the third buffer memory, controller of image input-output, external memory.

EFFECT: reduction of time expenses.

3 dwg

 

The invention relates to computing and can be used to construct a vector description of the elements of urban development in aerospace images of the earth's surface at the creation of electronic maps for geographic information systems.

A device to highlight the contours of the image (SU 1253337 A1)containing sequentially arranged matrix of photosensitive elements, a matrix of threshold discriminators, the signal processing unit and the display unit information.

The disadvantage of this device is the low accuracy of selection circuits, due to independent processing when selecting paths, each pixel separately without regard to the location of the neighboring pixels of the analyzed circuit, and the absence of the possibility of forming a vector describing the contours of the elements (objects) in the image.

The closest device is a multiprocessor vector computer (RU 2113010 C1)containing vector main internal memory associated with the use of multiply-wide information interface with the Central control processor subsystem input / output and at least one Central processing part which includes a vector arithmetic unit containing 2m (m=0,1...) multiple pipelined arithmetic% is sorow, each of which contains a control unit, registered memory and pipelined arithmetic unit.

The disadvantage of this device is the low speed image processing in the case of using the device for vectorization of the image, which is caused by the inefficient use of computing resources is identical in structure to the arithmetic processors when performing this task.

The technical task of this device is the reduction of time spent on the construction of a vector description of the elements of urban development in aerospace images of the earth's surface.

The task is solved in that in multiprocessor vector computer that contains a control processor and an information interface, inputs of the block vectorization, controller, RAM, RAM, the first graphics module consisting of the first graphics processor and the first buffer memory, the second graphics module consists of the second graphics processor and the second buffer memory, the third graphical element consisting of a third graphics processor and the third buffer memory controller I / o image, external memory, and the first input-output CI of the control processor connected to the input-output control CI block vectorization, the output address and input-output data D which is connected to the first the m input address AR and the first input-output data DP controller RAM, respectively; output addresses AM and the second input-output data DM controller RAM is connected to the input address and the input-output data D of RAM, respectively; a second input addresses And controller RAM via the data interface is connected to the first output address And the first graphics processor to the first output address And the second graphics processor to the first output address, And the third graphics processor and to the first output address And controller I / o image; a third input-output data D of the RAM controller via the data interface connected to the first input-output data D of the first graphics processor to the first input the output data D of the second graphics processor to the first input-output data D of the third graphics processor and to the first input-output data D of the controller I / o image; the second output of the address AM and the second input-output data DM of the first graphics processor is connected to the input address and the input-output data D of the first buffer memory, respectively; the second output of the address AM and the second input-output data DM of the second graphics processor is connected to the input address and the input-output data D of the second buffer memory, respectively; the second output of the address AM and the second input-the output data DM of the third graphics processor connected to the input address and the input-output data D of the third of the second buffer memory, respectively; the second output of the address AE and the second input-output data DE controller I / o image is connected to the input address and input-output data D of the external memory, respectively; a second input-output With a controlling processor with a data interface connected to the input / output control From the first graphics processor to the input-output control With the second graphics processor, input-output control From the third graphics processor and input-output control From the controller I / o image.

The invention is illustrated by drawings, where figure 1 presents a structural diagram of a device for vectorization aerospace images of the earth surface, figure 2 - algorithm of functioning of the device in serial mode, figure 3 - algorithm of operation of the device in a pipelined mode.

Device for vectorization aerospace images of the earth surface contains the processor module 1, which consists of a controlling processor 1.1 and block vectorization 1.2, the controller RAM 2 RAM 3, the first graphics module 4, consisting of the first graphics processor 4.1 and the first buffer memory 4.2, the second graphics module 5 consists of the second graphics processor 5.1 and the second buffer memory 5.2, the third graphical module 6 comprising a third graphical process is Sora 6.1 and the third buffer memory 6.2, controller I / o image 7, the external memory 8, data interface 9, and the first input-output CI of the control processor 1.1 is connected to the input-output control CI block vectorization 1.2, the output of the address a and the input-output data D which is connected to the first input of the address AR and the first input-output data DP controller RAM 2, respectively; output addresses AM and the second input-output data DM of the RAM controller 2 is connected to the input address and the input-output data D RAM 3, respectively; the second input addresses And controller RAM 2 through the information interface 9 connected to the first output address And the first graphics processor 4.1, to the first output address And the second graphics processor 5.1, to the first output address, And the third GPU 6.1 and to the first output address And controller I / o image 7; the third input-output data D of the RAM controller 2 via the data interface 9 connected to the first input-output data D of the first graphics processor 4.1, to the first input-output data D of the second graphics processor 5.1, to the first input-output data D of the third GPU 6.1 and to the first input-output data D controller I / o image 7; the second output of the address AM and the second input-output data DM of the first graphics processor 4.1 is connected to the input address and the input-output data is x D first buffer memory 4.2, respectively; the second output of the address AM and the second input-output data DM of the second graphics processor 5.1 is connected to the input address and the input-output data D of the second buffer memory 5.2, respectively; the second output of the address AM and the second input-output data DM of the third GPU 6.1 is connected to the input address and the input-output data D of the third buffer memory 6.2, respectively; the second output of the address AE and the second input-output data DE controller I / o image 7 is connected to the input address and input-output data D of the external memory 8, respectively; a second input the output control processor 1.1 using information interface 9 is connected to the input / output control From the first graphics processor 4.1, with the entrance-exit control With the second graphics processor 5.1, with the entrance-exit control From the third graphics processor 6.1 and the entrance-exit control From the controller I / o image 7.

The device operates as follows.

When the device starts processing the first image is performed in sequential mode. For this control processor 1.1 exhibits on the second input-output With the command code of the input image received information interface 9 to the input-output control From the controller I / o image 7. Upon receipt of the command code, the image input controller the I / o image 7 performs a line-by-line reading of the image from the external memory 8 (block 1 of the algorithm in figure 2), exposing the address line of the image on the second output address AE, which is fed to the input address And the external memory 8. When receiving the address of the external memory 8 element provides a corresponding line image through the input-output data D to the second input-output data DE controller I / o image 7. Controller I / o 7-element transmits the received image line through the controller RAM 2 RAM 3, for which the first output address, And generates the address line of the image received via the data interface 9 to the second input addresses And controller RAM 2, and the input-output data D of the element delivers the line of the image information through the interface 9 is supplied to the third input-output data D of the controller RAM 2. The RAM controller 2 transmits the received address to the input address And the RAM 3 and the elements of the line image on the input-output data D RAM 3, recording the resulting line image at the specified address. Upon completion of the read operation of the image controller I / o image 7 through the input-output control issues With the verification code to obtain data on the second input-output control processor 1.1, in which the control processor 1.1 exhibits on the second input-output With the command code to copy the image first graphics processor coming through information integration the face 9 to the input-output control With the first graphics processor 4.1.

The first graphics processor 4.1 using the controller RAM 2 mode direct memory access (RAP) provides line-by-line reading of the image from the RAM 3 and the recording in the first buffer memory 4.2 (block 2 of the algorithm in figure 2), for which the first graphics processor 4.1 the first output address, And generates the address line of the image received via the data interface 9 and the RAM controller 2 to the input address And the RAM 3. After retrieving the address of the RAM 3 element generates the specified string image on the input-output data D, where the string is fed to the second input-output data DM controller RAM 2, the feed data through the third input-output data D to the first input-output data D of the first graphics processor 4.1. The first graphics processor 4.1 element sends a string to the image input-output data D of the first buffer memory 4.2, forming the input address And the first buffer memory 4.2 address of the copied row, then the first buffer memory 4.2 writes the line image at the specified address. Upon completion of the copy image of the first graphics processor 4.1 delivers the information through the interface 9 to the second input-output control processor 1.1 confirmation code copy the data. Similarly, you copy the image from the RAM 3 to the second buffer memory 5.2 (block 3 algori the mA in figure 2) and the third buffer memory 6.2 (block 4 of the algorithm in figure 2). Upon completion of the copy image all the graphic processor control processor 1.1 gives the second input-input With command code processing that information through the interface 9 to the input-output control With the first graphics processor 4.1, input-output control With the second graphics processor 5.1, input-output control From the third graphics processor 6.1. When receiving the command code to handle each of the graphics processors is processing the image stored in the buffer memory corresponding to the graphics module.

The first graphics processor 4.1 produces differentiation aerospace image (block 5 of the algorithm in figure 2) by convolution with a mask representing a discrete approximation of partial derivatives of the Gaussian function [Elder J.H. Local Scale Control for Edge Detection and Blur Estimation [Text] / James. H. Elder, Steven W. Zuckler // IEEE Transactions on Pattern Analysis and Machine Intelligence. - Vol.20, No7. - 1998. - pp.699-716]. The second graphics processor 5.1 creates a clustered representation aerospace image (block 6 of the algorithm in figure 2) in the space containing the luminance and geometric properties [R. Gonzalez Digital image processing [Text] / Gonsales, Rvudz // M: Technosphere, 2006, S. 1072]. The third graphics processor 6.1 makes calculation of the coefficients of the discrete transform is urge aerospace image (block 7 of the algorithm in figure 2) [Soifer V.A. Methods of computer image processing / edited Wasover - 2nd ed., Corr. - M.: FIZMATLIT, 2003. - 784 C.]. At the end of processing each graphics processor via the data interface 9 delivers to the second input-output control processor 1.1 code processing is completed.

Getting codes complete processing of all graphics processor, control processor 1.1 on the second input-output command code sets up the processing results of the first graphics processor, which through the information interface 9 is fed to the input-output control With the first graphics processor 4.1. Upon receipt of this code, the first graphics processor 4.1 using the controller RAM 2 in PEP mode provides line-by-line recording obtained by differentiation of the contour image in the RAM 3 from the buffer memory 4.2 (block 8 of the algorithm in figure 2). To do this, the first graphics processor 4.1 exhibits on the second output address AM address line contour image, which is fed to the input address And the first buffer memory 4.2. Upon receipt of the address of the line buffer memory 4.2 element generates on input-output data D corresponding line image supplied to the second input-output DM of the first graphics processor 4.1, which element sends a string to image info through the communication interface 9 to the third input-output data D of the controller RAM 2 and sets the corresponding address on the second input addresses And controller RAM 2. The RAM controller 2 transmits the received address to the input address and the elements of the line image on the input-output data D of the RAM 3, which writes the resulting contour line of the image at the specified address. After copying is complete, the contour image in the RAM 3, the first graphics processor 4.1 via the data interface 9 delivers to the second input-output control processor 1.1 confirmation code copy of the results. Similarly, recording the cluster image from the second buffer memory 5.2 in the RAM 3 (block 9 of the algorithm in figure 2) and the frequency representation of the image from the third buffer memory 6.2 in the RAM 3 (block 10 of algorithm 2).

After receiving verification codes copy the results from all GPUs control processor 1.1 through the first input-output CI submits to the input-output control CI block vectorization 1.2 command code processing results, which block vectorization produces 1.2 create a vector view object based on the contour, cluster and frequency descriptions of aerospace images stored in the RAM 3 (block 11 of the algorithm in figure 2). Vector representation of objects [Miroshnichenko HE Recognizes hardware-software diagnostic complex [Text] / Soumyanath, Vnesti, Svetiev // Izv. Higher education institutions. Priborostroe is selected. - T, No. 2. - 2005. - S-27] is built as a set of closed vector sequences, each of which represents the contour of the object, the boundary of the cluster or region of the image with close values of the coefficients of the Fourier transform. The resulting vector representation of the objects on aerospace image using the controller's RAM 2 is written in the RAM 3. After the build completes vector description block vectorization 1.2 applies to the first input-output CI of the control processor 1.1 exit code vectorization, upon receipt of which the control processor 1.1 exhibits on the second input-output command code results received via the data interface to the input-output control From the controller I / o image 7. Controller I / o image 7 by means of the RAM controller 2 reads the vector representation of the image from the RAM 3 in RAP mode and stores it in the external memory 8 (block 12 of the algorithm in figure 2) in the same way as it reads the image from the external memory 8.

Processing the second and subsequent imaging device performs pipelining, which allows to increase the loading of the computing units. After copying the image from the RAM 3 to the buffer memory of each of the three graphic modules (blocks 1, 2, 3 of the algorithm in figure 3) in addition to the WPPT is erozirovanne the current image is the first graphics processor 4.1 (block 4 of the algorithm in figure 3), clustering the current image and the second graphics processor 5.1 (block 5 of the algorithm in figure 3), the Fourier transform of the current image to the third graphics processor 6.1 (block 6 of the algorithm in figure 3) are also made reading the next image from the external memory 8 in the RAM 3 (unit 8 of the algorithm in figure 3) and creating a block vectorization 1.2 vector representation of the previous image (block 7 of the algorithm in figure 3), the results of differentiation, clustering, and Fourier transform which is stored in the RAM 3. After all these transactions contour, cluster and frequency representation of the current image sequentially copied from the buffer memory of each graphics module in the RAM 3 via the controller RAM 2 (units 9, 10, 11 of the algorithm in figure 3), then the vector representation of the previous image is recorded on the RAM 3 in the external memory 8 (block 12 of the algorithm in figure 3).

The processor module 1 can be implemented on a dual-core Intel Core 2 Duo or AMD Athlon x2, and the first processor core performs the function of the control processor 1.1, the second core function block vectorization 1.2. To implement the processor module can also be used trehyadernye AMD Phenom X3 and Quad-core processors Intel Core 2 Quad or AMD Phenom, where the first kernel performs the function of the control processor 1.1, and d is ot two or three kernel function block vectorization 1.2.

Graphic modules 4, 5, 6 are implemented on three graphic accelerator nVidia GeForce 8800/9600/9800, combined with nVidia SLI, or three graphics accelerators from AMD ATI HD 3850/3870, combined with technology, ATI CrossFire.

Thus, the proposed solution allows to reduce the time required to build a vector description of the elements of urban development in aerospace images of the earth surface by introducing into the device of the first graphics processor 4.1, the second graphics processor 5.1, the third graphics processor 6.1 and block vectorization 1.2, which pipelining parallel to perform the differentiation, clustering, the Fourier transform of the current image and a vector encoding object in the previous image.

Device for vectorization aerospace images of the earth's surface, contains a control processor and an information interface, characterized in that the device entered the block vectorization, controller, RAM, RAM, the first graphics module consisting of the first graphics processor and the first buffer memory, the second graphics module consists of the second graphics processor and the second buffer memory, the third graphical element consisting of a third graphics processor and the third buffer memory, to ntroller I / o image, external memory, and the first input-output control processor connected to the input-output control block vectorization, the output address and the input-output data of which is connected to the first input addresses and the first input-output controller data RAM, respectively; output addresses and the second input-output controller data RAM is connected to the input address and the input-output data of the RAM, respectively; a second input addresses of the RAM controller via the data interface is connected to the first output address of the first graphics processor to the first output of the second graphics processor to the first output address of the third graphics processor and to the first output address controller I / o image; a third input-output controller data RAM via the data interface connected to the first input-output data from the first graphics processor to the first input-output data of the second graphics processor to the first input-output data of the third graphics processor and to the first input-output data of the controller I / o image; the second output addresses and the second input-output data of the first graphics processor is connected to the input address and the input-output data of the first buffer memory, respectively; the second output addresses and the second input-output data of the second graphics processor soedineniya entrance address and input-output data of the second buffer memory, respectively; the second output addresses and the second input-output data of the third graphics processor connected to the input address and the input-output data of the third buffer memory, respectively; the second output addresses and the second input-output data of the controller I / o image is connected to the input address and input-output data of the external memory, respectively; a second input-output control processor with a data interface connected to the input-output control of the first graphics processor, input-output control of the second graphics processor, input-output control of the third graphics processor and input / output controller I / o image.



 

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24 cl, 16 dwg

FIELD: physics, computer engineering.

SUBSTANCE: invention is related to systems and methods, which automatically create subscription for applications and services presented to wireless device from another computer device in wireless network, where subscription requires periodical payment for uninterrupted access to application or service. System controls interaction of end user of wireless device with other computer devices, such as servers of applications downloads, via wireless network. When end user receives application or service from computer device, system automatically registers subscription and may either invoice the subscriber of wireless device for subscription, or transfer to supplier or other object, to invoice the subscriber.

EFFECT: expansion of functional resources due to presentation of additional services and automatic generation of subscription invoices.

41 cl, 9 dwg

FIELD: process engineering.

SUBSTANCE: proposed system comprises sensor (17) to detect one or more process parametres at least one process station (20), data acquisition and processing device (32) operated by signals (R) from sensors (17) and intended for obtaining data (Q) on process quality and device (19) to control process flow on the basis of data (Q). Aforesaid device (32) is arranged at least one process station (20). Control device (19) is arranged remote from device (32) and comprise units (42, 43) of wireless transceiver to exchange data (Q) between devices (32) and (19).

EFFECT: higher efficiency.

15 cl, 3 dwg

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to connection of input-output devices or central processor devices or transfer of information or other signals between these devices. Provision for autoshaping manipulators in supercomputers in accordance with a given program with creation of an optimum architecture for the solved task is achieved due to that, the cooled substrate is a body with an inbuilt cooler, on which are attached (glued) microcircuit chips, containing multiple contact fibre optic connectors. On the end surface of the substrate there is a device for automatic attachment and connection of the substrate to a support. The autoshaping supercomputer contains a computer-builder, manipulators, controlled by this computer, as well as library for substrates with microcircuit chips and a fibre optic bus library. The supercomputer is automatically formed by manipulators by mounting the substrates onto a support and executing inter-substrate fibre optic connections through instructions from the computer builder. Manipulators are in the top part of the supports and guides above the supports.

EFFECT: multiple increase in inter-substrate and inter-support connections, compared to use of other means of connecting microcircuit chips, which provides for filling the entire inter-support space of the supercomputer with fibre optic bus.

6 cl, 9 dwg

FIELD: communications.

SUBSTANCE: method includes inputting data from individual subscriber into memory of subscriber device, then data are sent through subscriber device to data server, where it is clarified, whether subscriber provides certain information or consumes certain information with query for certain data, data from data provider are kept in information server database in form of individual provider record, and for data consumer data search is performed, appropriate to query, in database, in case if data answering the query is found on server, it is sent to data consumer. Method includes prior forming of classification, allowing forming identifiers of objects of possible interest of subscribers, before inputting data from individual subscriber or in process of this input at least partial conversion of these data to appropriate formed identifier of said classification, used for recognizing information in database, is performed, said information being appropriate for subscriber request. Portion of data not used in identifier is used dependent on category of subscriber.

EFFECT: broader functional capabilities.

2 cl, 2 dwg

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