Microcomputer and method of its testing

FIELD: information technologies.

SUBSTANCE: microcomputer (ASIC) comprises multiple integral circuits (IC), which are connected to each other with interfaces that are synchronous to data sources. At first test data is input into trigger for data transfer (F1) and trigger for transfer of clock pulse (F2) into IC on the side of data transfer. Then circuit (11) of phase locking generates clock signal, in response to which the first and second triggers send test data and clock pulse. Triggers (F3, F4) for reception of IC data on the side of data reception, test data is registered, which come from the first trigger (F1) in compliance with clock pulse, which comes from trigger (F2).

EFFECT: provision of testing at working frequency at the level of circuit boards without application of system level test, and assessment of data sent along each transfer channel.

12 cl, 21 dwg

 

The technical field to which the invention relates.

The present invention relates to the testing of large-scale integrated circuits (LSIS), more specifically, to a circuit configuration and method for testing interconnects BIS-level cards in real operating conditions.

The level of technology

In the manufacture of the card, which is equipped with specialized integrated chip (ASIC, English - Application Specific Integrated Circuit)designed and manufactured to perform a specific task, a widely used peripheral scanning system using the JTAG (joint working group on test automation-English - Joint Test Automation Group)to check whether the card is defective. In the case where the interconnect on the card level testing using JTAG testing is carried out only using the scheme without using JTAG circuit (hereinafter - the user's schema), which provides the intended work of the ASIC. This allows testing in General, regardless of the configuration schema user. There is a testing method known as EXTEST, which is part of the standard IEEE1149 (see, for example, non-patent document [1]: IEEE STD1149.1-1990, "IEEE Standard Test Access Port and Boundary-Scan Architecture", IEEE publication, Inc., 345 East 47th Street, NY 10017, USA).

Currently as input and turn the Yes to high speed ASIC mainly use interface with fast memory or interface synchronous with the source type. Synchronous with the source interface (scheme I / o) is applicable for high-speed operation and is used in a synchronous dynamic random access memory devices (SDRAM-English - Synchronous Dynamic Random Access Memories), such as SDRAM with dual speed (DDR-English - Double Data Rate) SDRAM and with the fourth speed (QDR, English - Quad Data Rate), and various high-speed tire CPU. Together with the data chips this interface passes from the chip on the transmission side of the chip on the receiving side clock pulse for latching data of the chip.

When testing such circuits operating at high speed, it is considered important to test in real conditions (check at the operating frequency), static test, such as EXTEST, to check the correct working of the logical schema.

Testing at the operating frequency synchronous with the source-level interface cards traditionally performed by the test system level using a test program developed by the developer of printed circuit boards, the system designer and developer of firmware for ASIC.

Disclosure of inventions

Tasks inventions

As mentioned above, it is preferable to test at the operating frequency was carried out in synchronous with the source interface, the CE ASIC, running with high speed. However, traditionally there is no General method for testing the operating frequency of the interface on the card level.

In addition, although the practical test at the operating frequency of exercise at the level of the boards by the test system level, as mentioned above, in this case, there arises the following problem. If the result of the test system-level faults are detected, it is necessary to debug. However, if the problem is synchronous with the source interface, the debug is not easy to implement. This is because due to a faulty interface distorted data only, and the status register in the chip is normal. In other words, the problem is only spoken observational data, and the control signal is operating properly. Because of this, it is extremely difficult to identify the cause of the problem.

Considering the above problems, the present invention is the creation of a common algorithm (configuration and operating method) test on the card level of the synchronous source interface ASIC inside at the operating frequency without the use of the test system level.

Problem solving

For solving the aforesaid problems, the invention can be implemented as a microcomputer that has the following proc is the tenant. The microcomputer has many integrated circuits (IC), connected with each other in sync with the source interface. The IP-side data through the synchronous source interface includes: circuit phase-locked loop (PLL) for transmission to the Executive synchronizing pulse during the actual operation, the first trigger for the transmission of test data in accordance with the Executive pulse passed by the PLL, and the second trigger to transmit synchronous with the source clock in accordance with the Executive pulse passed by the PLL. The IP-side of receiving data via synchronous with the source interface has a third trigger for collecting test data transmitted by the first trigger in accordance with a sync pulse that is transmitted by the second trigger.

More precisely, the IP on the transmission side includes in addition to the generation scheme of the dual pulses to extract a double-pulse signals of the Executive pulses transmitted by the PLL. In addition, the first trigger transmits test data in accordance with a double-pulse signals extracted from the schema generate double pulses. Similarly, the second trigger passes the clock pulse in accordance with a double-pulse signals extracted from the schema GE is aerovane dual impulses.

More precisely, the first trigger IP on the transmission side transmits the test data with a delay equal to half of a double-pulse signals relative to the clock transferred by the second trigger. Alternatively, the first trigger transmits test data to the front of the same clock as the clock pulse transmitted by the second trigger. In the latter case, the IP on the receiving side has a means of delay, such as the schema DDL (digital delay line, from the English - digital delay line) for transmitting the received sync pulse to the third trigger with a delay of π/2.

The first trigger IP on the transmission side may consist of a trigger with separate inputs (RS-flip-flop). In this case, the IP on the transmitting side further includes a TEST DATA REGISTER (TDR, English - TEST DATA REGISTER) JTAG (hereinafter JTAG_TDR, see non-patent document [1]) and stores the test data first trigger by setting or resetting the first flip-flop in accordance with the value held by this JTAG_TDR. Another possible configuration in which the test data is introduced into the first trigger by scanning paths of the data shifted through the scan path formed by the first trigger IP on the transmission side.

In addition, in the present invention is also a method for testing the microcomputer. Nestruev the microcomputer installed a lot of IP, interconnected synchronous with the source interface. The method includes a stage on which the IP-side data through the synchronous source interface type of the original value of the first trigger data and the second trigger to send a sync pulse, and the stage at which transmit the synchronization signal of the PLL for transmission to the Executive synchronizing pulse during the actual operation, after which the first trigger and the second trigger respectively transmit data to their original values and the sync pulse. The method also includes a step in which the third trigger for the reception of IP data receive-side data through the synchronous source interface collects the original values that are passed to the first trigger, in accordance with a sync pulse that is transmitted by the second trigger.

In this case, the phase of the input values in the first and second triggers includes a step in which each of JTAG_TDR that are coordinated respectively with the first and second triggers, keep a preset value, and the stage at which JTAG_TDR in accordance with the stored their values are set or reset the first trigger and the second trigger for input values in the first and second triggers. Alternatively, at the stage of input values in the first and second triggers the outcome of the s values enter by scanning paths test data shifted through the scan path relative to the first and second triggers, forming a scan path.

In addition, the present invention also proposes a method of testing a microcomputer, which includes a variety of IP-connected synchronous with the source interface. This method of testing involves the step at which the trigger on the side of the transmission data through the synchronous source interface receives and stores the test data, the stage at which transmit the synchronization signal of the PLL for transmission to the Executive synchronizing pulse during the actual work, and then transmit the test data stored in the trigger on the transmission side, and synchronous with the clock pulse source and the stage at which the trigger on the side of receiving data via synchronous with the source interface collects test data in accordance with a sync pulse.

In this case, the stage of acceptance test data trigger on the transmission side includes a stage on which retain the value specified in JTAG_TDR corresponding to the trigger on the transmission side, and the stage at which in accordance with the value stored in JTAG_TDR, carry out the setting or resetting of the trigger on the transmission side, which corresponds to JTAG_TDR to trigger on the transmission side has retained test data. Alternatively, at the stage of acceptance test data trigger on peredumaete the trigger on the transmission side stores the test data through the scan path test data shifted through the scan path relative to the trigger on the transmission side, forming a scan path.

Technical results of the invention

According to the present invention with the above configuration, the communication between the circuits connected synchronous with the source interface inside the ASIC may be implemented in accordance with the same timing as in the real process. Then you get the result data exchange and evaluate using JTAG_TDR to study in the chip on the receiving side. This allows testing at the operating frequency at the level of circuit boards without the use of the test system level.

In addition, this method of testing allows us to separately evaluate the data that is passed on each transmission channel. Accordingly, unlike the test system when a problem is detected you can easily determine the cause.

Brief description of drawings

Hereinafter described in detail preferred embodiments of the present invention with reference to the attached drawings on which is shown:

figure 1 - the complete configuration is synchronized with the source schema to which is applicable the first variant of implementation of the present invention,

figure 2 - the basic elements shown in figure 1 scheme for synchronization with a source subject to option exercise,

figure 3 - chart, illustriou the General form of the signal in the trigger F3, shown in figure 2,

figure 4 is a chart illustrating the waveform in the trigger F4, shown in figure 2,

figure 5 is a diagram illustrating the circuit configuration initialization triggers circuit according to a variant implementation,

figure 6 is a chart illustrating waveforms during testing according to a variant implementation,

7 is a block diagram illustrating a test sequence according to a variant implementation,

on Fig diagram illustrating the configuration of a trigger on the transmission side, used in the embodiment,

figure 9 is a diagram illustrating the configuration of a trigger on the receiving side, used in the embodiment,

figure 10 diagram illustrating the circuit configuration JTAG_TDR used in the embodiment,

figure 11 is a chart illustrating signals UpdateDR_L and RunTestIdle used in the embodiment,

on Fig diagram illustrating the entire configuration is synchronized with the source schema to which is applied a second variant implementation of the present invention,

on Fig diagram illustrating the basic elements shown in Fig scheme for synchronization with a source subject to option exercise,

on Fig - chart illustrating waveforms at three in the Hera F13, shown in Fig,

on Fig diagram illustrating a waveform in the trigger F14 shown in Fig,

on Fig diagram illustrating the entire configuration is synchronized with the source schema to which the applicable third alternative implementation of the present invention,

on Fig diagram illustrating the circuit configuration of triggers on the transmission side, used in the embodiment,

on Fig diagram illustrating the basic elements shown in Fig scheme for synchronization with a source subject to option exercise,

on Fig diagram illustrating a waveform in the trigger F23 shown in Fig,

on Fig diagram illustrating a waveform in the trigger F24 shown in Fig,

on Fig diagram illustrating waveforms during testing under option implementation.

The presented schemes under F1-F4, F11-F14, F21-F24 marked trigger 11 - PLL, 12 controller PLL, 13 - generator dual pulses, 14, 21 controller, TAR, 15, 22 - instruction register, 23 - schema DDL, 24 controller clock

Preferred embodiments of the inventions

First, let us briefly summarise the General principles of the invention. For testing according to the present invention in each pair of two chips (for synchronization with the source of the om), exchanging data they transfer, which carries a chip on the transmission side of the chip on the receiving end of many members of ASIC circuits (schemes). To do this, first put in action the triggers for synchronization with the source as the chip on the transmission side, and the chip on the receiving side for receiving the respective set values. Then, in accordance with a sync pulse trigger synchronous with the source interface with the same speed as during the actual operation, to transfer values (test data) trigger on the transmitter to trigger on the receiving side. Then display the result stored in the trigger on the receiving side, and then study it.

As described above, in the present invention, test data is passed through the synchronous source interface with the same speed as during the actual work, which carry out testing at the operating frequency. In some cases, when in test, you have to use triggers to synchronize with the source, can be applied to the way in which JTAG_TDR is shared.

Methods of synchronization with the source are: (a) method in which a transmitting side transmits data and clock pulse equal to half the interval is between them, and (b) a method in which a transmitting side transmits data and clock pulse at the front of one of the sync pulse. Of these methods, the method (b) in many cases use different from other periods of repetition front of the clock and data, to delay the clock pulse by π/2 (90°) by using the delay, such as the schema DDL (digital delay line) (next - mechanism delay sync pulse at π/2 is called DDL) in the chip on the receiving side, thereby the data zamalchivaut in a trigger in accordance with this clock.

As the method of input values (test data) triggers to synchronize with the source used method of input values in accordance with the setting signal is reset by using flip-flops with separate entrances as triggers to synchronize with the source. In addition, when the synchronization source carry out the aforementioned method (b), may be used a method in which the trigger on the transmission side is also used as a JTAG_TDR (i.e., in which the source is injected into the trigger on the transmission side using the algorithm of the shift data in accordance with JTAG). Therefore, for the implementation of the test according to the present invention can be expected to apply the schema configuration requirements the types. Further, the present invention is described on the example from the first to the third embodiments, which correspond to these configurations schema.

The first option exercise

In the first embodiment, described the following case. In particular, as a way synchronization source is used a method in which a transmitting side transmits data and clock pulse equal to half the interval between them.

Figure 1 shows the complete configuration is synchronized with the source schema to which the applicable option exercise. As shown in figure 1, the chip And is the chip on the transmission side, and the chip is a chip on the receiving side. Although figure 1 shows only synchronous with the source areas of the scheme, it is assumed that both circuits a and b respectively are system diagrams. It should be noted, as shown in figure 1 the differences between the chips a and b only indicate whether each of the chips and the chip on the transmission side or the chip on the receiving side. In other words, each circuit in the ASIC is a chip a or chip b depending on the state (the transferor or the transferee) circuit in synchronous with the source interface.

In the chip And under FF_T is indicated by a trigger on peredumaete. In this embodiment, the trigger on the transmission side is a trigger with separate entrances, the configuration of which is shown in Fig. In the chip IN FF_R indicates the trigger on the receiving side. The trigger on the receiving side is also a trigger with separate entrances, the configuration of which is shown in Fig.9. TDR_FF in circuits a and b denotes JTAG_TDR whose configuration is shown in figure 10.

Figure 2 illustrates the basic circuit elements for synchronization with a source subject to this option implementation. As shown in figure 2, the triggers to synchronize with the source in the chip A (the transferor) is the trigger F1 data and trigger F2 to send a sync pulse, and the chip In (host) - triggers F3 and F4 for receiving data. Of flip-flops F3 and F4 on the receiving side trigger F3 collects data transmitted by the trigger F1 at the forefront of the pulse transmitted by the trigger F2. Trigger F4 collects data transmitted by the trigger F1 on a falling edge of the sync pulse, transmitted by the trigger F2.

As shown in figure 2, a single trigger F2 to send a sync pulse has a single trigger F1, single trigger F3 and single trigger F4. However, in the real circuit single trigger F2 for transmission C is agroimpulse has several triggers, F1, and the number of triggers F3 and the number of triggers F4 in the chip In each case corresponds to the number of triggers F1 (see figure 1). In addition, the circuits a and b there are several sets of such triggers F1-F4. For example, suppose that the chips a and b have four sets of triggers F1-F4, with every single set trigger F2 has eight flip-flops F1, eight flip-flops F3 and eight flip-flops F4. In this case, the communication speed between integrated circuits a and b is 32 bits (=8 bits×4)/front of the clock.

In addition, in the chip And the many triggers F1 and F2 on the transmission side forms a scan path for production tests, each of them is connected with the terminal of the data input (data input into the scan register) and terminal output data (output data from the scan register in the chip A. Similarly, in the chip triggers F3 and F4 on the receiving side to form a scan path, each of them is connected with the terminal of the data input (data input into the scan register) and terminal output data (output data from the scan register in the chip C. Each of flip-flops F1, F2, F3 and F4 are set/reset in response to the output signal of the corresponding TDR_FF, each of which is JTAG_TDR (see figure 1). In addition, F1, F2, F3 and F4 are the triggers MUXSCAN (multip csornai scanning, English - multiplexer scan). During testing in F1 and F2 receives the polling signal SE="1", and F3 and F4 receives the polling signal SE is"0". This also applies to Fig-18, which are illustrated other embodiments of described next.

The following triggers F1 and F2 chips.

The flip-flop F1 on the transmission side data type value (test data) from the corresponding TDR_F. Then in response to the control signal SG_P="1", introduced by the multiplexer M1, trigger F1 inverts its own output signal and again enters the inverted output signal, and then outputs the stored value (DATAOUT) on a falling edge of the clock CLK2 from figure 11, the PLL.

In contrast, the flip-flop F2 on the transmission side to transmit sync, enter the original value from the corresponding TDR_FF. Then in response to the control signal SG_P="1", introduced by the multiplexer M2, trigger F2 inverts its own output signal and again enters the inverted output signal, and then outputs the stored value in the form of a pulse (function) by inputting the clock CLK2 from figure 11, the PLL without inverting. This configuration get DATAOUT output trigger function F1 and the output trigger F2 equal to half the interval between them.

In this case, the synchronization signal CLK2 output from figure 11, the FAP is, is a clock having the same frequency as the Executive clock pulse that controls the chip And in the process the real work.

The following triggers F3 and F4 chip Century

The flip-flop F3 on the receiving side for receiving data enter the original value from the corresponding TDR_FF. After that the sync pulse function coming from the chip And injected into the trigger F3 as Executive sync STB_clk without inverting. In accordance with this Executive sync STB_clk trigger F3 collects DATAOUT coming from chip A. thus, the value (test data) DATAOUT output from trigger F3 (DP) and then zamalchivaut in TDR_DP to explore.

In contrast, the flip-flop F4, which is another trigger on the receiving side for receiving data, enter the original value from the corresponding TDR_FF. After that the sync pulse function coming from the chip And injected into the trigger F4 as Executive sync STB_clk with inverted. In accordance with this Executive sync STB_clk trigger F4 collects data DATAOUT coming from chip A. thus, the value (test data) DATAOUT output from trigger F4 (DN) and then zamalchivaut in TDR_DN to explore.

Figure 3 shows a chart illustrating the waveform in the trigger F3.

Consider figure 3. On the front of the eating front, the first of the two signals CLK2 from figure 11, the PLL chip And trigger F2 output clock pulse (function), a STB_clk subsides. Then on the trailing edge of the first clock CLK2 of the trigger F1 display the test data (DATAOUT). Further in the front edge of the second clock CLK2 complete the output of the sync pulse, a STB_clk increases, due to which the trigger F3 chip In (DP) registers the value of the test data. In this case, (Fl="0") drawings indicates that the trigger F1 is set to "0" corresponding TDR_FF. This also applies to the subsequent description.

Figure 4 shows a chart illustrating the waveform in the trigger F4.

Consider figure 4. In the front edge of the first of the two signals CLK2 from figure 11, the PLL chip And trigger F2 output clock pulse (function), a STB_clk increases. Then on the trailing edge of the first clock CLK2 of the trigger F1 display the test data (DATAOUT). Further in the front edge of the second clock CLK2 complete the output of the sync pulse, a STB_clk subsides, due to which the trigger F4 chip In (DN) registers the value of the test data.

The following describes how input values in triggers F1-F4 to synchronize with the source, which is used in this embodiment.

Figure 5 shows the circuit configuration initialization triggers F1 and F2 chips A. Shows the trigger with separate entrances is a trigger F1 or trigger F2 chips As shown in Fi is .2. As shown in figure 5, first in TDR_FF retain any value. Then, when UpdateDR_L="1", flip-flops F1 and F2 can be set or reset in accordance with the value stored in TDR_FF. The signal UpdateDR_L generate, as shown figure 11. This also applies to the subsequent description. In the form shown in the drawings example, when the value in the corresponding TDR_FF equal to "1", the discharge of each of flip-flops F1 and F2, and when the value in the corresponding TDR_FF equal to "0", carry out the installation. In particular, 11 based on figure 5-5 the above-mentioned non-patent document [1], and for generating signals a, b, C and D and shown in the drawings, the scheme used the notation corresponding to figure 5-5.

The above-described method initialization triggers F1 and F2 chips A. However, as in this embodiment, triggers, F3 and F4 chips have similar configuration, each of flip-flops F3 and F4 are set or reset by using the appropriate TDR_FF chip Century, Respectively, in the drawings used symbols F1, F2 (F3, F4).

Next, again with reference to figure 1 describes the dependence of the connection chip-level, including triggers for synchronization with the source of that test in this embodiment.

First consider the chip And on the transmission side. In addition to mentioned the x above FF_T and TDR_FF, chip And includes a circuit 11 PLL and controller 12 PLL for this test as a device for transmission to the Executive pulses generator 13 dual pulses to extract the twin impulses of the Executive pulses transmitted by the circuit 11, the PLL, and then output pulses, the controller 14 TAR (port access to the means test, English Test Access Port) to control JTAG and register 15 teams (IR, from the English - Instruction Register). The outputs of the controller 14 TAR and register 15 teams through the decoder commands, and logical elements A1, A2 and A3 are served in TDR_FF, FF_T, the generator 13 double pulses, etc.

The controller 12 PLL controls the circuit 11 PLL so that the circuit 11 PLL transmitting at the same frequency as during the actual work, after you save in register 15 teams a bit line (hereinafter referred to test bits of the JTAG commands, which corresponds to the test.

The logical element And A1 delivers the signal test TCK (Test Clock) in the appropriate TDR_FF, when a test bit is stored in register 15 teams, and in parallel, when ShiftDR="1".

The logical element And A2 through the corresponding TDR_FF delivers in every FF_T control signal to set or reset FF_T, when a test bit is stored in register 15 teams, and in parallel, when UpdateDR_L="1". From the values entered in accordance with the plans TDR_FF, as described above, whether to be set or unset FF_T. In this way determine the initial values FF_T.

The logical element And A3 delivers in every FF_T control signal SG_P for installation inside FF_T cyclic status, and submit to the generator 13 double pulse trigger signal to extract the dual pulses from the output signal of the circuit 11 PLL, when a test bit is stored in register 15 teams, and in parallel, when RunTestIdle="1" (see 11).

Next, consider the circuit In the on the receiving side. In addition to the above-mentioned FF_R and TDR_FF chip includes a controller 21 TAR for controlling JTAG and the register 22. The output signals of the controller 21 TAR and register 22 through the decoder commands and logical elements And A4 and A5 are received in TDR_FF etc.

The logical element And A4 gives the multiplexers M1 and M2 control signal, according to which the multiplexers M1 and M2 select display data "1"when a test bit is stored in the register 22, and then, when ShiftDR="1". Due to the fact that the multiplexers M1 and M2 select display data "1"is carried out by scanning tract TDI (test data input) - TDO (test data output) in accordance with the timing of the test TJC and enter a value in each of TDR_FF.

The logical element And A5 delivers in TDR_FF control signal to set the and or reset FF_R, when a test bit is stored in the register 22, and parallel to, when UpdateDR_L="1". From the values entered in the appropriate TDR_FF as described above, whether to be set or unset FF_R. In this way determine the initial values FF_R. In addition, the controller 21 TAR delivers in TDR_FF signal ClockDR to control the operation TDR_FF.

The following describes operations when testing using the scheme with the above-described configuration.

Figure 6 shows a diagram illustrating waveforms in the circuits a and b during testing, and 7 shows a flowchart illustrating the sequence of testing.

According to this variant implementation of the test consists of three main stages: stage input values in triggers (both at the transmitting and at the receiving side to synchronize with the source, stage actuation is synchronized with the source interface with the same speed as during actual operation, and the step of obtaining the test result.

As shown in Fig.7, the test according to this variant of the first implementation in each of the registers 15 and 22 of the chips a and b retain the test bit. Thereby trigger circuit 11 PLL circuits a and b for transmission to the Executive of the sync pulse (step 701). Then according to the arbitrary value is niceyou each of the triggers to synchronize with the source (FF_T and FF_R in figure 1 and F1-F4 figure 2) (step 702). This initialization triggers can be implemented in a way that conforms to the standard JTAG 1149, as described above. As shown in Fig.6, each of flip-flops F1 and F2 in the chip And initiated in accordance with the value entered in the corresponding TDR_FF, and each of flip-flops F3 and F4 in the chip In a similar manner initiated in accordance with the value entered in the corresponding TDR_FF.

In the future, the generator 13 double pulses, powered RunTestIdle="1" chip And on a transmitting side transmits a dual pulses derived from the output signal of the circuit 11 PLL, with double pulses have the same speed as the sync pulse during the actual operation (step 703). As shown in Fig.6, the output control signal SG_P to install a cyclic state FF_T and simultaneously output signals CLK2 dual pulses. It should be noted that RunTestIdle generate, as shown in figure 11.

Then, in accordance with a double pulse triggers F1 and F2 respectively transmit the test data stored in a flip-flop F1, and the sync pulse chip In on the receiving side (step 704). Triggers F3 and F4 chips To collect data transmitted by the trigger F1 circuits And, in accordance with a sync pulse that is transmitted by the trigger F2 (step 705).

After that, in response to the clockDR in micro the schem me In on the receiving side zamalchivaut values, registered triggers F3 and F4, respectively, in TDR_DP and TDR_DN. Then the value in the latch removed from the study TDO (test data output from the English - Test Data Out) (step 706). These data can be extracted from the TDO in accordance with the signal ClockDR coming from the controller 14 TAR, in a way that conforms to the standard JTAG 1149.

This method provides for the exchange of test data between the triggers on the transmission side, and triggers on the receiving side, in all cases to synchronize with the source with the same speed as during the actual work. By assessing the value (test result), registered on the receiving side, can be tested on the level of fees synchronous with the source interface at the operating frequency.

The second option exercise

In the second embodiment, described the following case. In particular, synchronization source is used a method in which a transmitting side transmits data and a clock pulse at the front of one of the sync pulse, and in parallel are set or reset flip-flops on the transmission side in accordance with the values initiated TDR_FF.

On Fig shows the complete configuration is synchronized with the source schema to which this option is applicable implementation. As shown in Fig, chip And is mikros the emnd on the transmission side, a chip is a chip on the receiving side. Although Fig shown only synchronous with the source areas of the scheme, it is assumed that both circuits a and b respectively are system diagrams. It should be noted, as shown in figure 1 the differences between the chips a and b only indicate whether each of the chips and the chip on the transmission side or the chip on the receiving side. In other words, each circuit in the ASIC is a chip a or chip b depending on the state (the transferor or the transferee) circuit in synchronous with the source interface. In the chips a and b FF_T indicates the trigger on the transmission side, FF_R indicates the trigger on the receiving side, a TDR_FF denotes JTAG_TDR. Their configuration similar to the configurations of the first variant implementation, respectively shown in Fig, 9 and 10.

On Fig illustrated the basic elements of the scheme to synchronize with the source, subject to the option exercise. As shown in Fig, triggers to synchronize with the source in the chip A (the transferor) is the trigger F11 data and trigger F12 to send a sync pulse, and the chip In (host) - triggers F13 and F14 for receiving data. Of flip-flops F13 and F14 on the receiving side is e trigger F13 collects data, transmitted by the trigger F11 at the forefront of the pulse transmitted by the trigger F12. Trigger F14 collects data transmitted by the trigger F11 on a falling edge of the sync pulse, transmitted by the trigger F12.

As shown in Fig, single trigger F12 to send a sync pulse has a single trigger F11, single trigger F13 and single trigger F14. However, in the real circuit single trigger F12 to send a sync pulse has several triggers, F11, and the number of triggers F13 and the number of triggers F14 in the chip In each case corresponds to the number of triggers F11 (see Fig). In addition, the circuits a and b there are several sets of such triggers F11-F14.

In addition, in the chip And the many triggers F11 and F12 on the transmission side forms a scan path for production tests, each of them is connected with the terminal of the data input (data input into the scan register) and terminal output data (output data from the scan register in the chip A. Similarly, in the chip triggers F13 and F14 on the receiving side to form a scan path, each of them is connected with the terminal of the data input (data input into the scan register) and terminal output data (output data from the scan register in the chip C. Each of flip-flops F11, F12, F13 and F14 condition is enableval/reset in response to the output signal of the corresponding TDR_FF (see Fig).

The following triggers F11 and F12 chip A.

The flip-flop F11 on the transmission side data type value (test data) from the corresponding TDR_FF. Then in response to the control signal SG_P="1", introduced by the multiplexer M1, trigger F11 inverts its own output signal and again enters the inverted output signal, and then outputs the stored value (DATAOUT) by inputting the clock CLK2 from figure 11, the PLL without inverting.

In contrast, the flip-flop F12 on the transmission side to transmit sync, enter the original value from the corresponding TDR_FF. Then in response to the control signal SG_P="1", introduced by the multiplexer M2, trigger F12 inverts its own output signal and again enters the inverted output signal, and then outputs the stored value in the form of a pulse (function) by inputting the clock CLK2 from figure 11, the PLL without inverting. This configuration get DATAOUT output trigger F11 and function at the output of the trigger F12 on the front of one of the sync pulse.

In this case, the synchronization signal CLK2 output from the circuit 11 PLL, is the Executive pulse to control the chip And in the process the real work.

The following triggers F13 and F14 chip Century

The flip-flop F13 on the receiving side for receiving data enter the initial value of the C corresponding TDR_FF. Then in scheme 23 DLL delay by π/2 the length of the period function coming from the chip And then the delayed function is injected into the trigger F13 as Executive sync DDL_clk without inverting. In accordance with this Executive sync DDL_clk trigger F13 collects DATAOUT coming from chip A. thus, the value (test data) DATAOUT output from trigger F13 (DP) and then zamalchivaut in TDR_DP to explore.

In contrast, the flip-flop F14, which is another trigger on the receiving side for receiving data, enter the original value from the corresponding TDR_FF. Then in scheme 23 DLL delay by π/2 the length of the period function coming from the chip A, and enter the sync pulse function as the Executive of sync DDL_clk. Then the Executive clock pulse DDL_clk injected into the trigger F14 with inverted. In accordance with this Executive sync DDL_clk trigger F14 collects DATAOUT coming from chip A. thus, the value (test data) DATAOUT output from trigger F14 (DN) and then zamalchivaut in TDR_DN to explore.

On Fig shows a diagram illustrating a waveform in the trigger F13.

Consider Fig. In the front edge of the first of the two signals CLK2 supplied from figure 11, the PLL chip And, at the same time display the test on the installed (DATAOUT) flip-flop F11 and the sync pulse (function) flip-flop F12. Then DDL_clk increases with delay of π/2 relative to this clock. As a result, the period of growth DDL_clk shifts in the middle of the test data. In response to this increase DLL_clk trigger F13 chip In (DP) registers the value of the test data.

On Fig shows a diagram illustrating a waveform in the trigger F14.

Consider Fig. In the front edge of the first of the two signals CLK2 supplied from figure 11, the PLL chip And, at the same time display the test data (DAT AOUT) flip-flop F11 and the sync pulse (function) flip-flop F12. Then DDL_clk subsides delayed by π/2 relative to this clock. As a result, the period of decline DDL_clk shifts in the middle of the test data. In response to this decline DLL_clk trigger F14 chip In (DN) registers the value of the test data.

In this embodiment, the triggers F11-F14 to synchronize with the source as triggers F1-F4 of the first variant implementation, the set/reset in accordance with the output signals of the respective TDR_FF as described above. Therefore, when the configuration of the circuit shown in figure 5, each of flip-flops F11-F14 enter the original value in a manner analogous to the method used in the first embodiment.

Next, again with reference to Fig describes the dependence of the connection chip-level, including triggers to sync the saved source, which test in this embodiment.

First consider the chip And on the transmission side. In addition to the above-mentioned FF_T and TDR_FF, chip And includes a circuit 11 PLL and controller 12 PLL as a device for transmission to the Executive pulses generator 13 dual pulses to extract the twin impulses of the Executive pulses transmitted by the circuit 11, the PLL, and then output pulses, the controller 14 TAR to control JTAG and register 15 teams (IR). The outputs of the controller 14 TAR and register 15 teams through logic elements A1, A2 and A3 are served in TDR_FF, FF_T, the generator 13 double pulses, etc.

The controller 12 PLL controls the circuit 11 PLL so that the circuit 11 PLL transmitting at the same frequency as during the actual work, after you save the test bit in the register 15 teams.

The logical element And A1 delivers the TSC in the respective TDR_FF, when a test bit is stored in register 15 teams, and in parallel, when ShiftDR="1".

The logical element And A2 through the corresponding TDR_FF delivers in every FF_T control signal to set or reset FF_T, when a test bit is stored in register 15 teams, and in parallel, when UpdateDR_L="1". From the values entered in the appropriate TDR_FF as described above, whether to be set or unset FF_T. In this way, the definition is given in the original values FF_T. At the same time as the test data enter the original value FF_T, including trigger F1 shown in Fig.

The logical element And A3 delivers in every FF_T control signal SG_P for installation inside FF_T cyclic status, and submit to the generator 13 double pulse trigger signal to extract the dual pulses from the output signal of the circuit 11 PLL, when a test bit is stored in register 15 teams, and in parallel, when RunTestIdle="1".

Next, consider the circuit In the on the receiving side. In addition to the above-mentioned FF_R and TDR_FF, the chip includes a controller 21 TAR for control JTAG, the register 22, the circuit 23 DDL delay sync pulse and the controller 24 of the clock management scheme 23 DDL and not shown by the PLL. The output signals of the controller 21 TAR and register 22 through the logic elements And A4 and A5 are received in TDR_FF etc.

The controller 24 clock controls the circuit 23 (DDL) and the PLL so that the circuit 23 DDL not shown, the PLL could transmit on the same frequency as during the actual work after you save the test bit in the register 22.

The logical element And A4 gives the multiplexers M1 and M2 control signal, according to which the multiplexers M1 and M2 select display data "1"when a test bit is stored in the register 22, and then, to the Yes ShiftDR="1". Due to the fact that the multiplexers M1 and M2 select display data "1"is carried out by scanning tract TDI (test data input) - TDO (test data output) in accordance with the timing of the test TJC and enter a value in each of TDR_FF.

The logical element And A5 through appropriate TDR_FF delivers in every FF_R control signal to set or reset FF_R, when a test bit is stored in the register 22, and parallel to, when UpdateDR_L="1". From the values entered in the appropriate TDR_FF as described above, whether to be set or unset FF_R. In this way determine the initial values FF_R.

ClockDR controller 21 TAR delivers the signal testing TJC in TDR_FF when ShiftDR="1" or when CaptureDR="1". In accordance with the received timing of the test TJC perform the scan path of TDI-TDO, as well as, for example, TDR_FF collects data stored in FF_R.

When testing the circuit with the above-described configuration perform approximately the same operations as in the first embodiment described with reference to Fig.6 and 7.

The operation according to the second variant of implementation are distinguished by the following features from operations according to the first variant implementation.

First, in the first embodiment, the period of the output test data from the trigger F1 and the period you is ode of the sync pulse from trigger F2 separated by a time interval, equal to half the period. In contrast, in the second embodiment, the output test data from the trigger F11 and the output pulse from trigger F12 perform in front of one of the sync pulse.

In addition, in the first embodiment, in step 705, shown in Fig.7, triggers, F3 and F4 collect test data transmitted by the trigger F1, in accordance with a sync pulse that is transmitted by the trigger F2. In contrast, as in the second embodiment, the front of the sync pulse, which is output test data from the trigger F11, and the front of the clock on which the output clock pulse from trigger F12, have the same period, the sync pulse is delayed by π/2 in scheme 23 DLL. Then triggers F13 and F14 collect test data in accordance with this delayed sync pulse.

A third option exercise

As in the second embodiment, in the third embodiment, to synchronize with the source used a method in which a transmitting side transmits data and a clock pulse at the front of one of the sync pulse. However, in the third embodiment described a case where initialization is used, the way in which in JTAG_TDR enter a value, allowing the trigger on the transmission side to play the role of JTAG_TDR.

On Fig shows the complete configuration synchronous with and is a source schema, to which we apply this alternative implementation. As shown in Fig, chip And is the chip on the transmission side, and the chip is a chip on the receiving side. Although Fig shown only synchronous with the source areas of the scheme, it is assumed that both circuits a and b respectively are system diagrams. It should be noted that shown in Fig differences between the chips a and b only indicate whether each of the chips and the chip on the transmission side or the chip on the receiving side. In other words, each circuit in the ASIC is a chip a or chip b depending on the state (the transferor or the transferee) circuit in synchronous with the source interface.

In the chips a and b FF_T indicates the trigger on the transmission side, FF_R indicates the trigger on the receiving side, a TDR_FF denotes JTAG_TDR. As in this embodiment, FF_T also serve TDR_FF, in the chip And there is no TDR_FF. The configuration of one of these triggers FF_T on the transmission side shown in Fig. Configuration FF_R and TDR_FF chip In similar configurations of the first variant implementation, shown in figures 9 and 10.

On Fig illustrated the basic elements of the scheme to synchronize with the source, which is the subject of this Varian is and implementation. As shown in Fig, triggers to synchronize with the source in the chip A (the transferor) is the trigger F21 data and trigger F22 to send a sync pulse, and the chip In (host) - triggers F13 and F14 for receiving data. From triggers, F23 and F24 on the receiving side trigger F23 collects data transmitted by the trigger F21 at the forefront of the pulse transmitted by the trigger F22. Trigger F24 collects data transmitted by the trigger F21 on a falling edge of the sync pulse, transmitted by the trigger F22.

As shown in Fig, single trigger F22 to send a sync pulse has a single trigger F21, single trigger F23 and single trigger F24. However, in the real circuit single trigger F22 to send a sync pulse has several triggers, F21, and the number of triggers F23 and the number of triggers F24 in the chip In each case corresponds to the number of triggers F21 (see Fig). In addition, the circuits a and b there are several sets of such triggers F21-F24.

In addition, in the chip And the many triggers F21 and F22 on the transmission side to form a scan path for production tests, each of them is connected with the terminal of the data input (data input into the scan register) and terminal output data (output data from the scan register is in chip A. Similarly, in the chip triggers F23 and F24 on the receiving side to form a scan path, each of them is connected with the terminal of the data input (data input into the scan register) and terminal output data (output data from the scan register in the chip Century

In this embodiment, in each of the triggers F21 and F22 enter the initial value by scanning paths of the data shifted through the corresponding scan path. At the same time, each of the triggers F21, F22, F23 and F24 set/reset in response to the output signal of the corresponding TDR_FF (see Fig). The following triggers F21 and F22 chip A.

The flip-flop F21 on the transmission side data type value (test data through the scan path JTAG_TDR passing through pins 1 and 0, respectively multiplexers M3 and M1. Then in response to the control signal SG_P entered by the multiplexer M1, trigger F21 inverts its own output signal and again enters the inverted output signal, however, he introduces the synchronization signal CLK2 from figure 11, the PLL without its inverting and thereby outputs the stored value (DATAOUT).

In contrast, the flip-flop F22 on a transmitting side for transmitting data enter the original value through the scan path JTAG_TDR passing through pins 1 and 0 respectively multiplex the s M4 and M2. Then in response to the control signal SG_P entered by the multiplexer M2, trigger F22 inverts its own output signal and again enters the inverted output signal, however, he introduces the synchronization signal CLK2 from figure 11, the PLL without its inverting and thereby outputs the stored value in the form of a pulse (function). This configuration get DATAOUT output trigger F21 and function at the output of the trigger F22 on the front of one of the sync pulse.

In this case, the synchronization signal CLK2 output from the circuit 11 PLL, is the Executive pulse to control the chip And in the process the real work.

The following triggers F23 and F24 chip Century

The flip-flop F23 on the receiving side for receiving data enter the original value from the corresponding TDR_FF. Then in scheme 23 DLL delay by π/2 the length of the period function coming from the chip And then the delayed function is injected into the trigger F23 as Executive sync DDL_clk without inverting. In accordance with this Executive sync DDL_clk trigger F23 collects DATAOUT coming from chip A. thus, the value (test data) DATAOUT output from trigger F23 (DP) and then zamalchivaut in TDR_DP to explore.

In contrast, the trigger F24, which is another trigger on the receiving side for receiving data, enter ex is the initial value of the corresponding TDR_FF. Then in scheme 23 DLL delay by π/2 the length of the period function coming from the chip A, and enter the sync pulse function as the Executive of sync DDL_clk. Then the Executive clock pulse DDL_clk injected into the trigger F24 with inverted. In accordance with this Executive sync DDL_clk trigger F24 collects DATAOUT coming from chip A. thus, the value (test data) DATAOUT output from trigger F24 (DN) and then zamalchivaut in TDR_DN to explore.

On Fig shows a diagram illustrating a waveform in the trigger F23.

Consider Fig. In the front edge of the first of the two signals CLK2 supplied from figure 11, the PLL chip And, at the same time display the test data (DATAOUT) flip-flop F21 and the sync pulse (function) flip-flop F22. Then DDL_clk increases with delay of π/2 relative to this clock. As a result, the period of growth DDL_clk shifts in the middle of the test data. In response to this increase DLL_clk trigger F23 chip In (DP) registers the value of the test data.

On Fig shows a diagram illustrating a waveform in the trigger F24.

Consider Fig. In the front edge of the first of the two signals CLK2 supplied from figure 11, the PLL chip And, at the same time display the test data (DATAOUT) flip-flop F21 and the sync pulse (function) flip-flop F22. Then DDL_clk recession is no delayed by π/2 relative to this clock. As a result, the period of decline DDL_clk shifts in the middle of the test data. In response to this decline DLL_clk trigger F24 chip In (DN) registers the value of the test data.

Further, in this embodiment, described by way of input values in triggers F21-F24 to synchronize with the source.

On Fig shows the circuit configuration initialization triggers F21 and F22 chip A. As shown in Fig when ShiftDR="1", the multiplexer S1 receives the control signal SS_P that was selected ClockDR for submission to the triggers F21 and F22. In accordance with this signal ClockDR triggers F21 and F22 enter the data from the TDI (test data input) JATG to initiate triggers F21 and F22.

In contrast, triggers, F23 and F24 chip In set/reset, as in the case of triggers F1-F4 to synchronize with the source in the first embodiment, in accordance with output signals TDR_FF. Therefore, when the configuration of the circuit shown in figure 5, the original value is introduced into the triggers F23 and F24 in the same way as in the first embodiment.

Next, again with reference to Fig describes the dependence of the connection chip-level, including triggers for synchronization with the source of that test in this embodiment.

First consider the chip And on the transmission side. In addition to the above-mentioned FF_T, who iroshima And includes circuit 11 PLL and controller 12 PLL as a device for transmission to the Executive pulses the generator 13 dual pulses to extract the twin impulses of the Executive pulses transmitted by the circuit 11, the PLL, and then output pulses, the controller 14 TAR to control JTAG and register 15 teams (IR). The outputs of the controller 14 TAR and register 15 teams through logic elements A1 and A3 are served in FF_T, the generator 13 double pulses, etc.

The controller 12 PLL controls the circuit 11 PLL so that the circuit 11 PLL transmitting at the same frequency as during the actual work, after you save the test bit in the register 15 teams.

The logical element And A1 delivers the signal ClockDR in TDR_FF, when a test bit is stored in register 15 teams, and in parallel, when ShiftDR="1". The result is directly initiate FF_T.

The logical element And A3 delivers in FF_T control signal SG_P for installation within each of FF_T cyclic status, and submit to the generator 13 double pulse trigger signal to extract the dual pulses from the output signal of the circuit 11 PLL, when a test bit is stored in register 15 teams, and in parallel, when RunTestIdle="1".

Next, consider the circuit In the on the receiving side. In addition to the above-mentioned FF_R and TDR_FF, the chip includes a controller 21 TAR for control JTAG, the register 22, the circuit 23 DDL delay sync pulse and the controller 24 clock for the management scheme 23 DDL and not shown by the PLL. The output signals of the controller 21 TAR and register 22 through the logic elements And A4 and A5 are received in TDR_FF etc.

The controller 24 clock controls the circuit 23 (DDL) and the PLL so that the circuit 23 DDL not shown, the PLL could transmit on the same frequency as during the actual work after you save the test bit in the register 22.

The logical element And A4 gives the multiplexers M1 and M2 control signal, according to which the multiplexers M1 and M2 select display data "1"when a test bit is stored in the register 22, and parallel to, when ShiftDR="1". Due to the fact that the multiplexers M1 and M2 select display data "1"is carried out by scanning tract TDI (test data input) - TDO (test data output) in accordance with the timing of the test TJC and enter a value in each of TDR_FF.

The logical element And A5 delivers through TDR_FF control signal to set or reset FF_R, when a test bit is stored in the register 22, and parallel to, when UpdateDR_L="1". From the values entered in the appropriate TDR_FF as described above, whether to be set or unset FF_R. In this way determine the initial values FF_R.

ClockDR controller 21 TAR delivers the signal testing TJC in TDR_FF when ShiftDR="1" or when CaptureDR="1". In accordance with synchro is ignalum testing TJC perform the scan path of TDI-TDO, a TDR_FF collect data that is stored in FF_R.

The following describes operations when tested using the circuit having the above configuration.

On Fig shows a diagram illustrating waveforms in the circuits a and b during testing. Because the test sequence similar to the sequence according to the first variant implementation, which is described with reference to Fig.7, then it is also described with reference to Fig.7.

First, in each of the registers 15 and 22 respectively of circuits a and b retain the test bit. Thereby trigger circuit 11 PLL circuits a and b (PLL chip not shown) for transmission to each of the Executive pulse (step 701). Then according to an arbitrary value initiate each of the triggers to synchronize with the source (FF_T and FF_R on Fig and F21-F24 on Fig) (step 702).

In this embodiment, each of the triggers also initiate a manner consistent with the standard JTAG 1149. However, consider Fig. Shown in Fig multiplexer S1 selects the synchronization signal ClockDR output controller 14 TAR in accordance with the signal SS_P, which carried out the scan paths of the data shifted in accordance with the synchronization signal ClockDR. The result is immediate mandatory UN paid the mineralisation triggers F21 and F22, in introducing the test data. At the same time, as in the first embodiment, triggers, F23 and F24 chip initiate in accordance with stored in TDR_FF values that correspond to triggers F21 and F22, as shown on the timing diagram of the signals (note that this initialization is carried out earlier than the initialization triggers F21 and F22 chip).

In the future, the generator 13 double pulses, powered RunTestIdle="1" chip And on a transmitting side transmits a dual pulses from the output signal of the circuit 11 PLL (step 703). In this embodiment, the output signal CLK2 generator 13 double pulses is chosen is shown in Fig the multiplexer S 1, when ShiftDR="0". As shown in Fig.6, the output control signal SG_P for installation inside FF_T cyclic condition, then output signals CLK2 to obtain the dual impulses.

Then, in accordance with a double pulse triggers F1 and F22 respectively transmit the test data stored in a flip-flop F1, and the sync pulse chip In on the receiving side (step 704). Triggers F23 and F24 chips To collect data transmitted by the trigger F21 chip And, in accordance with a sync pulse that is transmitted by the trigger F22 (step 705). After that, the chip In on the receiving side latches shall indicate the value, registered triggers F23 and F24, respectively, in TDR_DP and TDR_DN. Then the value in the latch removed from the study TDO (step 706).

In the above description of the first to the third embodiments of the examples were the cases in each of them as triggers to synchronize with the source use triggers, forming the path of the JTAG scan. However, it is obvious that there may be other configuration, provided that they correspond to the nature and scope of the present invention. In particular, the input values and the study results can easily be done using channel scan in addition to tract the JTAG scan. In modern ASIC commonly used configuration for testing by scanning using JTAG. Accordingly, it is preferable that the test was conducted with the use of such triggers, forming the scan path. However, it is not excluded the case when for testing interconnects according to the considered variants of implementation in ASIC may apply a different circuit configuration.

1. A microcomputer that has two or more integrated circuits (IC), connected with each other in sync with the source interface, characterized in that
there is a IP side to send data through the synchronous source interface, including
a diagram of the phases of the howl-locked loop (PLL) for transmission to the Executive synchronizing pulse during the actual work,
the first trigger for the transmission of test data in accordance with the Executive pulse passed by the PLL, and
the second trigger for the transmission of synchronous with the source clock in accordance with the Executive pulse passed by the PLL, and
there is a IP side to receive data via synchronous with the source interface, including
the third trigger for collecting test data transmitted by the first trigger in accordance with a sync pulse that is transmitted by the second trigger.

2. The microcomputer according to claim 1, characterized in that IP on the transmission side includes in addition to the generation scheme of the dual pulses to extract a double-pulse signals of the Executive pulses transmitted by the PLL, the first trigger is capable of transmitting test data in accordance with a double-pulse signals extracted from the schema generate double pulses, and
the second trigger is capable of transmitting clock pulse in accordance with a double-pulse signals extracted from the schema generation dual impulses.

3. The microcomputer according to claim 1, characterized in that the first trigger IP on the transmitting side can transmit the test data with a delay equal to half of a double-pulse signals, relative to the sync pulse, the transmitted second trigger is m

4. The microcomputer according to claim 1, characterized in that
the first trigger IP on the transmitting side can transmit the test data at the front of the same clock as the clock pulse transmitted by the second trigger, and
IP on the receiving side has a delay means for transmitting the received sync pulse to the third trigger with a delay of π/2.

5. The microcomputer according to claim 1, characterized in that the first trigger IP on the transmission side is a trigger with separate entrances, and
IP on the transmitting side further includes a test data register to save the test data in the first trigger by setting or resetting the first flip-flop in accordance with the stored value.

6. The microcomputer according to claim 1, characterized in that the first trigger IP on the transmission side forms a scan path, and the test data is introduced into the first trigger by scanning paths of the data shifted through the scan path.

7. The way to test a microcomputer that has two or more integrated circuits (IC), connected with each other in sync with the source interface, including:
the stage at which the IP-side data through the synchronous source interface type of the original value of the first trigger data and the second trigger for the transmission of sync,
is Tadeu, which transmit the synchronization signal of the PLL for transmission to the Executive synchronizing pulse during the actual operation, after which the first trigger and the second trigger respectively transmit data to their original values and the sync pulse, and
the stage at which the IP-side of receiving data via synchronous with the source interface by means of a third trigger for receiving data collect baseline values transmitted by the first trigger in accordance with a sync pulse that is transmitted by the second trigger.

8. The method of testing according to claim 7, characterized in that the phase of the input values in the first and second triggers include:
the step at which each of the registers testing, coordinated respectively with the first and second triggers, stores the specified value, and
step through registers testing in accordance with the stored their values are set or reset the first trigger and the second trigger for input values in the first trigger and the second trigger.

9. The method of testing according to claim 7, characterized in that at the stage of input values in the first trigger and the second trigger original values introduced by the scanning paths of the data shifted through the scan path relative to the first trigger and the second trigger, forming the scan path

10. The way to test a microcomputer that has two or more integrated circuits (IC), connected with each other in sync with the source interface, including:
the stage at which by means of a trigger on the side of the transmission data through the synchronous source interface receive and store test data,
the stage at which transmit the synchronization signal of the PLL for transmission to the Executive synchronizing pulse during the actual work, and then transmit the test data stored in the trigger on the transmission side, and synchronous with the clock pulse source and
the stage at which by means of a trigger on the side of receiving data via synchronous with the source interface collect test data in accordance with a sync pulse.

11. The testing method of claim 10, wherein the stage of receiving test data trigger on the transmission side includes:
step on which save set value in the register is a test data corresponding to the trigger on the transmission side, and
a step in which in accordance with the value stored in the register test data, perform the setting or resetting of the trigger on the transmission side, which corresponds to the test data register to trigger on the transmission side has retained test data.

12. The method of testing p, characterized in that at the stage of acceptance test data trigger on a transmitting side via a trigger on the transmission side retain the test data through the scan path test data shifted through the scan path relative to the trigger on the transmission side, forming the scan path.



 

Same patents:

FIELD: technical systems diagnostics.

SUBSTANCE: method includes forming an equivalent standard model of connections, gaps of which include standard models of composition parts of current type of products, combinations of input signals are set in certain order, parameters of response on outputs of standard model of diagnosed product are determined as well as in characteristic intermediate points between standard models of composition parts of product, values of response parameters together with parameters of test input signals are recorded in database, after which process is repeated until fully searching all states of standard model.

EFFECT: possible forming of tests in absence of standard samples of control subject for different classes of products in different areas.

4 dwg

FIELD: measuring equipment.

SUBSTANCE: in turns, on each device, included in diagnosed block, feeding voltage amplitude is decreased in steps from nominal value Enom to threshold value Ethri with step ΔEn, while on each step of decreasing of amplitude of feeding voltage of device pseudo-random multi-digit code sets are sent to inputs of diagnosed block, consisting of logical zeroes and ones with even possibility of appearance of logical zero or logical one in each digit, received logic levels are recorded on outputs of diagnosed digital block and compared to standard levels, and when error frequency Fc appears, voltage value Ethri is recorded (functioning threshold) for each device and its functioning area is calculated on basis of feeding voltage ΔEpi. Defective (potentially malfunctioning) device is detected on basis of lowest value in functioning area ΔEpi, which is selected on basis of comparison of functioning areas of all devices, included in diagnosed digital block.

EFFECT: higher precision, higher efficiency.

1 dwg

The invention relates to the repair and maintenance of personal computers, namely, to the diagnosis of the health of hardware and software

The invention relates to the field of test and control digital semiconductor integrated circuits (IC) and can be used in assembling electronic means when the input control values of radiation resistance IP containing memory)

The invention relates to computing

The invention relates to the field of automation and computing, in particular to devices for controlling electrical installation

The invention relates to computer technology, and automation and can be used to build tools for monitoring and diagnosing discrete blocks of electronic equipment

The invention relates to the field of automation and computing, in particular to devices for controlling electrical installation

FIELD: measuring equipment.

SUBSTANCE: in turns, on each device, included in diagnosed block, feeding voltage amplitude is decreased in steps from nominal value Enom to threshold value Ethri with step ΔEn, while on each step of decreasing of amplitude of feeding voltage of device pseudo-random multi-digit code sets are sent to inputs of diagnosed block, consisting of logical zeroes and ones with even possibility of appearance of logical zero or logical one in each digit, received logic levels are recorded on outputs of diagnosed digital block and compared to standard levels, and when error frequency Fc appears, voltage value Ethri is recorded (functioning threshold) for each device and its functioning area is calculated on basis of feeding voltage ΔEpi. Defective (potentially malfunctioning) device is detected on basis of lowest value in functioning area ΔEpi, which is selected on basis of comparison of functioning areas of all devices, included in diagnosed digital block.

EFFECT: higher precision, higher efficiency.

1 dwg

FIELD: technical systems diagnostics.

SUBSTANCE: method includes forming an equivalent standard model of connections, gaps of which include standard models of composition parts of current type of products, combinations of input signals are set in certain order, parameters of response on outputs of standard model of diagnosed product are determined as well as in characteristic intermediate points between standard models of composition parts of product, values of response parameters together with parameters of test input signals are recorded in database, after which process is repeated until fully searching all states of standard model.

EFFECT: possible forming of tests in absence of standard samples of control subject for different classes of products in different areas.

4 dwg

FIELD: information technologies.

SUBSTANCE: microcomputer (ASIC) comprises multiple integral circuits (IC), which are connected to each other with interfaces that are synchronous to data sources. At first test data is input into trigger for data transfer (F1) and trigger for transfer of clock pulse (F2) into IC on the side of data transfer. Then circuit (11) of phase locking generates clock signal, in response to which the first and second triggers send test data and clock pulse. Triggers (F3, F4) for reception of IC data on the side of data reception, test data is registered, which come from the first trigger (F1) in compliance with clock pulse, which comes from trigger (F2).

EFFECT: provision of testing at working frequency at the level of circuit boards without application of system level test, and assessment of data sent along each transfer channel.

12 cl, 21 dwg

FIELD: physics; communications.

SUBSTANCE: invention relates to simulation and can be used in designing radio-electronic, engineering systems for evaluating operational characteristics. The outcome is achieved by measuring performance indices of a real communication network, simulating functioning processes of the simulated communication network and comparing the values.

EFFECT: possibility of simulating movement of communication network elements (nodes and communication devices) and subscribers (users) of the communication network; simulation of features of physical and geographical conditions of the region where the communication network is operating and where subscribers (users) are located; simulation network topology changes, change in communication channel (line) capacity; as well as increased simulation adequacy taking into account functioning processes of a real communication network.

7 dwg

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to micro- and nanotechnology and can be used when controlling and diagnosing microprocessor systems. The automated device for testing microprocessor systems contains the following: a testing module (1), units for permanent (2) and on-line storage of data, a unit for processing results and information (5), a control unit (4) which is a switch, a setting device (8), first (6) and second (7) interfaces. The units for permanent (2) and on-line (3) storage of data and the control unit (4) can be made as part of the tested object.

EFFECT: broader functional capabilities of the automated device due to possibility of detecting undocumented units and commands in a microprocessor system.

1 dwg

FIELD: information technology.

SUBSTANCE: in the method of creating control-diagnostic tests before creating the tests through digital shooting in optical range, pictures of the non-component side of the article with clear identification of types of radio components thereon and their position is obtained. For each combination of input test electrical signals, simultaneously with determination of standard values of parametres of electrical response signals from outputs of a standard sample of the article of the given type which is known to be fault-free, standard digital infrared images of the standard sample of the article of the given type are obtained through digital infrared video shooting, where the said infrared images display the differences between thermal conditions of the radio components in places where they are located on the fault-free standard sample of the article of the given type. The obtained data are entered into the computer data base of the control-diagnostic installation and are used for subsequent monitoring of correct operation and diagnosing faults in articles of the given type.

EFFECT: detection of faulty radio components without violating integrity of moisture-proof coating of the article, high efficiency and reliability of diagnosis.

5 cl, 2 dwg

FIELD: information technologies.

SUBSTANCE: automated repair bench comprises a computer with software and hardware, which includes 10 input-output devices, an analogue generator, a logical analyser, a digital oscillograph, power supply units, an internal local bus, a unit of external slots for connection of a tested device, and also an intellectual controller, comprising an inbuilt 32-digit processor on a crystal (NIOS-processor), connected to the computer along a USB bus and with a main memory of a fast memory DDR type, and also with a bus arbiter connected to an address port and an input-output port of the intellectual controller, connected with the internal local bus, at the same time all internal devices of hardware are controlled by the 32-digit processor on a crystal (NIOS-processor) along the internal local bus. (n+1) relay control units are connected to the internal local bus, and each of them comprises 64 input-output lines, ensuring operation with radio-electronic equipment, comprising electromagnet relays. Each relay control unit comprises (n+1) input-output devices, every of which comprises 64 input-output lines.

EFFECT: higher efficiency of testing digital-to-analogue devices and devices that comprise relays.

3 cl, 1 dwg

FIELD: electricity.

SUBSTANCE: generation of control and diagnostic tests is carried out on the basis of mathematical models of control objects built on circuits of electric principal control objects, mathematical models of electric radio elements (ERE) and parameters of electric signals for passport modes of ERE operation, and generation of reference thermal portraits of radioelectronic equipment (REE) items - a control object - is carried out by means of synthesis on the basis of individual thermal portraits of ERE of appropriate types and a drawing of the control object overview.

EFFECT: provision of the possibility to generate diagnostic tests for thermal imaging diagnostics of radio-electronic equipment faults when there are no reference samples of REE available.

2 dwg

FIELD: information technology.

SUBSTANCE: number of dynamic modules of a controlled system is determined, the reaction of a good system is recorded at an interval at control points and integral estimates of output signals of the system are determined. System signals are transmitted to the first inputs of multiplier units; an arithmetic mean value of moduli of signal time derivatives is transmitted to second inputs of the multiplier units; output signals of the multiplier units are transmitted to inputs of integration units; integration is completed at a certain moment in time; output signal estimates obtained from integration are recorded; simultaneously, integral estimates of signals of models are determined for each of the control points, obtained as a result of test deviations of parameters of each of the modules, for which a corresponding test deviation of parameters is introduced into each model for the dynamic system module. Deviations of integral estimates of signals of the model, obtained as a result of test deviations of parameters of corresponding modules, are determined. Standardised values of deviations of integral estimates of signals of the model are determined. Standardised values of deviations of integral estimates of signals are determined. Diagnostic features are determined and a faulty module is determined from the minimum value of the diagnostic feature.

EFFECT: increased noise-immunity of diagnosing continuous automatic control systems.

1 dwg

FIELD: information technology.

SUBSTANCE: disclosed is a method for preliminary assessment of quality of diagnostic tests, consisting in that, based on the description of internal parts of the diagnosed article, an equivalent standard model of connections is formed; for the obtained standard model of the diagnosed article, combinations of input test signals are formed; for each combination of input test signals, parameters of combinations of output signals are determined, wherein at the inputs of the obtained standard model of the diagnosed article, corresponding combinations of input signals are given in a corresponding sequence given in the assessed diagnostic test; for each combination of given input signals, except the first, parameters of combinations of response signals at the outputs of the standard model of the diagnosed article and in characteristic intermediate points between standard models of component parts of the article are determined and, by comparing response signals obtained for the previous combination of given input signals, change in values of response signals is determined; preliminary efficiency of the diagnostic test is calculated; a preliminary decision on sufficient quality of the assessed diagnostic test is made, as a result of which the assessed diagnostic test is sent for refinement or for experimental checking.

EFFECT: shorter time for diagnosing engineering systems.

5 dwg, 1 tbl

Up!