Device for information processing

FIELD: information technologies.

SUBSTANCE: invention is related to computer engineering and may be used in building neuronet information processing systems. Device comprises parallel bus connected to units of data input and output, units of result memory stack, related to units of local data memory, local memory of data availability, local memory of commands, local memory of functional parametres, ring-bus circuit, with which operational units are related, as well as units of local data memory, local memory of commands, local memory of functional parametres, local memory of data availability and vacant register, local stacks of data packets, which are connected to according operational units, parallel bus, register of availability and with priority circuit with cyclic assignment of priorities, which is connected by availability register and to units of result memory stack.

EFFECT: improved efficiency of device due to data packet buffering and provision of equiprobable servicing of data packet stacks with the help of mechanism for cyclic assignment of priorities.

2 cl, 2 dwg

 

The invention relates to computing and can be used to build neural information processing systems.

A device for processing information on the basis of regular memory structures oriented parallel execution of computation and containing interconnected through a switch operating blocks, memory blocks and blocks of input/output data [D. Patterson, T. Anderson, Cadwell N. and other Arguments in favor of IRAM. - Computerra, No. 15, 1998 P.3-14].

The drawbacks are the orientation of the technical solutions on the concept of consistent management of computing and a limited number of processor units. Due to the limited number of processor units this unit does not effectively address the problem of neural network basis with a high degree of parallelization of the computational process.

It is also known a device for processing information containing the operational blocks, interlocking blocks local memory commands and the local data memory blocks stack memory results, are connected to the outputs of the respective operating units and the inputs of the same blocks local memory data, blocks of data input and output connected to the parallel bus [Computers on VLSI: 2 kN. Book 1: TRANS. with jap. / Motooka T., Tomita S. and the R. - M.: Mir, 1988, Pp. 102-107].

The disadvantage of this device is the software parallelization of computations: at compile time is determined by the possibility of simultaneous execution of individual program fragments and their distribution by operational units, which number in the device is limited, which does not allow to fully realize the potential of parallelization of the problem-solving process. The device does not have hardware aimed at solving the problems inherent in the neural network basis.

The closest technical solution of the present invention and selected by the authors for the prototype is a device for processing information containing the operational blocks whose inputs are interconnected with the outputs of blocks local memory commands and blocks local data memory, and the outputs from the first bus, the blocks stack memory results, the inputs of which are connected with the second bus and the outputs to the inputs of corresponding blocks local memory data, blocks of data input and output connected to the first bus, characterized in that it contains a number of blocks local memory data blocks local memory functional parameters and blocks local memory ready data triggers of employment by the number of operating units, the third bus in the form of a ring, through the which are interconnected inputs of operational blocks, the outputs of the triggers of employment, the outputs of blocks local memory data blocks local memory commands, blocks local memory functional parameters and units of local memory data availability, and the inputs of blocks local memory functional parameters and blocks local memory commands is connected to the first bus, which together with the second bus forms a ring bus and the inputs of blocks local memory data availability are connected to the outputs of the same blocks stack memory results [RF patent 2179739, IPC G06F 15/00. A device for processing information / Graniterock, Fgeneral. No. 2000108883/09; Claimed 10.04.2000. Publ. 20.02.2002. Bull. No. 5. Priority from 10.04.2000].

The disadvantage of the prototype is limited bandwidth ring bus connecting the output bus operating units and the input bus of the blocks stack memory results and, consequently, reducing the overall performance of the device due to downtime operating blocks waiting for data to arrive.

The present invention is to increase the device performance due to local buffering of data packets generated by the operational units, and provide more efficient services buffered data packets through the mechanism of uniform circular prioritization.

P the set objective is achieved by in the device for processing information entered local stacks of data packets, the input bus which is connected to the output buses of the same name operating units, the output bus is a parallel bus, and the first control outputs - control inputs of the respective operating units, the register of readiness, each digit of which is connected with the second control the output of the eponymous local stack data packets, the priority chain with a round-Robin prioritization, the first and second inputs which are interconnected with direct and inverse outputs of the bits of the register ready, the first outputs from the first control inputs of the respective local stack data packets, the second output from the second control inputs all local stack data packets, and the third input is connected according to the scheme ORed with the control outputs of the blocks stack memory results, the output bus which is connected to the input tyres blocks local memory commands and blocks local memory functional parameters. In addition, the priority chain with a round-Robin prioritization may contain shift register interconnected with a generator of clock pulses, a pair of series-connected two-input logic elements And, OR, United in a ring, trehochkovye logical elements And p is the number of local stacks of data packets, the first inputs trehshipovyh logic elements And connected with the third input priority circuit with a round-Robin prioritization, second input trehshipovyh logical element with the same first input priority circuit with a round-Robin prioritization and corresponding inputs multiple-input logic element OR the first inputs of two-input logic elements And connected to respective second inputs of the priority chain with a round-Robin prioritization, the second inputs of two-input logic elements And third inputs of the respective trehshipovyh logic elements And outputs of two-input logic elements OR the respective pairs of series-connected two-input logic elements And and OR, the first inputs of two-input logic elements OR the outputs of two-input logic elements And the previous pair of series-connected two-input logic elements And and OR, the second inputs of two-input logic elements OR with the corresponding outputs shift register, and the output multi-input logic element OR interconnected with the second output of the priority circuit with a cyclic assignment of priorities.

When implementing a device for processing information in accordance with the claimed invention, wasnike the technical result - the opportunity to use the device in real-time due to rapid arrivals of data packets generated by operating units in the blocks stack memory results.

Figure 1 shows the structural diagram of the device for processing information, and figure 2 - option priority chain with a round-Robin prioritization.

A device for processing information includes a parallel bus PB 1, is connected with input data IN 2 and blocks of output data OUT 3, blocks stack memory results RS 4, which are connected with blocks local data memory DM 5 and blocks local memory data availability, RM 6, the ring bus RB 7, which are interconnected with operating units PU 8, blocks local memory commands, SEE 9, blocks local memory functional parameters of the FM 10 and the register of employment, BR 11, local stacks of data packets DS 12, the first control outputs 13 which is connected with the control inputs of the respective operational blocks PU 8, the register ready RR 14, each digit of which is connected with the second control the output 15 of the same name local stack data packets DS 12, the priority chain with a round-Robin prioritization PC 16, the first 17 and second 18 inputs which are interconnected with direct and inverse outputs of the bits of the register ready RR 14, the first exit 19 - sparvieri control inputs 20 of the respective local stack data packets DS 12, the second output 21 from the second control inputs 22 all local stack data packets DS 12, and the third input 23 is connected according to the scheme ORed with the control outputs of the blocks stack memory results RS 4.

Priority chain with a round-Robin prioritization PC 16 contains a shift register SR 24, interconnected with a generator of clock pulses PG 25, a pair of series-connected two-input logic elements 26 And 27 connected in a ring, trehochkovye logical elements And 28 on the number of local stack data packets DS 12, the first input 29 trehshipovyh logic elements And 28 are connected with the third input 23 priority chain with a round-Robin prioritization PC 16, the second input 30 trehshipovyh logic elements And 28 with the same first input 17 of the priority chain with a round-Robin prioritization PC 16 and the corresponding inputs multiple-input logic element OR 31, the first 32 inputs of two-input logic elements And 26 connected to respective second inputs of the 18 priority chain with a round-Robin prioritization PC 16, the second input 33 of two-input logic elements And 26 with the third input 34 of the respective trehshipovyh logic elements And 28 and the outputs of two-input logic elements OR 27 of the respective pairs of series-connected dogwho the new logical elements And and OR, the first input 35 of two-input logic elements OR 27 - the outputs of two-input logic elements And 26 of the previous pair of series-connected two-input logic elements And and OR, second input 36 input logic elements OR 27 with the corresponding outputs of shift register 37 SR 24, and the output multi-input logic element OR 31 is interconnected with the second output 21 priority chain with a round-Robin prioritization PC 16.

Consider the operation of the device for processing information, depicted in figure 1, which uses the priority chain with a round-Robin prioritization in accordance with figure 2.

Mode data input device for processing data packets generated in the block of input data IN 2, proceed to the parallel bus PB 1 format:

The block number of the local memoryAddress command packageAddress in the packageValue

Input data packets from the parallel bus PB 1 goes into the blocks stack memory results RS 4, where the "value data" is entered in the corresponding cell block local data memory DM 5. At the same time in the same address section of the block is okaley memory data readiness RM 6 bit is set ready. Setting all the bits ready in a targeted section of the block of local memory data readiness RM 6 initiates the fetch command packet from this address section blocks local data memory DM 5, commands, SEE 9, functional parameters of the FM 10 and transmitting the selected command packet on the ring bus RB 7 devices. When this address section of a block of local memory data readiness RM 6 is set to zero.

The processing of the command packet. Command packet on the ring bus RB 7 reaches operating unit PU 8 digit employment BR 11 which reset. The commit command packet in the input circuit of the operational unit PU 8 removes it from the bus RB 7 and sets the corresponding digit of the register of employment, BR 11, which leads to redirection of the other command packets on the bus RB 7, the remaining operating units PU 8. In the case of employment of all operating units PU 8 command packets circulating on the bus RB 7 to reset one of the bits of the register employment BR 11. Recorded in the input circuit of the operational unit PU 8 command package contains a complete set of data values and functional parameters to be processed, indicating the implemented function codes and addresses command packet receivers result. The operation unit PU 8 after processing is completed forms so the package is in the data many addresses command packet receivers of the it contains, and when the data packets are loaded into the appropriate local stack data packets DS 12, which after the insertion of the first packets of data sets corresponding digit readiness RR 14. Issuance of an operational unit PU 8 all prepared data packet is accompanied by the same reset discharge register employment BR 11.

In accordance with the values of the bits of the register ready RR 14, supplied to the first 17 and second 18 inputs the priority chain with a round-Robin prioritization PC 16, the first outputs of the 19 priority chain with a round-Robin prioritization PC 16 and trehshipovyh logic elements And 28 (figure 2) provide a choice of one of the local stack data packets DS 12, is ready to issue packets of data to the parallel bus PB 1. The sequence of alternating two-input logic elements 26 And logical elements OR 27 solves the problem: the creation of two-input logic elements And 26 of the chain barring selection of other local stack data packets DS 12 and change using a two-input logic elements OR 27 conditions at the circuit of the ban due to the unitary shift operation code of the form 0...0100 carried out in the shift register SR 24 in accordance with the pulses coming from the city is nerator clock pulses PG 25. A logic level zero on the second input 23 of the priority chain with a round-Robin prioritization PC 16 blocks the flow of data packets from all local stack data packets DS 12 to the parallel bus PB 1 if at least one control output blocks stack memory results RS 4 formed by a logic level zero, which corresponds to the complete filling of the block stack memory of the results of the RS 4. If you previously completed the block stack memory results RS 4 is released at least one cell, then the third input 23 priority chain with a round-Robin prioritization PC 16 is formed, the level of logical units, which authorized the issuance of a unitary code sample on the first outputs of the 19 priority chain with a round-Robin prioritization PC 16. The willingness of at least one local stack data packets DS 12 to the grant of a data packet (selected in the unit of the corresponding digit readiness RR 14) leads to the formation of the second output 21 priority chain with a round-Robin prioritization PC 16 level logical units of signal extraction supplied to the second control input 22 of all local stack data packets DS 12. Cyclic change of priority is provided by changing the position of the unit in a unitary code in the shift operations content svigals the th register SR 24. Unit unitary code via a corresponding two-input logic element OR 27 forming the enable signal sampling on the near left Tregubova logical element And 28, causes the level of logical units on the corresponding first output 19 priority chain with a round-Robin prioritization PC 16, if installed in the unit of the corresponding bits of the register ready RR 14 and there is no overflow blocks stack memory results RS 4 (on the second input 23 of the priority chain with a round-Robin prioritization PC 16 - level logical units). Zeros unitary code does not affect the operation of the circuit of the ban.

Priority chain with a round-Robin prioritization PC 16 generates a unitary code sample local stack data packets DS 12 in accordance with the rules: in blocks of stack memory the results of the RS 4 is free cells on the second input 23 of the priority chain with a round-Robin prioritization PC 16 - signal logical units); the highest priority is granted to local stack data packets DS 12, the position of which in the structure of the device corresponds to the position of the unit in a unitary code of the shift register SR 24; selects the priority or the closest to the left of it local stack data packets DS 12 with ready data packets. The data packets are issued on parallel the s bus PB 1 signal extraction coming from the second output 21 priority chain with a round-Robin prioritization PC 16 to the second control input 22 of all local stack data packets DS 12. Full exemption local stack data packets DS 12 accompanied by a reset of the corresponding digit readiness RR 14. Local stacks of data packets DS 12 represent the memory of the FIFO type, so the process of entering data packets from the output buses operating units PU 8 can be aligned in time with the process of extracting data packets from the output stack data packets DS 12 to the parallel bus PB 1 and then in the input circuit of the respective blocks stack memory of the results of the RS 4. Next is similar to the process input data.

The output mode of calculation results. The results of the calculation are formed operational units PU 8 in the form of data packets, the address field of each of which corresponds to one of the block addresses of the data output OUT 3. The data packets in the manner described above come from the output buses operating units PU 8 in the local stacks of data packets DS 12 and then to the parallel bus PB 1. However, they are not recorded not in one of the blocks stack memory results DS 4, and are fixed in the input circuits of blocks of output data OUT 3.

The programming mode of the device for processing information. The programming of the proposed mouth of the STS is carried out before using it in the above mentioned modes. When programming is required for each command packet to the appropriate address section of a block of local memory commands, SEE 9 enter codes address command packet receivers result. In this case, the value of the address of the command packet receiver of the result (value) of the data packet generated in block I IN 2, through the parallel bus PB 1 and the corresponding block stack memory results DS 4 is entered in the address section (field "address command package" and the field "address in the packet") of the specified block of local memory commands, SEE 9 (the "block number local memory").

Configuration mode functional parameters of the device for processing information. The setting of functional parameters is performed after the programming of the claimed device, but before it is functioning as a neural network. The process of entering values of functional parameters similar to the above sequence programming with the only difference that the "value" field of the data packet is placed in the address section of the corresponding block of local memory functional parameters of the FM 10. Perform set-up procedures after implementation of the programming of the device necessarily when solving problems in neural network basis, because the programming process defines the topology neuron the second network, and functional parameters are selected in the process of "learning" has already formed a network and recorded in the local memory functional parameters of the FM 10. If the functional parameters are known in advance (the network is "trained"), the order of programming and configuring devices for information processing can be arbitrary.

Introduction to the structure of the device local stack data packets DS 12 according to the number of operating units PU 8, register ready RR 14 and the priority chain with a round-Robin prioritization PC 16, interconnected with register ready RR 14 and with the local stack data packets DS 12, can solve the problem of increasing the performance of the device for processing information due to operational release operational units PU 8 from the results of processing and buffering in the local stacks of data packets 12, and the alignment in time of the processes of loading data packets in the local stacks of data packets DS 12 and retrieval on parallel bus PB 1 and further in the appropriate blocks stack memory results RS 4 without the use of a relatively slow mechanism of the ring bus RB 8. Cyclic prioritization provides in a given time interval is equal to the probability of service to all local stacks of data packets DS 12 regardless of the order under which the connectivity to the parallel bus devices for information processing.

1. Device for processing data containing parallel bus connected to the input sections and blocks of output data, the input tyres blocks stack memory results, the output bus which is connected to the input tyres blocks local data memory and blocks local memory data set ready, ring bus, which are interconnected with the input bus operating units, the output bus blocks local memory data blocks local memory commands, blocks local memory functional parameters, units of local memory data availability and register of employment, each of the discharge of which is connected to control the output of the relevant operating unit, characterized in that it contains the local stacks of data packets, the input bus which is connected to the output buses of the same name operating units, the output bus is a parallel bus, and the first control outputs - control inputs of the respective operating units, the register of readiness, each digit of which is connected with the second control the output of the eponymous local stack data packets, the priority chain with a round-Robin prioritization, the first and second inputs which are interconnected with direct and inverse outputs of the bits of the register ready, the first outputs from the first control inputs to meet the common local stack data packets, the second output from the second control inputs of all local stack data packets, and the third input is connected according to the scheme ORed with the control outputs of the blocks stack memory results, the output bus which is connected to the input tyres blocks local memory commands and blocks local memory functional parameters.

2. A device for processing information according to claim 1, characterized in that the priority chain with a round-Robin prioritization contains a shift register interconnected with a generator of clock pulses, a pair of series-connected two-input logic elements And, OR, United in a ring, trehochkovye logical elements And the number of local stacks of data packets, the first inputs trehshipovyh logic elements And connected with the third input priority circuit with a round-Robin prioritization, second input trehshipovyh logical element with the same first input priority circuit with a round-Robin prioritization and corresponding inputs multiple-input logic element OR the first inputs of two-input logic elements And connected to respective second inputs of the priority circuit, the second input of two-input logic elements And third inputs of the respective trehshipovyh logic elements And output the AMI two-input logic elements OR the respective pairs of series-connected two-input logic elements And and OR, the first inputs of two-input logic elements OR outputs of two-input logic elements And the previous pair of series-connected two-input logic elements And and OR, the second inputs of two-input logic elements OR with the corresponding outputs shift register, and the output multi-input logic element OR interconnected with the second output of the priority circuit with a round-Robin prioritization.



 

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