Transistor with current limitation and method of its manufacturing

FIELD: electric engineering.

SUBSTANCE: invention is related to power vertical transistors, comprising MOS-structure, produced with application of double diffusion, having source electrodes (emitter) and gate on one surface of substrate, and drain electrode (collector) on opposite surface of substrate. In transistor with current limitation, comprising substrate having the first and second opposite surfaces, DMOS-transistor installed on the first surface of substrate, alternating areas of N-type and P-type of conductivity arranged on the second surface of substrate, cells of DMOS-transistor on the first surface of substrate have a shape of strips, alternating areas of N-type and P-type of conductivity have a shape of strips on the second surface of substrate, moreover, strips on the second surface of substrate are arranged perpendicularly relative to strips on the first surface of substrate. In process of transistor manufacturing they form areas of N-type and P-type of conductivity on the second surface of substrate with a certain ratio of areas.

EFFECT: manufacturing of transistor of increased resistance to short circuit of load circuit with specified current limitation, increased accuracy of reproducibility of specified current limiter, increased yield of good transistors in percentage ratio, reduced prime cost of transistors manufacturing.

7 cl, 1 dwg

 

The invention relates to the field "field effect transistors", in particular to vertical power transistors, containing the MOS structure, produced with the use of double diffusion, with the electrodes of the source (emitter) and shutter on one surface of the substrate, and the drain electrode (collector) - on the opposite surface of the substrate.

Known design effect transistor with insulated gate (THIES), limiting the maximum current, comprising a semiconductor substrate having first and second opposite large surfaces, the first of which is formed a vertical N-channel MOS transistor with the emitter electrodes and the gate, and the second surface of the high impurity concentration P+-type in the semiconductor substrate - electrode collector (patent US 4,641,162 from 03.02.1987 IPC H01L 29/02). The advantage described THIES is the design of the emitter, is divided into several parts in each cell, by allowing a reduction of the perimeter of the emitter of each cell to limit the maximum collector current, which is of great importance when it is used in modes that allow short-term short circuit of loads.

The main disadvantage of the TEESE is the increased degree of integration of the transistor, as in modern miniaturization cell power transistors, which are the camping TEESE, you need the area of the emitter is divided into several parts with additional operations photolithography, which in turn will lead to further miniaturization, the reduction of the yield of the devices and appreciation of the transistor.

Known construction IGBTs with short-circuited collector (patent US 4,841,345 from 20.06.1989, IPC H01L 29/739, US 5,070,377 from 03.12.1991, IPC H01L 29/66), comprising a semiconductor substrate having first and second opposite large surfaces. On the first surface formed of a vertical N-channel drop-transistor with the emitter electrodes and the gate, and the second surface, alternating areas of high impurity concentration P+and N+-type adjacent to the collector electrode.

From the description of these transistors, it follows that the alternating field of R+and N+-type adjacent to the collector electrode, are used to embed the reverse diode in the IGBT, as DMAP transistor, which is of great importance when switching inductive loads and to improve performance IGBTs, in which minority carriers are absorbed much faster thanks to the availability of the second surface regions of N-type, alternating with an injecting hole of the P-regions.

The disadvantage of transistors is no limit to the collector current.

Patent US ,641,162 from 03.02.1987 IPC H01L 29/02 taken as a prototype.

The aim of the invention is the manufacture of the transistor with a given current limit, precision, reproducibility given tomographically, increasing the yield of transistors in percentage terms, the reduction in the cost of manufacture of transistors.

The technical result is achieved by the fact that made the transistor current limitation, containing a substrate having first and second opposite surfaces, drop-transistor located on the first surface of the substrate, multiple alternating between a region of N-type and P-type conductivity located on the second surface of the substrate, characterized in that the cells of DMAP transistor on the first surface of the substrate are in the form of strips, numerous alternating between a region of N-type and P-type conductivity are in the form of stripes on the second surface of the substrate, and the strip on the second surface of the substrate are perpendicular to the stripes on the first surface of the substrate, in accordance with the method of manufacturing a transistor current limitation consisting in the formation of DMAP transistor on the first substrate surface and numerous alternating between the regions of N-type and P-type conductivity on the second surface of the substrate, opposite the first surface of the substrate, characterized those who, for the calculation of the current limitations collector IK maxthat is equal to IP+INform the ratio of the areas of regions of N-type and P-type conductivity on the second surface of the substrate through the mask, photomask in accordance with the equation:

IP/IN=SP/SN×1/(1/y-1),

where IP- the total current injection of holes from P-type regions;

IN- the total current of electrons N-type regions;

SP- the total area of the regions of P-type conductivity on the second surface of the substrate;

SN- the total area of the regions of N-type conductivity on the second surface of the substrate;

y - factor injection P/N junctions on the second surface of the substrate.

The drawing shows a transistor with a current limiting containing semiconductor substrate 3 N-type with the first surface 1 and the second surface 2, which protivorechat each other, drop-transistor 4 to the electrode 5 and source-emitter and gate 6 formed on the first surface 1, numerous region 7 of N-type conductivity adjacent area 8 of P-type conductivity formed on the second surface 2, the contact metal 9 flow-collector deposited on areas 7 and 8.

To limit the maximum collector current-drain transistor at a certain level to protect it from destruction in a sudden excess of the poppy is kalinago current (for example, in case of short circuit of the load circuit) on the response time external circuit protection device is the ratio of the areas of region 7 of N-type and area 8 of P-type conductivity on the second surface is defined by a photomask mask when forming these areas in accordance with the formula:

where IP- the total current injection of holes from P-type regions;

IN- the total current of electrons N-type regions;

SP- the total area of the regions of P-type conductivity on the second surface of the substrate;

SN- the total area of the regions of N-type conductivity on the second surface of the substrate;

y - factor injection P/N junctions on the second surface of the substrate.

In other designs transistors with short-circuit collector current conduction INgrows linearly, and the current injection IP- quadratic depending on the voltage of the drain - source (collector - emitter). After exceeding the P/N junction voltage of ~0.5 At IPcan be much more as INand limit the current operation of the transistor, especially in case of short circuit of loads.

However, if a transistor constructed in accordance with the condition of the formula [1] such that IP<IK max(IK max- maximum collector current that the transistor can withstand the be the destruction of more than 10 microseconds), he will be able without destruction to survive long enough to trigger an external circuit overload protection, that is not less than 10 microseconds.

Let us consider the principle of operation of the transistor current limitation according to the invention. The transistor with short circuit collector with a positive voltage gate - source (gate - emitter)is above the threshold, the drain current (collector) increases linearly with increasing positive voltage drain - source (collector - emitter) from 0 to ~0.5 V, as DMAP transistor. When the voltage of the drain - source (collector - emitter) above 0.5 V drain current (collector) in the transistor, due to the modulation of the conductivity of minority carriers injected from the P+-areas on the second surface, grows according to the square law, as IGBTs, and reaches high values at voltage drain - source (collector - emitter), much smaller than DMAP transistor. The voltage drop in the open state of this transistor is much lower than the equal area of DMAP transistor, and therefore the collector current can reach values considerably higher than the operating current. To limit current, which is especially important when the transistor is in the short circuit mode of the load, the transistor current limitation according to the invention, the area ratio of regions of P-type and N-type is routenote on the second surface are made in accordance with the formula [1], which connects between a ratio of hole and electron currents with the corresponding space regions of N-type and P-type conductivity on the second surface via the ratio of injection y.

The claimed effect transistor can be produced in several ways. In the first variant of the method of fabrication begins with the formation on the second surface of the substrate by the methods of microelectronics (ion doping, photolithography, high temperature processing) numerous regions of N-type conductivity adjacent to the regions of P-type conductivity with the further formation on the first surface of the substrate, DMAP transistor with the source electrodes and the gate.

In the second variant of the method of manufacturing the transistor begins with the formation of DMAP transistor with the source electrodes and the gate on the first surface of the substrate followed by the formation of numerous regions of N-type conductivity adjacent to the regions of P-type conductivity on the second surface of the substrate.

In the third embodiment of the manufacturing method of the transistor begins with the formation of regions of N-type and P-type conductivity on the second surface of the substrate before the last high-temperature processing used in the manufacture of DMAP transistor on the first substrate surface.

In the manufacture of the transistor is used monocrystallic the ski silicon, which is 1.5-2 times cheaper epitaxial used in the manufacture of IGBTs, DMAP transistors.

To improve the reproducibility level of the current limit transistor current limitation according to the invention is mainly used strip topology as drop-cells on the first surface and regions of P-type and N-type conductivity in the second stock (collector) side, and the orientation of the first and second side perpendicular to each other.

1. The transistor current limitation, containing a substrate having first and second opposite surfaces, drop-transistor located on the first surface of the substrate, alternating between a region of N-type and P-type conductivity located on the second surface of the substrate, characterized in that the cells of DMAP transistor on the first surface of the substrate are in the form of strips, alternating between a region of N-type and P-type conductivity are in the form of stripes on the second surface of the substrate, and the strip on the second surface of the substrate are perpendicular to the strips on the first surface of the substrate.

2. A method of manufacturing a transistor current limitation consisting in the formation of DMAP transistor on the first surface of the substrate and alternating between the regions of N-type and P-type conductivity on the second surface is oblozhki opposite the first surface of the substrate, characterized in that for the calculation of the current limitations collector IK maxthat is equal to IP+INform the ratio of the areas of regions of N-type and P-type conductivity on the second surface of the substrate through the mask, photomask in accordance with a ratio
IP/IN=SP/SN×1/(1/γ-1),
where IP- the total current injection of holes from P-type regions;
IN- the total current of electrons N-type regions;
SP- the total area of the regions of P-type conductivity on the second surface of the substrate;
SN- the total area of the regions of N-type conductivity on the second surface of the substrate;
γ is the coefficient of injection P/N junctions on the second surface of the substrate.

3. A method of manufacturing a transistor according to claim 2, characterized in that the first form of the region of N-type and P-type conductivity on the second surface of the substrate, and then forming drop-transistor on the first substrate surface.

4. A method of manufacturing a transistor according to claim 2, characterized in that the first form of drop-transistor on the first surface of the substrate, and then forming region of the N-type and P-type conductivity on the second surface of the substrate.

5. A method of manufacturing a transistor according to claim 2, characterized in that the forming region of the N-type and P-type conductivity on the second surface of the substrate before the last Vysokoe eratures processing, used in the manufacture of DMAP transistor on the first substrate surface.

6. A method of manufacturing a transistor according to claim 2, wherein forming the cells of DMAP transistor on the first surface of the substrate in the form of strips arranged perpendicular relative to alternating between the bands of regions of N-type and P-type conductivity on the second surface of the substrate.

7. A method of manufacturing a transistor according to claim 2, characterized in that the transistor is made of monocrystalline silicon.



 

Same patents:

FIELD: heterostructures of semiconductor devices, primarily those of field-effect transistors.

SUBSTANCE: proposed semiconductor heterostructure of field-effect transistor has AlN single-crystalline substrate, GaN template layer, GaN channel layer, and AlxGa1-xN layer; disposed one on top of other between template and channel layers are intermediate AlyGa1-yN layer and AlzGa1-zN buffer layer, respectively; value of y at template layer boundary is 1 and at buffer layer boundary it equals buffer layer z value; in this case 0.3 ≤ x ≤0.5 and 0.1 ≤ z ≤0.5. Buffer layer in semiconductor heterostructure at channel layer boundary can be doped with Si through depth of 50 to 150 Å.

EFFECT: enhanced conductivity of heterostructure channel layer and, hence, enhanced working currents and power of field-effect transistors.

2 cl, 1 dwg

The invention relates to semiconductor devices and can be used in radio, microwave devices etc

The invention relates to electronic equipment, namely, to field effect transistors on heterostructures with selective doping (FRI GSL)

FIELD: heterostructures of semiconductor devices, primarily those of field-effect transistors.

SUBSTANCE: proposed semiconductor heterostructure of field-effect transistor has AlN single-crystalline substrate, GaN template layer, GaN channel layer, and AlxGa1-xN layer; disposed one on top of other between template and channel layers are intermediate AlyGa1-yN layer and AlzGa1-zN buffer layer, respectively; value of y at template layer boundary is 1 and at buffer layer boundary it equals buffer layer z value; in this case 0.3 ≤ x ≤0.5 and 0.1 ≤ z ≤0.5. Buffer layer in semiconductor heterostructure at channel layer boundary can be doped with Si through depth of 50 to 150 Å.

EFFECT: enhanced conductivity of heterostructure channel layer and, hence, enhanced working currents and power of field-effect transistors.

2 cl, 1 dwg

FIELD: electric engineering.

SUBSTANCE: invention is related to power vertical transistors, comprising MOS-structure, produced with application of double diffusion, having source electrodes (emitter) and gate on one surface of substrate, and drain electrode (collector) on opposite surface of substrate. In transistor with current limitation, comprising substrate having the first and second opposite surfaces, DMOS-transistor installed on the first surface of substrate, alternating areas of N-type and P-type of conductivity arranged on the second surface of substrate, cells of DMOS-transistor on the first surface of substrate have a shape of strips, alternating areas of N-type and P-type of conductivity have a shape of strips on the second surface of substrate, moreover, strips on the second surface of substrate are arranged perpendicularly relative to strips on the first surface of substrate. In process of transistor manufacturing they form areas of N-type and P-type of conductivity on the second surface of substrate with a certain ratio of areas.

EFFECT: manufacturing of transistor of increased resistance to short circuit of load circuit with specified current limitation, increased accuracy of reproducibility of specified current limiter, increased yield of good transistors in percentage ratio, reduced prime cost of transistors manufacturing.

7 cl, 1 dwg

FIELD: electricity.

SUBSTANCE: in vertical field transistor containing the source connection, ohmic contact to the source, source, vertical conducting channels, gate made in the form of metal band, sink, the first and the second dielectric layers located on upper and lower surfaces of metal band and adjacent to side surfaces of vertical conducting channels, and substrate, to lower sink surface there in series applied is layer of ohmic contact, contact layer of ductile metal and damping layer of ductile metal, to lower surface of non-perforated end of metal band there in series applied is the first process layer, the second process layer and support for non-perforated end of metal band; substrate is made from heat-conducting dielectric material; to upper side of substrate there applied are the first and the second contact platforms which are galvanically connected to lower surfaces of damping layer and metal support, and all the transistor elements arranged on dielectric substrate, except the source connection, are enveloped with protective dielectric filling.

EFFECT: invention allows increasing output power of transistor and improving reliability and its life time.

8 cl, 3 dwg

FIELD: electricity.

SUBSTANCE: semiconductor device comprises a thinned substrate of single-crystal silicon of p-type conductivity, oriented according to the plane (111), with a buffer layer from AlN on it, above which there is a heat conducting substrate in the form of a deposited layer of polycrystalline diamond with thickness equal to at least 0.1 mm, on the other side of the substrate there is an epitaxial structure of the semiconducting device on the basis of wide-zone III-nitrides, a source from AlGaN, a gate, a drain from AlGaN, ohmic contacts to the source and drain, a solder in the form of a layer including AuSn, a copper pedestal and a flange. At the same time between the source, gate and drain there is a layer of an insulating polycrystalline diamond.

EFFECT: higher reliability of a semiconducting device and increased service life, makes it possible to simplify manufacturing of a device with high value of heat release from an active part.

3 cl, 7 dwg

FIELD: electricity.

SUBSTANCE: suggested device unites three field effect transistors into a unified vertical structure with channels of n- and p-type conductivity thus forming an electrical junction between them, at that the source of p-type channel is located opposite the source of n-type channel, and the source of p-type channel is located opposite the source of n-type channel. Sources of the channels are interconnected by a conductor and an additional zone with n+-type conductivity where the source of n-type channel is formed, and drains of the channels have separate outputs. The device can be equipped with one gate (three-terminal device - version 1) or two gates (four-terminal device - version 2) located at the other (second) lateral side of the channels. Current in the channels passes in one direction and creates back voltage in the junction thus locking the channels. The device can contain more than one structure, at that gates are common for neighbouring structures.

EFFECT: invention allows reducing dimensions, increasing operational speed, current and output power of the device.

4 cl, 6 dwg

FIELD: electricity.

SUBSTANCE: SHF high-power transistor with multilayer epitaxial structure contains a basic substrate of silicium, a heat-conductive polycrystalline diamond layer, epitaxial structure based on wideband III-nitrides, a buffer layer, a source, a gate, a drain and ohmic contacts. The heat-conductive polycrystalline diamond layer has thickness of 0.1-0.15 mm, and at the epitaxial structure surface between the source, gate and drain there is an auxiliary heat-conductive polycrystalline diamond layer, a barrier layer of hafnium dioxide and an auxiliary barrier layer of aluminium oxide placed in-series. At that the barrier layers of hafnium dioxide and aluminium oxide have total thickness of 1.0-4.0 nm, besides they are placed under the gate, at the epitaxial structure directly, as a layer of solid AlGaN solution with n-conductivity.

EFFECT: increase of heat transfer in the transistor active area and minimisation of current losses.

3 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: SHF high-power transistor contains basic substrate of silicium, a heat-conductive polycrystalline diamond layer, a multilayer epitaxial structure on wideband III-nitrides, a buffer layer, a source, a gate, a drain and ohmic contacts. At that the basic substrate of silicium has thickness less than 10 mcm, the heat-conductive polycrystalline diamond layer has thickness of at least 0.1 mm, and at the surface of the epitaxial structure there is an auxiliary layer of heat-conductive polycrystalline diamond and a barrier layer of hafnium dioxide with thickness of 1.0-4.0 nm, which is placed under the gate, directly at the epitaxial structure made of a layer of solid AlGaN solution with n-conductivity.

EFFECT: increase of SHF-power output, effective removal of heat from the transistor active area and minimisation of current losses.

3 cl, 4 dwg

FIELD: chemistry.

SUBSTANCE: invention relates to a method of producing cyclopropane fullerene derivatives of general formula 2 by heating a non-modified fullerene with tosylhydrazine in the presence of a solvent and a base. The process is carried out with tosylhydrazine of α-keto acetic ester of general formula 1 (R1-C(=N-NH-Ts)COOR (1), where in general formulae 1 and 2, the radical R denotes a linear or branched Cn aliphatic radical, where n ranges from 1 to 50; radical R1 denotes a C6 aromatic radical; Fu is fullerene C60 fullerene C70, or a higher fullerene C>70, or a mixture of fullerenes C60 and C70 (total content of 95.0-99.999% by weight) and higher fullerenes (C>70, content of 0.001-5.0% by weight). The method enables to obtain fullerene derivatives having in their structure an ester group which is directly bonded to the cyclopropane moiety in the fullerene sphere, using readily available α-keto acetic esters.

EFFECT: invention relates to use of cyclopropane fullerene derivatives of general formula 2 as semiconductor materials for electronic semiconductor devices, materials for an organic field-effect transistor and materials for an organic photovoltaic cell.

6 cl, 13 dwg, 3 ex

FIELD: electricity.

SUBSTANCE: invention is related to high-voltage gallium nitride high-electron mobility transistors (GaN HEMT), in particular to GaN HEMT design for high-voltage applications. A high-voltage gallium nitride high-electron mobility transistor is grown at a silicon substrate with coated template structure having thickness of 700-800 nm and consisting of alternate layers of GaN/AlN with thickness of 10 nm at most; between the buffer layer and barrier layers a spacer layer of AlN is introduced with thickness of 1 nm at most; passivation layer is covered by a field plate connected electrically to the gate; distance between the gate and drain and length of the field plate are interrelated quantities, which are selected on the basis of required breakdown voltage.

EFFECT: manufacture of high-voltage gallium nitride high-electron mobility transistor with high performance capabilities at simplification of the process cycle and reduction of material costs for its manufacture.

4 dwg

FIELD: chemistry.

SUBSTANCE: heterostructure modulated-doped field-effect transistor comprises a flange, a pedestal, a heteroepitaxial structure, a buffer layer, a source, a gate, a drain and ohmic contacts. The pedestal has thickness of 30-200 mcm and is made from a heat-conducting layer of CVD polycrystalline diamond with implanted Ni and annealed surface layers on two sides. On top of the pedestal there is a substrate made from monocrystalline silicon with thickness of 10-20 mcm and a buffer layer. On the surface of the heteroepitaxial structure, between the source, the gate and the drain, there are series-arranged additional layers of heat-conducting polycrystalline diamond, a barrier layer of hafnium dioxide and a barrier layer of aluminium oxide. The barrier layers have total thickness of 1.0-4.0 nm. Furthermore, in the gate region, the buffer layers are situated under the gate, directly on the epitaxial structure in the form of a layer of a solid AlGaN solution.

EFFECT: improved heat removal from the pedestal and the active region of the transistor, ensuring minimal current leakage from the gate and achieving the lowest noise factor in the GHz range.

6 cl, 6 dwg

Up!