Generator of system of discrete orthogonal signals

FIELD: physics, computer technology.

SUBSTANCE: invention is related to automatics and computer technology and may be used in devices for spectral analysis and communication for generation of orthogonal signals. Device comprises clock oscillator, counter, cyclic shift registers, multipliers of the first group, four limiters of signals level, multipliers of the second group, element NOT, multiplier.

EFFECT: simplification of generator and elimination of equipment duplication.

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The invention relates to automatic control and computer engineering and can be used in the devices of spectral analysis and communication to generate orthogonal signals.

Known generator system of discrete orthogonal signal containing a clock generator, a counter, m-1 cyclic 2i- bit shift registers (2mthe dimensionality of the system signals Haar formed on the first bit output of the counter and the outputs of the multipliers of the first group,- the number of cyclic shift register), 2m-2 tubes of the first group, 2m-1 pairs of multipliers of the second group, 2m-1 pairs of multipliers of the third group, four level limiter element and NOT the multiplier (see USSR author's certificate No. 1741122, CL G06F 1/02, 1990).

However, the known generator has considerable complexity and hardware redundancy, since it is composed of 2m-1 pairs of multipliers of the third group (the number of multipliers in the third group exactly 2m+1-2).

The closest in technical essence of the present invention is the generator of the system of discrete orthogonal signal containing a clock generator, a counter, m-1 cyclic 2i- bit shift registers (2mthe dimensionality of the system signals Haar formed on the first bit output scetchy the a and the outputs of the multipliers of the first group, - the number of cyclic shift register), 2m-2 tubes of the first group, 2m-1 pairs of multipliers of the second group, 2m-1 multipliers of the third group, four level limiter signal element and NOT the multiplier, and the i-th bit output of the counter (numbering from senior level) connected to the shift input 1-th cyclic shift register, (i+1)-th bit output of the counter is connected with the first inputs (2i-1)th to (2i+1-2)-th multipliers of the first group, the second inputs of which are connected to respective bit outputs of the i-th cylindrical shift register(m+1)-th bit output of the counter is connected to the inputs of the first and second limiters level signals, the outputs of the first and second limiters level signals are connected respectively to the second inputs of the first and second multipliers each pair of tubes of the second group, the first bit output of the counter through the element is NOT connected to the third input of the limiter signal level, m-th bit output of the counter is connected to the input of the fourth limiter level signals, the outputs of the third and fourth terminators level signals connected to the inputs of the multiplier, the output of which is connected with the second inputs of the multipliers of the third group, the first bit output of the counter is connected to the first input of the first multiplier of the third group, o is on the j-th multiplier of the first group connected to the first input of the (j+1)-th multiplier of the third group, the outputs of the multipliers of the third group are connected to first inputs of respective multipliers of the second group, the outputs of which are outputs of the generator (see the patent for the invention №2022333 from 17.09.93, publ. 30.10.94, bull. No. 20).

However, the known generator has considerable complexity and hardware redundancy, as it is composed of 2m-1 multipliers of the third group.

The aim of the invention is the simplification of the generator through the elimination of 2m-m-1 multipliers of the third group.

This objective is achieved in that in the known generator system of discrete orthogonal signal containing a clock generator, a counter, m-1 cyclic 2i-bit shift registers (m+1 - the number of digits of the counter,- the number of cyclic shift register), 2m-2 tubes of the first group, 2m-1 pairs of multipliers of the second group, m multipliers of the third group, four level limiter signal element and NOT the multiplier, and the i-th bit output of the counter (numbering from senior level) connected to the shift input of the i-th cyclic shift register, the second input (2i-1)th to (2i+1-2)-th multipliers of the first group connected to respective bit outputs of the i-g is the cyclic shift register, (m+1)-th bit output of the counter is connected to the inputs of the first and second limiters level signals, the outputs of the first and second limiters level signals are connected respectively to the second inputs of the first and second multipliers each pair of tubes of the second group, the first bit output of the counter through the element is NOT connected to the third input of the limiter signal level, m-th bit output of the counter is connected to the input of the fourth limiter level signals, the outputs of the third and fourth terminators level signals are connected to the inputs of the multiplier, the output of which is connected to the second inputs of the multipliers of the third group, the first bit output of the counter is connected to the first the input of the first multiplier of the third group, the output of the first multiplier of the third group is connected with the first inputs of the first pair of multipliers of the second group, the outputs of the multipliers of the second group are the outputs of the generator, the changes made, namely, that (i+1)-th bit output of the counter is connected to the first input of the (i+1)-th multiplier of the third group, the output of the (i+1)-th multiplier of the third group is connected with the first inputs (2i-1)th to (2i+1-2)-th multipliers of the first group, the output of the j-thmultiplier of the first group is connected with the first inputs (j+1)-th pair of the multipliers of the second group.

Figure 1 presents the structure of the business scheme of the generator system of discrete orthogonal signals, figure 2 - timing diagram illustrating the process of generating signalsandthe proposed generator, figure 3 - view of the signals generated by the proposed generator.

The generator system of discrete orthogonal signals includes a clock generator 1, a counter 2, a cylindrical registers 3 shift multipliers 4 of the first group, the first and second limiters 5.1 and 5.2 level signals, multipliers 6 of the second group, the multipliers 7 of the third group, the item is NOT 8, the third and fourth terminators 9.1 and 9.2 level signals, the multiplier is 10.

The generator works as follows.

In the initial state, the counter 2 is reset to zero, and in the cyclic registers 3 shift codes recorded species 1000...0. Under the action of the clock pulses coming from the output of the generator 1, the outputs of the m high-order bits (m+1)-bit counter 2, a system of signals Rademacher, presents levels of ±1. Signals Rademacher received at the first inputs of respective multipliers 7 of the third group. However, the number of multipliers 7 in the proposed generator is equal to m, that is (2m-m-1) multipliers less than in the prototype (see the patent for the invention №2022333 from 17.09.94, publ. 30.10.94, bull. No. 20), which consists of 2m-1 multipliers 7.

During the period of formation of the signals at the outputs of the generator signal, f is rmoney on the first bit output of counter 2 is supplied to the input of the element 8. Investirovanie signal with its output fed to the input of the third limiter 9.1 level signals. Simultaneously to the input of the fourth limiter 9.2 signal level signal Rademacher m-th bit output of counter 2. The limiter 9 is implemented as a diode so that the output of the third limiter 9.1 appears positive part of the signal from the output element 8, and the output of the fourth limiter 9.2 a negative part of the signal Rademacher, coming from the m-th bit output of counter 2. Because at the first input of the multiplier 10 receives the signal from the output of the third limiter 9.1, and the second input - output signal of the fourth limiter 9.2, then the output of multiplier 10 is formed by a sequence of negative pulses, located on the second half-period of the formation of the signals at the outputs of the generator. This sequence of negative pulses supplied to the second inputs of all of the multipliers 7 of the third group, the first input of which receives the appropriate signals Rademacher. In the result of multiplying the outputs of the multipliers 7 third group signals are formed, the shape of which is different from the waveforms of HC.

The output signal of the first multiplier 7 third group is supplied to the first inputs of the first pair of multipliers 6 the second group of Signals from the outputs of the OST is lnyh multipliers 7 of the third group are received at the first inputs of respective multipliers 4 of the first group, on the second input of which receives signals from the bit outputs of the registers 3 shift. The bit width of the shift register 3 and the number of multipliers 4 in the subgroup is equal to the number of signals in the subset (2iwhere i is the number of subsets), obtained from one signal Rademacher converted to the corresponding multiplier 7. In registers 3 cyclically shifted code like 1000...0, bits of which specify the interval of existence of the signals at the outputs of the multipliers 4. The shift by one digit is invoked on every change of the sign of the signal Rademacher on the shift input of the register 3. The signals from the outputs of the multipliers 4 in the first group are received at the first inputs of respective multipliers 6 of the second group.

The signal HC from the output of the (m+1)-th digit of the counter 2 is supplied to the inputs of the first and second limiters 5.1 and 5.2 level signals. Limiters 5 can be implemented as diodes so that at the output of the limiter 5.1 appears positive part of the signal Rademacher, and the output of the limiter appears 5.2 negative part of the signal Rademacher.

The result of multiplication of the signals received at the first inputs of the multipliers 6 of the second group, with the output signals of the limiters 5 on the outputs of the respective pairs of tubes 6 are formed signals To(k)r(θ)and L(k)r(θ)identical signals generated prot is type (see patent for invention No. 2022333 from 17.09.94, CL G06 1/02).

Figure 2 shows the timing charts illustrating the process of forming the proposed signal generatorand.

The graphs depict a temporary state outputs:

a) a clock generator 1;

b) (m+1)-th digit of the counter 2;

C) a first limiter 5.1 signal level;

g) a second limiter 5.2 signal level;

d) the first digit counter 2;

e) item NO 8;

g) a third limiter 9.1 signal level;

C) m-th digit of the counter 2;

and fourth limiter 9.2 signal level;

th) multiplier 10;

K) the second digit counter 2;

l) multiplier 7.2 third group, at the first input of which receives the output signal of the second digit counter 2, and the second input - output signal from the multiplier 10;

m)multiplier 4.2 first group;

n) corresponding multiplier 6 of the second group, on which a signal is generated;

on the respective multiplier 6 of the second group, on which a signal is generated.

Figure 3 shows the signals generated by the proposed generator. From the drawing it is seen that these signals identical to signals generated by the prototype.

The use of the invention allows to significantly simplify the mouth of austo generator through the elimination of 2 m-m-1 multipliers of the third group.

The generator system of discrete orthogonal signal containing a clock generator, a counter, m-1 cyclic 2i-bit shift registers (m+1 - the number of digits of the counter, i=1,- the number of cyclic shift register), 2m-2 tubes of the first group, 2m-1 pairs of multipliers of the second group, m multipliers of the third group, four level limiter signal element and NOT the multiplier, and the i-th bit output of the counter (numbering from senior level) connected to the shift input of the i-th cyclic shift register, the second input (2i-1)th to (2i+l-2)-th multipliers of the first group connected to respective bit outputs of the i-th cyclic shift register, (m+1)-th bit output of the counter is connected to the inputs of the first and second limiters, signal level, the outputs of the first and second limiters level signals are connected respectively to the second inputs of the first and second multipliers each pair of tubes of the second group, the first bit output of the counter through the element is NOT connected to the third input of the limiter signal level, m-th bit output of the counter is connected to the input of the fourth limiter level signals, the outputs of the third and fourth terminators level signals are connected to the inputs of the multiplier, you are the od of which is connected to the second inputs of the multipliers of the third group, the first bit output of the counter is connected to the first input of the first multiplier of the third group, the output of the first multiplier of the third group is connected with the first inputs of the first pair of multipliers of the second group, the outputs of the multipliers of the second group are the outputs of the generator, characterized in that for purposes of simplification of the generator it introduced changes, namely that (i+1)-th bit output of the counter is connected to the first input of the (i+1)-th multiplier of the third group, the output of the (i+1)-th multiplier of the third group is connected with the first inputs (2i-1)th to (2i+l-2)-th multipliers of the first group, the output of the j-thmultiplier of the first group is connected with the first inputs (j+1)-th pair of the multipliers of the second group.



 

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