Manufacturing method of shf powerful field ldmos transistors

FIELD: physics; semiconductors.

SUBSTANCE: invention concerns electronic semiconductor engineering. Essence of the invention consists in the manufacturing method of SHF powerful field LDMOS-transistors, including forming of a primary sheeting on a face sheet of an initial silicon body with top high-resistance and bottom high-alloy layers of the first type of conductance, opening of windows in a primary sheeting, sub-alloying of the revealed portions of silicon an impurity of the first type of conductance, cultivation of a thick field dielectric material on the sub-alloying silicon sites in windows of a primary sheeting thermal oxidising of silicon, creation in a high-resistance layer of a substrate in intervals between a thick field dielectric material of elementary transistor meshes with through diffused gate-source junctions generated by means of introduction of a dopant impurity of the first type of conductance in a substrate through windows preliminary opened in a sheeting and its subsequent diffused redistribution, forming of connecting busbars and contact islands of a drain and shutter of transistor structure on a thick field dielectric material on a face sheet of a substrate and the general source terminal of transistor structure on its back side, before silicon sub-alloying and cultivation of a thick field dielectric material in windows of a primary sheeting a high-resistance layer of a substrate is underetched on the depth equal 0.48 - 0.56 of thickness of a field dielectric material, and before dopant impurity introduction in the formed source crosspieces of transistor meshes in a high-resistance layer of a substrate in sheeting windows etch a channel with inclined lateral walls and a flat bottom depth of 1.5 - 2.6 microns.

EFFECT: improvement of electric parametres of SHF powerful silicon LDMOS transistors and increase of percentage output of the given products.

5 dwg, 2 tbl

 

The invention relates to electronic semiconductor technology, in particular to methods of creating SHF (superhigh frequency) power silicon field LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors.

A known method of manufacturing a powerful microwave field LDMOS transistors selected as analog (U.S. patent No. 6063678 "Fabrication of lateral RF MOS devices with enhanced RF properties", published, 16.05.2000), including: formation of primary protective coating of oxide and silicon nitride on the front side of the original silicon p-R+the substrate of the first conductivity type; opening Windows in the primary protective coating; ponteginori exposed areas of the silicon impurity of the first conductivity type; growing a thick field dielectric on ponteginori parts of the silicon in the Windows primary protective coating by thermal oxidation of silicon; forming channel, high stokovoj, high-alloyed and low-alloy stock areas in the volume of the high-resistance layer of the substrate and idstorage dielectric and polysilicon gate electrode on the surface between the thick field dielectric; etching through the V-shaped grooves in the high resistance R--layer substrate in stokovyh regions of the transistor cells; a metal coating on the front side of the substrate and forms the of the photolithography electrodes of the drain and source of the transistor cells and simultaneously connecting tyres and pads drain and gate of transistor structure (crystal, chip); forming a common electrode and source of the transistor structure at the rear side of the substrate.

In made in such a way that the devices the source electrodes of unit cells through the V-shaped grooves are closed at the lower alloyed layer of the substrate, and connecting buses and pads drain and gate of transistor structure is placed on a field dielectric bordering on the periphery of the blocks of elementary transistor cells. To reduce stray capacitance drain-source and gate-source transistor structure and reduce the likelihood of breakdown field of the dielectric welding of the external wire leads to contact pads drain and gate, it is desirable that the field dielectric was as thick as possible. However, it is known that during thermal oxidation of silicon, the growth of the oxide film thickness d at the expense of silicon layer thickness of 0,44d, and the rest of the grown silicon dioxide of a thickness of 0,56d rises above the original surface of the silicon substrate. Therefore, even when dSiO2=1,2...1,3 µm silicon dioxide will rise above the surface of the silicon on the dB=0,68...to 0.72 μm and implement in the interval between such local protruding parts SiO2the elements of the UHF LDMOS transistor structures with topological dimensions 0,5...1,0 µm extremely problematic.

the other disadvantage of this method - analog should be attributed to the complexity of the formation of cross-cutting V-shaped grooves in a high-resistance layer of the substrate in stokovyh regions of the transistor cells. Indeed, since the grooves are formed on one of the last stages of a technological route - before applying the metallic coating on the front side of the substrate, to create can only be used "dry" methods of etching silicon, which in industrial production have found very limited application. Along the way there was enough serious problems associated with the removal of residual photoresist from the bottom of the grooves after placement stokovyh metal bridges that close the source electrodes of the transistor cells on the lower alloyed layer of the substrate, performing in the transistor structure as a common electrode of the source.

As a prototype the selected method of manufacturing a microwave power silicon LDMOS transistors described in U.S. patent No. 6707102 B2 ("Semiconductor device including an insulated gate type field effect transistor and method for fabricating the same"published 16.03.2004,), in which the peripheral field insulator around the blocks of cells generated is identical to the method-analogue, and a connecting node between the lower alloyed layer of the substrate and source electrodes of the transistor cells have not placed in the grooves of the metal wire,and end-to-end diffusion jumpers created at the initial stage of the technological route through implementation in a high-resistance layer of the substrate dopant of the same conductivity type, and its subsequent diffusion redistribution.

One of the drawbacks of the prototype, as it was already noted for the method-analogue, is associated with disabilities in a significant thickening (>1.5 μm) peripheral field dielectric of thermal silicon dioxide.

The second drawback of the prototype method due to the need for long-term high-temperature diffusion process of redistribution embedded in the generated ishikawae jumper transistor cells dopant, which is usually accompanied by the appearance of additional structural defects in the silicon substrate and ultimately leads to the deterioration of the electrical parameters of the fabricated devices and reducing the yield of products.

The technical result of the present invention is the improvement of the electrical parameters of microwave power silicon LDMOS field-effect transistors, increasing the percentage of yield of products and, as a result, ensuring appropriate conditions for the establishment of profitable commercial production of devices of this class by modernizing processes in the formation of the peripheral field of dielectric and the WPPT is usinig stokovyh jumpers transistor cells.

The technical result is achieved by the fact that in the known method of manufacturing a microwave powerful LDMOS field-effect transistors, including the formation of the primary protective coating of oxide and silicon nitride on the front side of the original silicon substrate from the upper high resistance and lower alloyed layers of the first conductivity type, opening Windows in the primary protective coating, ponteginori exposed areas of the silicon impurity of the first conductivity type, growing a thick field dielectric on ponteginori parts of the silicon in the Windows primary protective coating by thermal oxidation of the silicon, creating a high resistance layer of the substrate in between the thick field dielectric elementary transistor cells through diffusion stokovye ridges, formed by introducing in the substrate through the previously opened in the protective coating of the window dopant of the first conductivity type and its subsequent diffusion redistribution, the formation of connective tyres and pads drain and gate of transistor structure on a thick field dielectric on the front side of the substrate and a common electrode and source of the transistor structure on its rear side, before ponteginori silicon and growing a thick field dielectric high the intelligent layer of the substrate in the Windows primary protective coating podrublivajut deep equal...0,48 0,56 thickness of the field dielectric, and before the introduction of the dopant in the generated ishikawae jumper transistor cells in the high resistance layer of the substrate in the Windows of the protective coating etched groove with inclined side walls and a flat bottom depth 1.5...to 2.6 microns.

Comparative analysis of the prototype shows that the inventive method is characterized by the presence of a new combination and sequence of technological operations: the leakage of a high-resistance layer of the substrate in the Windows primary protective coating on a certain depth immediately before ponteginori silicon and the subsequent cultivation of the field dielectric of thermal silicon dioxide on ponteginori parts of the silicon in the Windows primary protective coating; etching in a high-resistance layer of the substrate in a pre-opened in the protective coating Windows grooves defined geometric shape and a predetermined depth immediately before the introduction of the dopant in the generated ishikawae diffusion jumper LDMOS transistor cells. Thus, the claimed method meets the criteria of the invention of "novelty."

From table 1 evaluation results according to the position of the top border of the field dielectric in relation to the level of the original surface kresniapolsky (d Bfrom the depths of protravlivanija silicon (hTRand the thickness of the grown field dielectric (d) in the Windows primary protective coating, it follows that the leakage of the silicon in the Windows primary protective coating before growing them in a local layer of thermal silicon dioxide allows you to:

- increase 1.5...3.0 times compared with the prototype and the method is similar to the thickness of thermal silicon dioxide and to place almost all grown field dielectric in the volume of the high-resistance layer of the substrate;

- when specified in the claims the optimal ratio of hTR=(...0,48 0,56)d to provide acceptable for the implementation of powerful microwave field LDMOS transistors flatness (playmost) the front surface of the silicon substrate (grown by the present method of thermal silicon dioxide of thickness d=3,5...4,0 µm will rise above the original surface of the silicon substrate only at 0.28...of 0.32 μm, whereas in the prototype and the way-similar to 1,96...2,24 mm.

Beyond the ratio of hTR=(...0,48 0,56)d is valid, but not advisable, since the depth of protravlivanija silicon hTR<0,48d field dielectric is already significantly rise above the level of the original surface of the silicon substrate, and when hTR>0,56d is going to be below a specified level as well as nagulat the flax. Prescribed in that formula of the invention the sequence of operations for leakage and ponteginori silicon in the Windows primary protective coating is dictated in order to ensure the presence of ponteginori layer of silicon under grown silicon dioxide and thus prevent the formation of leaks in the adjacent field to the dielectric layer of the silicon substrate.

Etching grooves with inclined side walls and a flat bottom in the high-resistance layer of the substrate in the Windows of the protective coating before the introduction of the dopant in the generated ishikawae jumper transistor cells allows you to:

- reduce compared to the prototype for the duration of the diffusion process of the evaporating device is embedded in a high-resistance layer of the substrate dopant and to reduce the number entered in the source substrate additional structural defects;

- be used to form grooves not exclusive "dry" methods of etching silicon, as in the method-analogue, and more are available and well proven in industrial production processes, in particular anisotropic etching of silicon in alkaline solutions (KOH-IPA-H2O and others);

- when the comparable sizes of the Windows, opened in the protective coating, to implement lower compared with the method of the prototype of the m values of the distributed resistance stokovyh diffusion jumpers transistor cells;

to simplify the comparison with the method is analogous to the process of removing residual photoresist from the bottom of the grooves;

- place the alloyed region of the source and the source electrodes of the transistor cells not only on the horizontal surface of the substrate, as in the method prototype, but partly on the inclined walls of the grooves and thereby reducing the size of the elementary transistor cells, and consequently to increase the density of their arrangement in the active region of the transistor structure;

to avoid breakage stokovoj metallization unit cells at the interface, horizontal and slanted surface of the substrate.

Specified in the claims, the range of depths of the etched grooves 1,5...of 2.6 μm is optimal, as é the depths of the grooves substantially increases the duration of the process of diffusion pickup embedded in the substrate dopant, and at greater depths there are difficulties with the removal of residual photoresist from the bottom of the grooves when all subsequent photolithographic processing. The last problem is substantially simplified by forming grooves with more gently sloping side walls and extended flat bottom.

In the present invention the combination and sequence of performance for new process operations provides the opportunity for the awn generate microwave power silicon LDMOS field effect transistors with improved compared with the prototype electrical and operating characteristics, that is, manifests a new technical property. Therefore the claimed method meets the criterion of "inventive step".

This invention also essential, as it provides a significant technical effect, namely:

- the possibility of improving the electrical parameters and extend the functionality of commercially available UHF LDMOS transistors through improvement in the basic process of their production;

- the possibility of increasing the percentage yield and the establishment of profitable industrial output microwave power silicon LDMOS transistors of a new generation and creation on their basis of electronic equipment that meet current and future requirements for power, weight and performance, reliability and durability.

In figures 1, 2, 3, 4, 5 shows the main stages in the manufacture of microwave power silicon LDMOS field effect transistors n-channel according to the invention, where we have introduced the following notation:

1 - the original silicon p-p+the substrate with the lower alloy and the upper high resistance layers;

2 - primary protective coating of oxide and silicon nitride on the front side of the substrate;

2' - opened window in the primary protective coating;

3 - etched grooves in a high-resistance layer of the substrate is Windows primary protective coating;

4, 4' - ponteginori R+-areas of silicon, is formed in the high resistance layer of the substrate in the Windows primary protective coating, respectively, before and after cultivation of the field insulator;

5 - peripheral field dielectric is grown on ponteginori R+-parts of the silicon in the Windows primary protective coating by thermal oxidation of silicon;

6 - secondary protective coating on the front side of the substrate;

7 Windows opened in the protective cover 6 between the peripheral field insulator 5;

7' - grooves with inclined side walls and a flat bottom formed in the high resistance layer of the substrate in the Windows 7 protective coatings;

8, 8' - diffusion ishikawae R+jumper transistor cells formed in the high resistance layer of the substrate in the Windows 7 protective coatings, respectively, after the introduction of the substrate dopant and subsequent diffusion redistribution of embedded impurities;

9 - low-alloy n-area drain of transistor cells;

10, the p - channel region of the transistor cells;

11 - alloyed n+area drain of transistor cells;

12 - alloyed n+area source of transistor cells;

13 - gate dielectric;

14 - the gate electrodes of the transistor cells;

15 - interlayer of dial ctric;

16 - the source electrodes of the transistor cells;

17, the drain electrodes of the transistor cells;

18 - connective stock tires transistor structure;

19 - connecting bolt bus transistor structure;

20 - the common electrode and source of the transistor structure;

21 - induced n-channel.

Example

Using the original silicon p-p+of the substrate oriented in the plane (100), thickness and resistivity of the upper epitaxial R--layer...6,5 6,0 µm and...9,5 9,0 Ohm·cm and a specially designed set of masks were fabricated samples LDMOS transistor structures by the present method with the length of the induced n-channel...0,95 0,85 μm underlying power silicon microwave LDMOS transistor designed for operation in the frequency range up to 1,5...2,0 GTZ-mode class AB when the voltage on the drain UcPete=26...32 Century. Each transistor structure with a size of 1.6 mm×4.2 mm was included in 40 blocks of elementary transistor cells (24 cells in each block) with a total length (width) of the channel W≈8 cm, surrounded on the periphery by a thick layer of thermal silicon dioxide (field dielectric), 11 stock and 10 of the sealing pads, placed on a thick field dielectric in between blocks of transistor cells and the purpose is the R for connection to a transistor structure (crystal, chip) external wire (Al, Au) conclusions. The method is as follows. On the front side of the original silicon p-R+the substrate (1) with the orientation of the crystallographic axes in the plane (100), consisting of the lower alloyed p+-layer with a resistivity ρR+=0,03...0.005 Ohm·cm and the upper epitaxial R--layer with ρR-=5...11 Ohm·cm and a thickness of 4.0...6.5 microns, form the primary protective coating (2) of the layer of silicon dioxide with a thickness of 0.03...0.1 ám and a layer of silicon nitride with a thickness of 0.15...0.25 μm, by photolithography to expose the through-window (2') in the primary protective cover (2), podrublivajut silicon in the Windows (2') of the primary protective coating to a depth of hTR=(...0,48 0,56)d and form thus the grooves (3) in the high-resistance layer of the substrate, poligiros surface silicon layer (4) Bohr - 1 and grown in ponteginori R+-areas of silicon (4, 4') field insulator (5) of thermal silicon dioxide of thickness d - 2. Then remove the primary protective coating (2) from the front surface of the substrate, forming in its place the secondary protective coating (6) of thermal and pyrolytic silicon dioxide thickness of 0.15...of 0.4 μm by photolithography to expose the window (7) protective coating (6) between the peripheral field dielectric (5), anisotropic travlin the eating of silicon in alkaline solution of KOH-IPA(isopropyl alcohol)-H 2O etched in a high-resistance layer of the substrate in the Windows (7) trapezoidal grooves (7') with inclined side walls and a flat bottom depth 1.5...of 2.6 μm, at T=1100°C by diffusion from a solid source boron nitride in the environment of N2+O2within 20...60 minutes generate in the grooves (7') high-alloyed near-surface p++layer (8) - 3, and subsequent diffusion redistribution of embedded impurities at a temperature T=1100...1200°C in an environment of N2+O3form alloyed ishikawae p+jumper transistor cells (8') - 4. Next, implantation in the substrate, ions of phosphorus or arsenic to form low-alloy n--area of flow (9) of transistor cells with a thickness of 0.15...0.5 µm, implantation of boron ions and the subsequent diffusion justify embedded impurities at T=1100°C in an environment of N2+O2within 20...40 minutes to create the p-channel region (10) of transistor cells with a depth of 0.7...1.1 µm, implantation of arsenic ions to form alloyed n+-area runoff (11) and the source (12) of the transistor cells with a thickness of 0.2...0.4 µm, thermal oxidation of silicon is grown gate dielectric (13) of the transistor cells in the thickness of 700...1000 Å on the front side of the substrate, covering the gate dielectric layer magnetron sputtering of molybdenum with a thickness of 0.2...0.3 microns or alloyed layer of polysilicon t is linoy 0,3...0,4 μm and a photolithography method to form from them the gate electrodes (14) of the transistor cells, put on the front side of the substrate interlayer dielectric (15) alloy phosphorus pyrolytic silicon dioxide of a thickness of 0,2...0,5 ám figure 4. Thereafter, by photolithography to expose the contact window in the interlayer dielectric over alloyed n+the areas of the drain and the source, stokovye R+-bridges and gate electrodes of transistor cells is applied on the front side of the substrate, the metallic coating (Al, TiPtAu etc) and photolithography to form from it the source electrodes (16) and drain (17) of the transistor cells and simultaneously connecting buses drain (18) and bolt (19) transistor structure - 5. The common electrode and source of the transistor structure (20) on the rear side of the substrate formed with the landing of the crystal to heat the surface of the body, and the induced n-channel (21) formed by applying the positive potential to the gate electrode of the transistor structure.

Using silicon p-p+the substrate of the same liposomial the same set of masks were also made samples UHF LDMOS transistor according to the method prototype. In this case, the field dielectric of thermal silicon dioxide with a thickness of 1 and 1.5 μm was formed without prior protravlivanija silicon in the Windows primary protective coating, and ishikawae R+c samplesthreshold voltages Uzi longthe leakage currents of the gate IC utafter this fit of transistor structures were mounted in ceramic-metal chassis CT-25 and collected the instruments in addition to the above parameters were measured drain current Iwiththe slope S, the resistance of the drain-source open Rsi OTC, interelectrode capacitance - input With11ANDcommunicating With12output22Iand energy parameters - output power Pothe gain in power Tourand the efficiency of stock chain ηwithat a frequency of f=1000 MHz at a supply voltage according to the article the ku U c Pete=28...30 V mode class AB in the circuit with a common source with pulse width tISM=100 µs, duty cycle θ=10.

Electrical parameters of the devices and the percentage of yield structures on the wafer produced by the present method and the method prototype, shown in table 2. From the presented results we can draw the following conclusions:

1. With increasing thickness of the peripheral field of the dielectric from 1.5 μm to 2.6 μm input With11ANDand output With22Icapacity decreased by 1.3 times, the gain in power Tourand the efficiency of stock chain ηwithincreases respectively in ~1.18 and 1.07 times.

2. With increasing depth in trapezoidal grooves h from 1.5 to 2.8 μm, the drain current Iwithhave made by the present method devices increases 1.2 times the resistance Rsi OTCdecreases in 1.17 times, Poand ηwithincrease of approximately 1.06 times. The most optimal is the depth range of trapezoidal grooves h=1,5...of 2.6 μm, because when h<l,5 beginning to grow Rsi OTCand decreases ηwithand when h>2,6 µm 4...5% reduced the percentage of yield structures on the plate.

3. I made the claimed method of the devices compared to devices made by the method prototype, the drain current Iwithage is no 1.24...1.33 times, the resistance Rsi OTCdecreases in...1,17 1,24 times, the input With11Andand output With22Icapacity reduced...at 1.15 1.48 times and accordingly 1.1...1.43 times the output power Pothe gain in power Tourthe efficiency of stock chain ηwithincrease, respectively, in...1,14 1,2 times, 1,21 1,35...times...1,14 1,17 times and, finally, the percentage of yield structures on the plate increases...1,17 1,32 times.

Technical and economic efficiency of the proposed method in comparison with the prototype consists of:

- the possibility of improving the electrical parameters and increasing the percentage of yield commercially available microwave power silicon LDMOS field-effect transistors through improvement in the basic process of their construction (modernization of technological process of forming a thick peripheral insulator transistor structure and stokovyh diffusion jumpers transistor cells);

- create and organize cost-effective industrial production of microwave power silicon LDMOS field effect transistors of a new generation and design on the basis of their electronic equipment that meet current and future requirements for reliability, power consumption, weight and performance and durability.

Sources inform the tion

1. U.S. patent No. 6063678 “Fabrication of lateral RF MOS devices with enhanced RF properties”, published, 16.05.2000 (similar).

2. U.S. patent No. 6707102 B2 Semiconductor device including an insulated gate type field effect transistor and method for fabricating the same”published 16.03.2004, (prototype).

Table 1
d, µmdB, MKM
hTr=0,46dhTr=0,48 dhTr=0.5 dhTr=0,52 dhTr=0.54 dhTr=0,56 dhTr=0,58 dhTr=0,6 dhTr=0,62 dPrototype (similar)
1,00,10,080,060,040,020-0,02-0,04-0,060,56
1,40,140.1120,0840,056 0,0280-0,028-0,056-0,0840,784
1,70,170,136is 0.1020,0680,0340-0,034-0,068-0,1020,952
2,00,20,160,120,080,040-0,04-0,08-0,121,12
2,50,250,20,150,10,050to-0.05-0,1-0,151,4
3,00,30,240,180,12 0,060-0,06-0,12-0,181,68
3,50,350,280,210,140,070-0,07-0,14-0,211,96
4,00,40,320,240,160,080-0,08-0,16-0,242,24

A method of manufacturing a powerful microwave field LDMOS transistor, comprising forming the initial protective coating of oxide and silicon nitride on the front side of the original silicon substrate from the upper high resistance and lower alloyed layers of the first conductivity type, opening Windows in the primary protective coating, ponteginori exposed areas of the silicon impurity of the first conductivity type, growing a thick field dielectric on under legirovannykh parts of the silicon in the Windows primary protective coating by thermal oxidation of silicon, the creation of a high-resistance layer of the substrate in the gaps between the thick field dielectric elementary transistor cells through diffusion stokovye ridges, formed by introducing into the substrate through the previously opened in the protective coating of the window dopant of the first conductivity type and its subsequent diffusion redistribution, the formation of connective tyres and pads drain and gate of transistor structure on a thick field dielectric on the front side of the substrate and a common electrode and source of the transistor structure on its rear side, characterized in that before ponteginori silicon and growing a thick field dielectric high-resistance layer of the substrate in the Windows primary protective coating podrublivajut to a depth equal to 0.48...0,56 thickness of the field dielectric, and before the introduction of the dopant in the generated ishikawae jumper transistor cells in the high resistance layer of the substrate in the Windows of the protective coating etched groove with inclined side walls and a flat bottom depth 1.5...of 2.6 μm.



 

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5 dwg, 1 tbl

FIELD: physics; semiconductors.

SUBSTANCE: invention concerns electronic semiconductor engineering. Essence of the invention consists in the manufacturing method of SHF powerful field LDMOS-transistors, including forming of a primary sheeting on a face sheet of an initial silicon body with top high-resistance and bottom high-alloy layers of the first type of conductance, opening of windows in a primary sheeting, sub-alloying of the revealed portions of silicon an impurity of the first type of conductance, cultivation of a thick field dielectric material on the sub-alloying silicon sites in windows of a primary sheeting thermal oxidising of silicon, creation in a high-resistance layer of a substrate in intervals between a thick field dielectric material of elementary transistor meshes with through diffused gate-source junctions generated by means of introduction of a dopant impurity of the first type of conductance in a substrate through windows preliminary opened in a sheeting and its subsequent diffused redistribution, forming of connecting busbars and contact islands of a drain and shutter of transistor structure on a thick field dielectric material on a face sheet of a substrate and the general source terminal of transistor structure on its back side, before silicon sub-alloying and cultivation of a thick field dielectric material in windows of a primary sheeting a high-resistance layer of a substrate is underetched on the depth equal 0.48 - 0.56 of thickness of a field dielectric material, and before dopant impurity introduction in the formed source crosspieces of transistor meshes in a high-resistance layer of a substrate in sheeting windows etch a channel with inclined lateral walls and a flat bottom depth of 1.5 - 2.6 microns.

EFFECT: improvement of electric parametres of SHF powerful silicon LDMOS transistors and increase of percentage output of the given products.

5 dwg, 2 tbl

FIELD: physics.

SUBSTANCE: in a field-effect transistor which includes an oxide film as a semiconductor layer, the oxide film has a channel part, a source part and a drain part, and concentration of one of hydrogen or deuterium in the source part and in the drain part exceeds that in the channel part.

EFFECT: invention enables to establish connection between the conducting channel of a transistor and each of sources and drain electrodes, thereby reducing change in parameters of the transistor.

9 cl, 13 dwg, 6 ex

FIELD: electricity.

SUBSTANCE: in manufacturing method of semiconductor device, which involves processes of ion implantation and formation of active areas of instrument on silicon substrate, after formation of active areas there created is hidden p-layer under channel of instrument by alloying of substrate with Be ions with energy of 125-175 keV, dose of (2-5)·1012 cm-2 and with further annealing at 650-750°C during 20-30 minutes and H2 atmosphere.

EFFECT: reducing leakage current values in semiconductor devices, providing processibility, improving parameters, reliability and increasing percentage yield.

FIELD: electricity.

SUBSTANCE: in the method for manufacturing of a semiconductor device including formation of a semiconductor substrate of the first type of conductivity, a gate electrode formed above a subgate dielectric and separated with interlayer and side insulation from a metal source electrode (emitter), a channel area of the second conductivity type and a source area of the first conductivity type, formed by serial ion alloying of admixtures into windows of the specified shape in the gate electrode, and the metal source electrode, a subgate dielectric is developed, as well as a gate electrode and interlayer insulation above the gate electrode in a single photplithographic process by plasma-chemical feeble anisotropic etching with ratio of vertical and horizontal components of etching speed making (3÷5)/1.

EFFECT: reduced resistance in open condition without increasing dimensions of a crystal and improved efficiency without deterioration of other characteristics.

11 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: manufacturing method of SHF LDMOS transistors includes growth of thick field dielectric at surface of high-ohmic epitaxial p- -layer of source silicone p-p+-substrate at periphery of transistor configurations, formation of source p+-junctions and p-wells of transistor cells in epitaxial p- -layer of substrate not covered with field dielectric, growth of gate dielectric and formation of polysilicone electrodes of transistor cells gate in the form of narrow lengthwise teeth of rectangular section with close adjoining tapped contact pads from source side over p-wells, creation of high-alloy n+-areas of sink, source and low-alloy n-area of transistor cells by introduction and further diffusion redistribution of donor dopant using gate electrodes as protective mask, formation of metal electrodes of sinking, source, screens and buses shunting gate electrodes of transistor cells through tapped contact pads at substrate face and common metal source electrode of transistor configuration at backside, the first degree of low-alloy multistage n-area of transistor cell source is formed after formation of source p+-junctions by introduction of donor dopant to epitaxial p--layer of substrate without usage of protective masks, p-wells, sink and source areas of transistor cells are created with use of additional dielectric protective mask identical in configuration and location of lengthwise teeth of polysilicone gate electrode without tapped contact pads adjoining to them, simultaneously with p-wells similar areas are formed at edges of low-alloy n-area of transistor cells sink and gate electrodes with tapped contact pads adjoining to teeth are formed after removal of additional dielectric protective mask and subsequent growth of gate dielectric, at that width of polysilicone gate electrode teeth are selected so that it exceeds length of transistor cell induced channel per overlay error value.

EFFECT: improvement in electric parameters of powerful silicone generating SHF LDMOS transistors, increase of their resistance to ionising radiation exposure and increase of production output in percents.

7 dwg

FIELD: electricity.

SUBSTANCE: transistor based on a semiconductor compound comprises a semiconductor plate, a channel and a contact layers, ohmic contacts of a source and a drain, made on the basis of a thin-film compound of Ge and Cu, and a gate, where thin films of barrier-forming metal, a diffusion barrier and a conductor are installed in layers on a semiconductor plate. The gate conductor material is a thin-film compound of Ge and Cu with thickness of 10-1,000 nm, with mass content of Ge in the range of 20-45%.

EFFECT: higher thermal stability of gate parameters, lower value of reduced contact resistance of ohmic contacts of a source and a drain.

6 cl, 6 dwg, 1 tbl

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