Detection of data for transfer of hierarchically encoded data

FIELD: information technology.

SUBSTANCE: present invention relates to methods of detecting hierarchically encoded data. In one detection scheme, log-likelihood ratio (LLR) is derived for code bits of the first data stream, based on received data symbols. Interference caused by the first data stream is evaluated. LLR is derived for code bits of the second data stream, based on the LLR for code bits of the first data stream and evaluated interference. LLR for code bits of the first data stream is decoded to obtain decoded data from the first data stream. Decoded data are recoded and re-modulated to obtain re-modulated symbols. Interference caused by the first data stream is evaluated based on the re-modulated symbols. LLR for the first data stream can be derived from received symbols in real time without buffering the received symbols. LLR for the second data stream can be derived after decoding the first data stream.

EFFECT: more efficient detection of hierarchically encoded data.

34 cl, 6 dwg

 

The claim to priority under 35 U.S.C. §119

This patent Application claims the benefit of Provisional application No. 60/538271, entitled "Buffer Size Reduction in a Hierarchical Coding System" (reducing the size of the buffer in the system of hierarchical coding), registered on January 21, 2004 and assigned to the assignee of this application, and thus included explicitly in this document by reference.

I. the technical Field to which the invention relates

The present invention relates in General to communications, and more particularly to techniques for performing detection data to transmit hierarchically encoded data in a wireless communications system.

II. Prior art

Hierarchical coding is a method of data transmission, whereby multiple (e.g. two) of the data stream are superimposed (e.g., added) to each other and are transmitted simultaneously. "Coding" in this context refers to channel coding than coding the data in the transmitter. Hierarchical coding may preferably be used, for example, for delivery of services broadcast to users within the designated area of broadcasting. These users may feel different channel conditions and achieve different relations of the signal level of the aggregate level of mutual interference and noise (SNR). Therefore, these users are able to receive data at different data rates. Using hierarchical encoding the broadcast data can be divided into "main stream" and "stream extensions. The main stream is processed and transmitted by way of the conditions that all users in the area of broadcasting could restore the flow. The thread extension is processed and transmitted by way of the conditions for all users with the best channel conditions could restore the stream.

To restore the transmission of hierarchically encoded data, the receiver first detects and restores the main stream in relation to the flow expansion as noise. The receiver then evaluates and mitigates interference caused by the main thread. After that, the receiver detects and restores the flow expansion with suppressed interference from the main thread. For improved performance the main thread and thread extensions usually are restored sequentially, one thread at a time, in the above-described order. To restore each thread usually requires a large amount of processing. Moreover, it can also require a large amount of buffering, depending on the method and speed with which each thread can be discovered and restored. Large amounts of processing and buffering can influence the t system performance and cost.

There is therefore a need in the art in methods for the effective implementation of the detection data to transmit hierarchically encoded data.

The INVENTION

This document describes techniques to perform discovery data to transmit hierarchically encoded data. These techniques can be used for wireless communication systems with both single-carrier and multi-carrier (e.g., OFDM multiplexing (orthogonal frequency division signals)).

In one scheme of the detection data received symbols originally received to transmit hierarchically encoded data using multiple (e.g. two) of data streams, and the logarithmic likelihood ratio (LLR) for code bits of the first data stream (main stream) are derived on the basis of the received symbols. LLR for the first data stream are decoded to obtain decoded data, which are additionally encoded and remodulate to get remodulating symbols for the first data stream. Interference due to the first data stream, are valued on the basis remodulating characters. LLR for code bits of the second data stream (stream extension) then derived based on the LLR for code bits of the first data stream and the estimated location is. LLR for the first data stream may be (1) derived from the received symbols in real-time without buffering the received symbols, and (2) stored in the buffer for decoding. LLR for the second data stream may be (1) displayed after the decoded first data stream and (2) are stored in the same buffer by overwriting the LLR for the first data stream. The received symbols are not used to calculate LLR for the second data stream and therefore they do not need to buffer.

In another detection scheme data LLR for code bits of the first data stream originally derived on the basis of the received symbols. Evaluation of data characters (or unencrypted symbol hard decisions) for the first data stream is then displayed on the basis of either the received symbols, or LLR for the first data stream. Interference due to the first data stream, are estimated based on estimates of data symbols and suppressed in the adopted symbols to produce characters with suppressed noise. LLR for code bits of the second data stream is then derived based on the characters with suppressed noise. LLR for the first and second data streams can be calculated from the received symbols in real-time without buffering the received symbols. LLR for the second data stream may be regulated/adjusted after decoded by the first data stream by (1) detection of errors in the estimates of data symbols on the basis of remodulating symbols for the first data stream, and either (2A) destination LLR for code bits of estimates of data symbols, which is wrong, for cancellation, or (2b) modification LLR for code bits of estimates of data symbols which are the error using correction factors derived remodulating characters and estimates of the data symbols.

Various aspects and embodiments of the invention are described in more detail later.

BRIEF DESCRIPTION of DRAWINGS

Signs and feature of the present invention will become more apparent from the following detailed description, taken together with the drawings in which the same reference position define respectively the same elements throughout the document and where:

Fig. 1 shows the transmitter and receiver in a wireless communications system;

Fig. 2A shows the signal constellation for QPSK;

Fig. 2B shows the signal constellation for hierarchical coding with QPSK as for the main thread and thread extensions;

Fig. 3 shows the processor receive (RX) for the first circuit of the detection data;

Fig. 4 shows the RX processor for the second circuit detection data;

Fig. 5 shows the processor RX for the third circuit detection data; and

Fig. 6 shows the RX processor for the second circuit detection data using the modulation scheme more high is one order for the main thread.

DETAILED DESCRIPTION

The word "model" is used herein to mean "serving as an example, an incident or illustration". Any variant of implementation or the project described in this document as "typical", should not necessarily be construed as preferred or advantageous in comparison with other variants of implementation or projects.

Fig. 1 shows a block diagram of a transmitter 110 and a receiver 150 in a wireless communication system 100. In the transmitter 110, the encoder/modulator a inside the processor 120 transmit (TX) data receives, encodes, punctuates and modulates (i.e. symbolic displays the main data stream (denoted as {db}) and provides the appropriate main character stream (denoted as {sb}). The encoder/modulator 122b similarly receives, encodes, punctuates and modulates the data stream extensions (denoted as {de}) and provides a stream of symbols extensions (denoted as {se}). The data for each thread is typically encoded in packets, with each packet is encoded separately in the transmitter and decoded separately in the receiver. Threads {sb} and {se} characters contain "the data symbols, which are modulation symbols for data.

A multiplexer 130 receives and combines basically the stream and the stream of characters extensions. Inside the combiner 130 multiplier 132A receives and multiplies the base stream {sb} characters on scale factorKband the multiplier 132b receives and multiplies the flow {se} characters of the expansion scale factorKe. Scale factorsKbandKedetermine the amount of transmitter power to use for the main flow and expansion, respectively. A large part of the total powerPtotalthe transmitter is typically allocated by the main thread. The adder 134 receives and sums the scaled data symbols from multiplier 132A with the scaled data symbols from multiplier 132b and provides the combined or composite characters, which can be expressed as:

a.,Equation (1)

wheresbis the symbol data for the main thread,seis a symbol data stream expansion andxis a merged symbol. Scaling and merging are performed on a per-symbol basis.

Block 138 transmitter (TMTR) receives a stream of combined symbols (denoted as {x}) from the multiplexer 130 and the pilot symbols, control symbols, processes combined and the control symbols based on the model of the system and generates one or more modulated si the channels. The pilot symbol is a modulation symbol for pilot signal, which is known in advance as the transmitter and the receiver, and can be used by the receiver for channel estimation and other purposes. The block 138, the transmitter may perform modulation by multiplexing orthogonal frequency division multiplexing (OFDM) for transmission to United and pilot symbols across multiple sub-bands, spatial processing to transmit the combined and pilot symbols from multiple antennas, etc. Modulated(s) signal(s) transmitted through a wireless channel to a receiver 150.

In the receiver 150 unit 160 of the receiver (RCVR) receives one or more signals through a wireless channel, processes adopted(s) signal(s) in the manner complementary to the processing performed by the block 138 transmitter, provides received pilot symbols (denoted as {yp}) 162 block channel estimation, and provides a stream of received symbols (denoted as {y}) processor 170 RX. The received symbols can be expressed as:

,Equation (2)

wherehis the complex gain of the channel for the combined symbolx, nis the noise observed joint symbolx,andyit is an accepted symbol for a unifying symbolx.Noisenincludes noise in the channel and placed and, the noise receiver, etc.

Block 162 channel estimation evaluates the response of the wireless channel based on received pilot symbols and provides assessmentgain channel. For simplicity, the description herein involves the evaluation of the channel without error, that is,.

The processor 170 RX includes detectors 172 and 176, block 174 suppression, decoders 182 and 186 and the encoder/modulator 184. Detector 172 detects the data stream {y} of received symbols for the main thread and provides detected symbols for the main thread (marked as).Each detected symbolis an estimate of the symbolsbdata can be represented, for example, many of the logarithmic relationship likelihood (LLR), as described below. The decoder 182 decodes the detected symbols for the main thread and provides the decoded primary stream (denoted as). The encoder/modulator 184 then re-encodes and remodulated decoded primary stream in the same way as performed by the transmitter 110, and provides nemodulirovannyj the main stream (denoted as), which is an estimate of the main thread {sb} characters. Block 174 hearth is of interference takes nemodulirovannyj main thread, assesses and mitigates interference caused by the main thread, in the stream of received symbols and provides a stream of characters with suppressed interference (denoted as {ye}) detector 176. The detector 176 detects the data in the stream {ye} characters with suppressed interference for flow expansion and provides detected symbols for flow expansion (denoted as). The decoder 186 decodes the detected symbols for flow expansion and provides the decoded stream extension (denoted as).

The controllers 140 and 190 control the operation of the transmitter 110 and receiver 150, respectively. Modules 142 and 192 provide memory storing program codes and data used by controller 140 and 190, respectively.

Upon detection of data performed by the receiver is affected by various factors, such as the modulation scheme used for each data stream, the particular form used to represent the detected symbols, the technique used to perform discovery data, etc. For clarity detection data transmission hierarchically encoded data with quadrature phase modulation (QPSK) for both streams and the use of LLR to represent the detected symbols particularly described below.

Fig. 2A in which it shows the constellation diagram 200 for QPSK, which includes four signal points 210A through 210d on a two-dimensional complex plane. These four signal points are located in the coordinates 1+j1, 1-j1, -1+j1-1-j1 and they are given labels'11', '10', '01' and '00' respectively. For QPSK modulation, each pair of code bits (denoted asb1andb2)displayed in one of four possible signal points, and an integrated value for a mapped signal point is a modulation symbol for a pair of code bits. For example, bitb1can be used for in-phase (I) component, and bitb2can be used for quadrature (Q) component of the modulation symbol. In this case, the modulation symbol for each pair of code bits can be expressed as:s=b1+jb2whereand.

Fig. 2B shows the signal constellation 250 for hierarchical coding with QPSK as for the main thread and thread extensions. The QPSK constellation for the main thread is represented by the four signal points 210A through 210d. The QPSK constellation for flow expansion is superimposed on the QPSK constellation for the main thread and is represented by the four signal points with a on 260d on each signal point 210. Scale factorsKbthe Kedetermine (1) the distance between the signal points 210 of the main flow and the center of the complex plane and (2) the distance between the signal points 260 flow expansion and signal points 210 of the main thread.

Referring again to Fig. 2A, using QPSK symbol modulation for one of only four possible signal points transmitted for each pair of code bits. However, due to noise, interference and distortion in the wireless channel, the received symbol (e.g. symbol 212 in Fig. 2A) may not fall directly into one of the four possible signal points. The detection data is performed to remove the effects of the wireless channel (for example, removal of the complex coefficienththe gain channel) and to determine which of the four possible signal points is transferred by the symbolsdata. Information for each detected symboloften presented in the form of LLR for each of the two components of the code bits ofb1andb2for the detected symbol. Each LLR indicates the plausibility of its code bitsbi,being a one ('1' or +1) or zero ('0' or -1). LLR for the ith code bit of the detected symbolcan be expressed as:

for i=1, 2 for QPSK, Equation (3)

whereb ithereith code bit for the detected symbol;

chances are that bitbithe detected symbolequal to 1;

a.chances are that bitbithe detected symbolequal to -1;

b.LLRiis the LLR of the code bitbi.

LLR is a bipolar value to a large positive value, corresponding to a higher likelihood that the code bit is +1, and a large negative value, corresponding to a higher likelihood that the code bit is set to-1. LLR zero indicates that the code bits are equally probable is +1 or-1. LLR for each code bit is usually quantized to a predetermined number of bits (or L bits, where L > 1), to facilitate storage. The number of bits to use for LLR depends on various factors, for example, the requirements of the decoder SNR of the detected symbols, etc.

Fig. 1 shows a symbolic representation of the detection data to transmit hierarchically encoded data. The detection data may be performed in various ways. Next, we describe three schemes detection data.

Fig. 3 shows the processor a RX for the first circuit of the detection data, in which the main thread and the thread is rasshireniya both are detected based on the received symbols { y}.The processor a RX is the embodiment of processor 170 RX in Fig. 1.

The processor a RX the received symbols {y} initially stored in the buffer 314. Block 320 calculate the LLR of the main thread retrieves the received symbols from the buffer 314 and performs the detection data for each acceptedyto obtain two LLR for the two code bits of the symbolsbthe main thread, which is in this adopted the symbol. Two LLR for the main thread can be expressed as:

,Equation (4)

whereandare the LLR for the two bits of the symbolsbthe main thread in the accepted symboly;

a.his an estimate of the gain channel for a received symboly;

b. "*" means complex conjugate number;

c.Ebis the energy of the symbolsbthe main thread; and

d.N0,bis the power of noise and interference observed by the symbolsbthe main thread.

It is assumed that the symbolsbthe main thread is a complex value. The energy of the symbol main thread isand the energy of the symbol stream extension iswhereE totalis the total energy of the combined symbolx.PowerN0,bnoise and noise includes noiseN0channel and interference from the flow expansion. Block 320 calculate the LLR provides the main stream (denoted as {LLRb}) through the multiplexer 322 (Mux) buffer 324 for storage.

The decoder 182 receives and decodes the LLR of the main stream from the buffer 324 and provides the decoded datafor the main thread. The decoder 182 may implement turbodecoding or decoder Viterbi (Viterbi)if the transmitter were performed respectively turbo or convolutional coding. Turbodecoding performs decoding on the LLR for a number of iterations to obtain more and better estimates of the transmitted data bits. The decoding process usually requires a certain amount of time to complete and may additionally require storage LLR main stream during the decoding process (for example, turbodecoding).

After LLR main stream decoded, the decoded datarecoded and remodelista through the encoder/modulator 184 for receiving remodulating characters.Block 330 interference assessment receives and multiplies remodelirovania charactersto estimate { h} gain channel and provides estimates{ib}interferences caused by the main thread. The adder 332 receives and subtracts the estimate {ib} the interference from the received symbols {y}obtained from the buffer 314, and provides the {ye} with suppressed interference, which can be expressed as:

a.Equation (5)

Nemodulirovannyj symbolequal to the symbolsbthe main thread if the main thread is correctly decoded. Decoded if the main thread correctly, or error, can be determined on the basis of CRC (control cyclic redundant code) or any other circuit detecting the error.

Block 340 calculate LLR stream extension performs the detection of the data symbols {ye} with suppressed interference to obtain two LLR for the two code bits of each characterseflow expansion.Two LLR for flow expansion can be expressed as:

a.,Equation (6)

whereLLRe1andLLRe2are the LLR for the two bits of the symbolseflow expansion deduced on the basis of the symbolyewith suppressed interference;

a.Eeis the energy of the symbolseflow extended the I; and

b.N0,eis the power of noise and interference observed by the symbolseflow expansion.

Block 340 calculate the LLR provides flow expansion (denoted as {LLRe}) through the Mux 322 buffer 324 for storage. Then the decoder 182 decodes the LLR flow expansion to obtain decoded datafor flow expansion.

For the first circuit of the detection data processor a RX you must store the received symbols {y} in the buffer 314 and LLR main stream in the buffer 324, while the main stream is decoded by the decoder 182. The sizes of the buffers 314 and 324 depend on the size of data packets, decoding delays, and possibly other factors. The same buffer 324 may be used to store as LLR main thread, and LLR flow expansion, as these flows are decoded sequentially.

Fig. 4 shows the processor 170b RX for the second circuit detection data, in which the main flow is detected based on the received symbols {y}, and the flow expansion is detected based on the LLRs of the main thread. The processor 170b RX is another option for the processor 170 RX in Fig. 1.

The processor 170b RX block 420 calculate the LLR of the main thread performs the detection data on the received symbols {y} to obtain the LLR {LLRb} the main thread, as Asano in equation (4). Block 420 calculate the LLR provides the main flow through the multiplexer 422 buffer 424 for storage. The decoder 182 receives and decodes the LLR of the main stream from the buffer 424 and provides the decoded datafor the main thread. After LLR main stream decoded by the encoder/modulator 184 recodes and remodulated decoded datato obtain remodulating charactersfor the main thread.

LLR main stream derived from and closely dependent on the received symbols. LLR stream extensions can be thus calculated directly from LLR main thread instead of the accepted characters. LLR flow expansion can be expressed as:

,

,Equation (7)

,

,

where,anddenotes the estimate of the gain on the channel power for the received symboly. The first equality in equation (7) is obtained by substituting equation (5) into equation (6). The number in parentheses in the third equality is intended for LLR main thread. Equation (7) indicates that the LLR stream extensions which can be derived from LLR main thread and remodulating characters.

The processor 170b RX multiplier 426 receives and scales the LLR of the main flow coefficientG1gain and provides the scaled LLR main thread. Block 430 interference assessment receives and multiplies each nemodulirovannyj symbolas per evaluationgain channel power, and the ratioG2gain to obtain estimatesinterferences caused by the main thread. Processing by block 430 interference assessment is different from processing by block 330 interference assessment according to Fig. 3. The adder 432 receives and subtracts the estimateinterference from the scaled LLR main stream and provides LLR stream extensions that are sent through Mux 422 and to the buffer 424 for storage. The decoder 182 then decodes the LLR flow expansion to obtain decoded datafor flow expansion. As shown in equation (7), the received symbols {y} not used to calculate LLR stream extension.

For the second circuit detection data processor 170b RX no need to store the received symbols, and only one buffer 424 may be used for storage as LLR main thread, and LLR flow expansion. This can significantly reduce the requirements for buffering, for whom the receiver.

LLR main thread quantums and stored with sufficient number of bits of the conditions that these LLR provided good performance for decoding the basic stream and the advanced could be used to derive LLR flow expansion. For the second circuit detection data the number of bits to use for LLR main stream affects the accuracy and the range of LLR for both threads. In one particular implementation of turbodecoding LLR quanthouse six bits in the range [-8, 8] with an accuracy of 0.25. Accuracy means the maximum permissible error of quantization. Range and accuracy are usually chosen both on the basis of the performance of the decoding and indirectly related to the signal-to-noise (SQNR). Moreover, the range and accuracy usually do not change based on factors such as the code rate or the effective SNR.

The accuracy of the LLR flow expansion is affected by the ratioG1the gain is used to scale LLR main thread in equation (7). If the powerN0,bnoise and interference observed by the main thread, the predominant noise

N0channel, and no interference from the flow expansion,N0,bapproximately equal toN0and the flow expansion will have a lower SNR than the one used for the main thread, as typically used less power to flux the extensions. In this case, the ratioG1the gain is less than unity, and since the LLR of the main flow scaled byG1on the accuracy of the LLR flow expansion does not impact the accuracy of the LLR of the main thread. However, if the ratioG1the gain is greater than unity, then one or more additional bits of the lower order of lesser importance can be used for LLR main thread.

The range for quantization must be large enough to LLR main thread is not filled or were reduced to very small values, which can degrade performance. Saturation LLR main thread is usually not a serious problem for turbodecoding, but can greatly affect the quality of the LLR stream extensions that are derived from the LLR of the main thread. To determine how many additional bits of high order is necessary in order to prevent saturation of the LLR, the adopted symbolyin equation (4) can be replaced byas follows:

,

,Equation (8)

wherenbrepresents the noise and interference observed by the main thread, which includes interference from stream extension.

If you pass a symbol the main thread, each of the two LLR for the symbolsbwill have an average value ofand standard deviation. SNR for the main thread then is. Assuming "reasonable" variation mean value plus three times the standard deviation for a received symbolythe amplitude of the LLR must be able to accept values up to. This number increases with increasing SNR for the main thread. Thus, the worst case is when the channel noise is zero, and the SNR of the main flow enters the minimum level of noise caused by the interference from the flow expansion. From this point of view, the SNR of the main flow is equal toSNRb=Eb/Eeand the maximum amplitude of LLR to fit equal. It should be noted that this is a safe range, because when onN0,bdominated by interference from a stream expansion, the noise is no longer Gaussian noise, and noise QPSK, which goes beyond the average plus one standard deviation.

The number of bits to use for the LLR of the main stream may be selected based on the ratio of the energy of the symbol of the main flow to the energy of the symbol stream extension. For example,if the capacity of the main thread four times stronger than the power flow extensions (orEb/Ec=4),the LLR of the main thread must be quantized with an amplitude of up to. For a typical implementation of turbodecoding described above, with the range [-8, 8] LLR main thread can be quantized and stored with two additional high order bits, or 8 bits in total. As another example, if the power of the primary stream up to nine times stronger than the power flow extensions (orEb/Ec=9),the LLR of the main thread must be quantized with an amplitude of up toand can be used three additional bits of high order for LLR.

Although LLR main thread may be stored with additional bits for the second circuit detection data, the total memory requirement is still significantly less than that in the first circuit of the detection data, which stores the received symbols, and LLR main thread. This is especially true as the accepted characters are also likely to require a higher bit width when the presence of the flow extension.

Fig. 5 shows the processor s RX for the third circuit detection data, in which the main flow is detected based on the received symbols {y}, and the flow expansion is detected using nakedyoung of modulename. The processor s RX is another option for the processor 170 RX in Fig. 1.

The processor s RX block 520 calculate the LLR of the main thread performs the detection data on the received symbols {y} to obtain the LLR of the main flow, as shown in equation (4). Block 520 calculate the LLR provides the main stream buffer 524 for storage. The decoder 182 receives LLR main flow of buffer through the multiplexer 524 and 526, decodes these LLR and provides the decoded datafor the main thread.

For the third circuit detection LLR data flow extensions are computed from the received symbols {y} similarly, the first detection circuit data. However, the interference caused by the main thread, are estimated based on estimates of unencrypted data characters (instead remodulating characters) for the main thread. LLR flow expansion can thus be calculated simultaneously with LLR main thread instead of having to wait for the completion of decoding the basic stream.

Assessmentunencrypted data characters (or just estimate of the character data) is an estimate of the symbolsbthe basic stream obtained by making tough decisions or endorsed byyor LLR main thread for acceptedy. For example, Silas in Fig. 2A, the evaluation of the symbol data for a received symbol 212 may be a signal point 1+j1, which is the closest signal point to the received symbol 212. Evaluation of the data characters are displayed on the basis of the received symbols without the advantages of an error correction code used for the main thread. Evaluation of the data characters are, thus, more prone to errors than remodelirovania characters that benefit from features error correction code of the main thread. Therefore, FTA evaluationinterference derived from estimates of the data symbols, are less reliable, and LLR flow expansion derived from noncoding characterswith suppressed interference, are also less reliable than those derived by the first circuit of the detection data. The performance of the decoding for stream extension may deteriorate if the LLR for estimates of data symbols, which are erroneous, specified by the values of high reliability (or more weight) in the decoding process.

Various schemes can be used to mitigate the harmful effects of the error character data (or error symbol hard decision) decoding stream extension. Error of the data symbols can be detected through the your comparison of each remodulating symbol with the corresponding estimate of the symbol data and declaring an error, if this pair is not equal.

In the first compensation circuit error LLR flow extensions for the estimates of data symbols, which are erroneous, given the lack of weight in the decoding process. This can be achieved by assigning these LLR for cancellation, which are zero LLR values that indicates an equal likelihood that the code bits are equal to +1 or-1. If the frequency of occurrence of erroneous symbols (SER) is relatively low, the effects of the use of invalidations for LLR corresponding to the error data characters can be small. For example, if the minimum noise level is 6 dB (which corresponds to the main thread, which has four times the power flow extensions), SER is equal to approximately two percent. The deterioration in the performance of the decoding from the announcement of these error symbols with a hard decision as invalidations should not be significant.

In the second compensation circuit error LLR flow expansion, obtained by using estimates of the data symbols, which are erroneous, are adjusted on the basis of remodulating characters after the decoded main thread. LLR flow expansion from equation (7) can be expressed as:

,

,Equation (9)

p> ,

whereandare the original LLR for the two bits of the symbolseflow expansion. Equation (9) indicates that the originalandcan be obtained on the basis of the symbolyand evaluationcharacter data. After the decoded main stream and accessible remodelirovania characters, the originalandcan be adjusted using remodulating charactersto obtain the finalandthat can be decoded to obtain decoded data for flow expansion. If the original LLR are saturated, then the LLR can be assigned to the defeats. The final LLR saved, even if they are saturated.

The processor s RX block 528 hard decisions or LLR main thread (as shown in Fig. 5), or the received symbols (not shown in Fig. 5), and performs a hard decision for deriving estimatescharacter data for the main thread. Hard decision can be made, as is known in the art. For example, each evaluation of the data symbol can latinasnaked signal point, the nearest distance to the adopted symbol. Unlike remodulating character assessment character data can be displayed with minimal delay.

Block 530 interference assessment receives and multiplies evaluationcharacter data on the estimates {h} gain channel and provides FTA evaluationinterferences caused by the main thread, which can be expressed as:.The adder 532 receives and subtracts the estimateinterference from the received symbols {y} and provides noncoding characterswith suppressed interference, which can be expressed as:.Block 540 calculate LLR flow expansion discovers data on unencrypted symbolswith suppressed interference to obtain the original LLR stream extensionsimilar to those shown in equation (6). Block 540 calculate the LLR provides the source of the flow expansion buffer 544 for storage.

After the decoded LLR main stream, the encoder/modulator 184 recodes and remodulated decoded datato obtain remodulating charactersfor the main thread. The detective is p 542 error character takes remodelirovania characters and evaluationcharacter data, detects errors in the estimates of data symbols and provides an indication for each evaluation of data characters, which is found erroneous. The detector 542 error symbols can optionally calculate a correction factorfor each evaluation of the character data, which is wrong, if you are using the second compensation circuit errors. Block 546 regulation LLR accepts and adjusts the initial LLRflow expansion from the buffer 544 and provides the final LLRflow expansion through the multiplexer 526 decoder 182. Block 546 regulation LLR may (1) appoint LLR stream extensions for assessments of character data that is erroneous, for cancellation, to the first circuit of the error compensation or (2) add the correction factorcbto the original LLR stream extension for each evaluation of the character data that is erroneous, for the second compensation errors.

For the third circuit detection data processor s RX no need to store the received symbols, and two buffer 524 and 544 are used to store the LLR of the main thread and LLR flow expansion, respectively.

For clarity, the three schemes detection data described above for QPSK. These schemes detection data can also be used on the I modulation schemes of higher order which are the modulation of a higher order than QPSK. The first and third circuit detection data can be used in the manner described above, with any modulation scheme for the main thread and any modulation scheme for flow expansion. For the third circuit detection data correction factorcan be used for correcting the original LLR in accordance with the modulation scheme used for flow expansion, whenever found estimates of data symbols, which is incorrect.

For the second circuit detection data LLR main thread to contain all the information in the received symbols, and can therefore be used to assess or recover the received symbols. LLR stream extensions can then be calculated from the adopted estimates characters. Evaluating characters from the LLR of the main flow can be performed as described below. For simplicity, the following description assumes that the main thread uses a modulation scheme with display gray with a higher order than QPSK. Displaying gray nearby signal points in the constellation (in the horizontal and vertical directions for a rectangular constellation) have labels that differ only in the location of one bit. Displaying warming reduces the number of errors is udovich bits for the most probable error events, that corresponds to the symbol displayed in the signal point near the correct signal point, and in this case, only one code bit would be wrong. The following description also assumes that the LLR of the main flow are calculated using the approximation with two peaks, which can be expressed as:

,

,Equation (10)

whereLLRiis the LLR forith code bit for a received symboly;

a.si,1is the intended symbol modulation, which is the closest to the adopted symbolyfrom the condition thatith code bit forsi,1has a value of +1; and

b.si,0is the intended symbol modulation, which is the closest to the adopted symbolyfrom the condition thatith code bit forsi,0has a value of-1.

Signal constellation for M-th PSK or M-QAM modulation scheme has M signal points. Each signal point is associative associated with the label of B bits, where B=log2M code bits are displayed in the symbol modulation, which is a complex value for a signal point whose label is equal to the values In the code bits. In logarithmic relations likelihood is calculated for each received symbolyis each LLR, calculated on the basis of a corresponding pair of the alleged characterssi,1andsi,0the modulation.

Equation (10) provides one equation for the received symbolyfor each code bit of the detected symbolsthe modulation. Thus, there are three equations for each received symbol for 8-PSK (B=3), four equations for each received symbol for 16-QAM (B=4), etc. Can be shown that B equations derived from equation (10) for code bits are linear equations. From these equations can be defined in two unknown quantities, namely the real and imaginary parts of the received symboly. However, the difficulty lies in the fact that a different pair of alleged characters

si,1andsi,0modulation is used for each of the B equations for the received symbolyand these estimated modulation symbols is unknown. For 8-PSK and 16-QAM with display gray estimated modulation symbols may be defined, at least for two of the B code bits for each received symbolyusing the procedure described below. Two (independent) linear equations are then available to calculate the two unknown values for the real and imaginary parts of the received symboly.

The values ofsi,1andsi,0 ycan be defined as follows. First of all, equation (10) indicates that the sign of the LLR for each code bit is determined by the estimated symbol modulation, which is the closest toy/h.For example, ifsi,1closer toy/hthansi,0,is less thanandLLRiis a negative value. Conversely, ifsi,0closer toy/hthansi,1thenLLRiwill be a positive value. Reversing this circumstance, the signs of the LLR of the B code bits (hard bit decisions) determine the signal pointsc(hard symbol decision), which is the closest toy/h.For example, ifLLR1=+a, LLR,2=+bandLLR3=-csymbol 8-PSK, wherea, bandcall are positive values, then the closest signal point to this symbol 8-PSK is labeled '001'.

To simplify the notation, the closest signal pointsccan be periobalance using labels with all zeros by performing exclusive OR operation (XOR) on the label of each signal point in the constellation labeled nearest signal point. In this new notation the estimated symbolsi,0for each of the code bits equal to b is Irisa signal point scorsi,0=scfori=1...B. determination Proceduresi,1depends on the signal constellation and described, in particular, for 8-PSK and 16-QAM with display gray below.

For 8-PSK eight signal points in the constellation are evenly spaced from each other by 45° on the unit circle. Closest signal point toy/hdenoted as '000' on the procedure described above. For constellation for 8-PSK the following two closest signal point toy/hare the two neighboring signal points to '000' (i.e. one signal point on the left and the other signal point to the right of '000' along the unit circle). Since the constellation is displayed in gray, the two neighboring signal points differ from '000' in only one bit location. For example, if two neighboring signal point marked as '100' and '010', thensi,1there '100' to the left of the code bits, and '010' for the average code bit. The values ofsi,1andsi,0for two of the three code bits are thus known and can be used along with the LLR for these two code bits and evaluation ofhgain channel to calculate a received symboly.

For 16-QAM 16 signal points are located in a two-dimensional grid, and each signal point has at least one adjacent signal toccontrol real axis and at least one neighboring signal point along the imaginary axis. Since the constellation is displayed in gray, these neighboring signal points are different from the original signal point is not greater than the location of a single bit. The closest signal point toy/hdenoted as '0000' on the procedure described above. If two neighboring signal point nearest signal pointscreferred to as '1000' and '0001', thensi,1is '1000' to the left of the code bits and '0001' to the right of the code bits. Thus, the values ofsi,1andsi,0for two of the four code bits is known and can be used to calculate a received symboly. Use one neighbor horizontally and one neighbor vertically resolves the situation with dependent equations.

Fig. 6 shows the processor 170d RX for the second circuit detection data with the main stream, modulated by using a modulation scheme of a higher order. The processor 170d RX includes most of the blocks of the processor a RX in Fig. 3 (without buffer 314) and additionally includes block 326 evaluation of accepted characters.

Block 320 calculate the LLR of the main thread displays LLR main thread based on the received symbols {y} and provides the LLR of the main flow through the multiplexer 322 buffer 324 for storage. Block 326 evaluation of received symbols takes LLR main stream from the buffer 32 and produces estimates the received symbols based on the LLR, for example, as described above. The adder 332 receives and subtracts the estimate {ib} interference of estimatesthe received symbols and provides the symbolswith suppressed noise. Block 340 calculate LLR stream extension displays LLR flow-based expansion characterswith suppressed interference and provides LLR flow expansion through the multiplexer 322 buffer 324 for storage.

For clarity, the individual blocks of the LLR calculation is shown for the main thread and thread extensions in Fig. 3, 5 and 6. The LLR calculation for the two flows can be performed by a single computing unit LLR, for example, a method of multiplexing time division (TDM). All the calculation for detecting the data can also be performed by digital signal processor (DSP)having one or more blocks of multiplication with accumulation, and one or more arithmetical and logical units (ALU). The flowchart shown in Fig. 3, 4, 5 and 6, can also be used as flow diagrams of a method for discovery processes data.

Detection techniques data, described here, can be used for systems with single-carrier and multi-carrier. Several bearing can be provided by OFDM or any l the Bo other structural elements. OFDM effectively divides the total bandwidth of the system into multiple (N) orthogonal subbands, which are also called tones, subcarriers, the elements of the sampling rate or frequency channels. Using OFDM, each subrange associative links with the corresponding subcarrier, which can be modulated with data.

The combined symbolxcan be transmitted for each sub-band used for data transmission. To N United symbols can be transmitted over N sub-bands in each period of the OFDM symbols. The transmitter performs the OFDM modulation by transforming into the time domain for each group of N combined and pilot symbols {x(k)},which must be passed in one period of the OFDM symbols using N-point inverse fast Fourier transform (IFFT) to obtain a "transformed" symbol that contains N characters pseudonoise sequence. To combat intersymbol interference (ISI)caused by frequency-selective fading, part (Ncpcharacters pseudonoise sequence) of each transformed symbol is usually repeated for the formation of the corresponding OFDM symbol. Each OFDM symbol is transmitted in one period of the OFDM symbols, which is equal to N+Ncpperiods of characters pseudonoise sequence, g is e N cpis the length of cyclic prefix.

The receiver receives the stream of data samples for the received signal and removes the cyclic prefix in each adopted the OFDM symbol to obtain a corresponding received transformed symbol. The receiver then converts each adopted transformed symbol to the frequency domain using an N-point fast Fourier transform(FFT) to obtain the N received symbols {y(k)} for N sub-bands. Each acceptedy(k) is intended for Unitedx(kor pilot symbol sent by subrangek,which is distorted by a factor ofh(k) gain channel and degrades the noisen(kas shown in equation (2). The received symbols can be serialized and processed as described above for the three schemes detection data.

Detection techniques data described in this document can also be used for more than two data streams. Processing (for example, the LLR calculation, estimation symbols, the estimation of interference and so on)that are used to stream the extension can be repeated for each additional data stream.

Methods of data discovery, described in this document, may be implemented by various means. For example, these techniques may be implemented in hardware on which the provisions, software or their combination. For a hardware implementation, the processing units used to perform discovery data, may be implemented in one or several specific integrated circuits (ASIC), digital signal processors (DSPS), digital signal processing (DSPD), programmable logic devices (PLD), programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, other electronic units designed to perform the functions described here, or their combinations.

For software implementation of the methods of detection data may be implemented with modules (e.g., procedures, functions, and so on)that perform the functions described here. Software codes may be stored in the memory module (e.g. module 192 memory according to Fig. 1) and executed by a processor (for example, the controller 190). The memory module may be implemented within the processor or external to the processor, in this case, it can be connected to the communication processor via various means known in the art.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the to present invention. Various modifications to these options for implementation will be completely obvious to experts in the field of technology and the General principles defined in the materials of the present application may be applied to other variants of implementation without deviating from the essence or scope of the invention. Thus, the present invention is not intended to be limited to the variants of the implementation shown in the materials of the present application, and must comply with the widest scope consistent with the principles and the latest features disclosed in the materials of this application.

1. Execution method of detecting data in a wireless communication system based on the hierarchically encoded data, comprising stages, which are:
derive the logarithmic likelihood ratio (LLR) for code bits of the first data stream based on the received data symbols;
estimate interference due to the first data stream;
output LLR for code bits of the second data stream based on the LLR for code bits of the first data stream and the estimated interference, and
decode LLR for code bits of the first data stream to obtain decoded data from the first data stream.

2. The method according to claim 1, further comprising stages, which are:
recode and remodelers the decoded data to obtain remodelers which the R symbols, where interference due to the first data stream, are valued on the basis remodulating characters.

3. The method according to claim 1, in which the LLR for code bits of the first data stream derived from the received symbols in real-time without buffering the received symbols.

4. The method according to claim 1, further comprising stages, which are:
keep LLR for code bits of the first data stream in the buffer; and
keep LLR for code bits of the second data stream in the buffer by overwriting the LLR for code bits of the first data stream.

5. The method according to claim 1, wherein the quadrature phase shift keying (QPSK) is used for both the first and second data streams.

6. The method according to claim 1, in which the modulation scheme with higher order than quadrature phase shift keying (QPSK)is used for encoding the first data stream, the method further comprises a stage on which:
derive estimates of received symbols based on the LLR for code bits of the first data stream, and where the LLR for code bits of the second data stream are displayed on the basis of estimates of the received symbols and the estimated interference, instead of the LLR of the code bits of the first data stream and the estimated interference.

7. The method according to claim 6, in which the stage at which derive estimates of received symbols includes a stage on which
form two equations for each accepted si the ox data based on the LLR for code bits of the symbol data, and where the evaluation of an accepted symbol for a received symbol data derived from these two equations.

8. The method according to claim 1, in which the LLR for code bits of the first and second data streams are output on the basis of approximation with two peaks, instead of the received data symbols and the LLR of the code bit in the first data stream and the estimated interference, respectively.

9. The method according to claim 1, additionally containing a stage, on which:
derive estimates of the gain channel for the wireless channel used for data transmission, and where the LLR for code bits of the first and second data streams and the interference due to the first data stream output by the estimated gain of the channel, instead of the received data symbols and LLR for code bits of the first data stream and the estimated interference, respectively.

10. The method according to claim 1, wherein the first data stream is the main stream and the second data stream is a stream extension to transmit hierarchically encoded data.

11. The method according to claim 1, wherein the wireless communication system uses multiplexing orthogonal frequency division signals (OFDM), and in which the received text data derived from the multiple sub-bands.

12. Device discovery is complete, the data in the wireless communication system based on the hierarchically encoded data, with the holding:
the first computing unit, configured to derive a logarithmic relationship likelihood (LLR) for code bits of the first data stream based on the received data symbols;
the evaluation unit of interference is made with the possibility of estimating interference due to the first data stream;
a second computing unit, configured to derive LLR for code bits of the second data stream based on the LLR for code bits of the first data stream and the estimated interference, and
a decoder configured to decode the LLR for code bits of the first data stream to obtain decoded data of the first data stream.

13. The device according to item 12, further comprising:
the encoder and modulator, made with transcoding capabilities and remodelirovania the decoded data to obtain remodulating symbols of the first data stream, and where the evaluation unit interference configured to estimate interference due to the first data stream based on remodulating characters.

14. The device according to item 12, further comprising:
a buffer configured to store the LLR for code bits of the first data stream and storing the LLR for code bits of the second data stream by rewriting LLR for code bits of the first data stream.

15. The device according to item 12, further comprising:
the evaluation unit is the anal, made with the possibility of deriving estimates of the gain channel of the wireless channel used for data transmission, and where the LLR for code bits of the first and second data streams and the interference due to the first data stream output by the estimated gain of the channel, instead of the received data symbols and LLR for code bits of the first data stream and the estimated interference, respectively.

16. Device discovery is complete, the data in the wireless communication system based on the hierarchically encoded data that contains:
tool for removing logarithmic relationship likelihood (LLR) for code bits of the first data stream based on the received data symbols;
means for estimating interference due to the first data stream;
tool for removing LLR for code bits of the second data stream based on the LLR for code bits of the first data stream and the estimated noise; and
means for decoding the LLR for code bits of the first data stream to obtain decoded data from the first data stream.

17. The device according to item 16, further comprising:
means for transcoding and remodelirovania the decoded data to obtain remodulating symbols corresponding to the first data stream, where the interference due to the first data stream, measured on the OS is ove remodulating characters.

18. The device according to clause 16, where the LLR for code bits of the first data stream derived from the received character data in real-time without buffering the received symbols.

19. The device according to item 16, further comprising:
means for storing the LLR for code bits of the first and second data streams, where the LLR for code bits of the second data stream is stored by overwriting the LLR for code bits of the first data stream.

20. Execution method of detecting data in a wireless communication system based on the hierarchically encoded data, comprising stages, which are:
derive the logarithmic likelihood ratio (LLR) for code bits of the first data stream based on the received data symbols;
derive estimates of the data symbols of the first data stream on the basis of either the received data symbols, or LLR for code bits of the first data stream;
estimate interference due to the first data stream on the basis of estimates of data symbols;
output LLR for code bits of the second data stream based on the received data symbols and the estimated noise; and
decode LLR for code bits of the first data stream to obtain decoded data of the first data stream.

21. The method according to claim 20, in which estimates of the data symbols are output through tough decisions either on the adopted symbols, or LR for the code bits of the first data stream.

22. The method according to claim 20, further comprising stages, which are:
recode and remodelers the decoded data to obtain
remodulating symbols corresponding to the first data stream; and
regulate LLR for code bits of the second data stream on the basis of
remodulating characters and code bits of the estimated data symbols of the first data stream.

23. The method according to item 22, in which the stage at which regulate LLR, includes the steps in which
errors in the estimates of data symbols on the basis of remodulating characters, and
assign LLR for code bits of the estimates of the data symbols are detected erroneous, for cancellation to decode.

24. The method according to item 22, in which the stage at which regulate LLR, includes the steps in which
errors in the estimates of data symbols on the basis of remodulating characters,
derive correction factors for estimates of the data symbols are detected erroneous, and
adjust the LLR for code bits of the estimates of the data symbols are detected erroneous, using correction factors.

25. The method according to claim 20, in which the LLR for code bits of the first and second data streams are derived from the received symbols in real-time without buffering the received symbols.

26. The method according to claim 20, further containing a stage, on which:
Boo is aresult LLR for code bits of the first and second data streams for subsequent decoding.

27. Device discovery is complete, the data in the wireless communication system based on the hierarchically encoded data that contains:
the first computing unit, configured to derive a logarithmic relationship likelihood (LLR) for code bits of the first data stream based on the received data symbols;
block a decision made with the possibility of deriving estimates of the data symbols for the first data stream based on the received data symbols;
the evaluation unit of interference is made with the possibility of estimating interference due to the first data stream on the basis of estimates of data symbols;
a second computing unit, configured to derive LLR for code bits of the second data stream based on the received symbols and the estimated noise; and
a decoder configured to decode the LLR for code bits of the first data stream to obtain decoded data of the first data stream.

28. The device according to item 27, further comprising:
the encoder and modulator, configured to encode and remodelirovania the decoded data to obtain remodulating symbols corresponding to the first data stream; and
block adjustment with adjustable LLR for code bits of the second data stream based on remodulating symbols and codes the x bits of the estimated data symbols of the first data stream.

29. The device according to p, optionally containing:
the bug detector characters made with the possibility of detecting errors in the estimates of data symbols on the basis of remodulating characters, and where the block adjustment with adjustable LLR for code bits of the estimates of the data symbols are detected erroneous for cancellation to decode.

30. The device according to p, optionally containing:
the bug detector characters made with the possibility of detecting errors in the estimates of data symbols on the basis of remodulating characters, and where the power adjustment is made with the possibilities derive correction factors for estimates of the data symbols are detected erroneous, and for correcting LLR for code bits of the estimates of the data symbols are detected erroneous, using correction factors.

31. Device discovery is complete, the data in the wireless communication system based on the hierarchically encoded data that contains:
tool for removing logarithmic relationship likelihood (LLR) for code bits of the first data stream based on the received data symbols;
means for deriving estimates of the data symbols for the first data stream based on the received data symbols;
means for estimating interference due to the first data stream based on estimates of the end-of the s data;
tool for removing LLR for code bits of the second data stream based on the received data symbols and the estimated noise; and
means for decoding the LLR for code bits of the first data stream to obtain decoded data of the first data stream.

32. The device according to p, optionally containing:
means for transcoding and remodelirovania the decoded data to obtain remodulating symbols corresponding to the first data stream; and
means for regulating the LLR for code bits of the second data stream based on remodulating characters and code bits of the estimated data symbols of the first data stream.

33. The device according to p, in which the means for regulating LLR includes
means for detecting errors in the estimates of data symbols on the basis of remodulating characters, and
means for assigning LLR for code bits of the estimates of the data symbols are detected erroneous, for cancellation to decode.

34. The device according to p, in which the means for regulating LLR includes
means for detecting errors in the estimates of data symbols on the basis of remodulating characters,
means to derive correction factors for estimates of the data symbols are detected erroneous, and
means for correcting LLR for code bits of estimates the end-of the s data found erroneous by using correction factors.



 

Same patents:

FIELD: radio engineering; demodulation of sixteen-position quadrature amplitude keyed signals.

SUBSTANCE: newly introduced in prior-art sixteen-position quadrature amplitude keyed (KAM-16) signal demodulator are fifth and sixths counters and phase error correction unit; there units make it possible to execute following new operations with signal: counting of signal points within count interval, their quantity enabling evaluation of phase error due to unwanted lock-on; correction of calculated phase error in phase error correction unit.

EFFECT: enlarged functional capabilities.

2 cl, 5 dwg, 1 tbl

FIELD: signals transmission equipment engineering.

SUBSTANCE: use of given method in systems for transmitting and receiving signals of quadrature amplitude modulation with low bearing frequency synchronization threshold makes it possible to decrease demodulation threshold due to provision of low synchronization threshold by bearing frequency. Result is achieved by adding to pack of M m-level quadrature amplitude modulation symbols of previously given symbols, part of which does not change from pack to pack, and another part is periodically inverted in some of packs. Due to that at receiving side components of quadrature amplitude modulation signals are singled out, appropriate for additional previously given symbols (frequency of which are known). On basis of these components, inversion frequency is determined, which provides for removal of ambiguousness in adjustment of receipt synchronization frequency, thus making it possible to approach Shannon threshold closely.

EFFECT: decreased demodulation threshold.

4 cl, 1 tbl, 9 dwg

FIELD: radio engineering, possible use during coherent demodulation of signals with combined amplitude-phase manipulation.

SUBSTANCE: prototype device includes second memorizing device and logarithm computation block, while outputs of first and second analog-digital converters are connected, respectively, to first and second inputs of second memorizing device, output of which is connected to input of logarithm computation block, output of which is connected to second input of multiplier.

EFFECT: increased resistance of interference due to removal of false clamp point by phase on discriminatory characteristic.

4 dwg

FIELD: radio engineering.

SUBSTANCE: first calculator calculates soft value Λ of third demodulated symbol of 4 demodulated symbols by subtraction of distance 2a between two demodulated symbols of same axis of indication table from level , quadrature component Yk. Second calculator determines soft value Λ of fourth demodulated symbol by calculating using first variable α. Third calculator calculates soft value Λ of first demodulated signal by subtraction of distance 2a from level of common-mode component Xk. Fourth calculator determines soft value Λ of second demodulated symbol by calculating using second variable β.

EFFECT: higher efficiency.

5 cl, 14 dwg, 12 tbl

FIELD: radio communications; digital communication systems.

SUBSTANCE: proposed spectrum-division frequency modulator that incorporates provision for using frequency-modulated signals of high modulation index in communication systems where frequency resources are limited has two multipliers, two phase shifters, smoothing-voltage generator, two amplitude-phase modulators, carrier generator, adder, and frequency shift control unit.

EFFECT: enhanced noise immunity of communication systems.

3 cl, 15 dwg

FIELD: radio engineering.

SUBSTANCE: demodulation device for octic phase-keyed signals receives input signal Rk(Xk, Yk) incorporating k quadrature component Yk and k cophasal component Xk and functions to generate L(sk, 0), L(sk, 1, and L(sk, 2) relaxed-solution values. Computer functions to calculate Zk by subtracting |Yk| level of quadrature signal component Yk from |Xk| level of cophasal signal component Xk. First selector chooses Zk for respective most significant bit of quadrature signal component Yk. Second selector chooses Zk for respective most significant bit of cophasal signal component Xk. Third selector is used to select output signal of second selector or "0" for respective most significant bit in Zk.

EFFECT: facilitated processing required in calculating minimal distance from signal received.

4 cl, 5 dwg

FIELD: communication systems using variable transfer process; optimizing modulation process and code repetition frequency in given hardware environment.

SUBSTANCE: in order to find most effective modulation and code repetition frequency process including code correction according to this criterion, communication system transmitter is provided with code packet coder and certain set of modulators having different modulation orders and modulating sub-packets that function as code words outputted from coder. Selector functions to select one of modulators by comparing product of modulation order by code repetition frequency which is, essentially, relationship between code packet size and number of information modulating characters and by comparing product of modulation order by code repetition frequency with threshold value.

EFFECT: enhanced effectiveness of found process.

29 cl, 6 dwg, 1 tbl

The invention relates to electrical engineering and can be used at the reception signals of the quadrature amplitude-shift keying (QAM)

The invention relates to electrical engineering and can be used in communication systems

FIELD: communication systems using variable transfer process; optimizing modulation process and code repetition frequency in given hardware environment.

SUBSTANCE: in order to find most effective modulation and code repetition frequency process including code correction according to this criterion, communication system transmitter is provided with code packet coder and certain set of modulators having different modulation orders and modulating sub-packets that function as code words outputted from coder. Selector functions to select one of modulators by comparing product of modulation order by code repetition frequency which is, essentially, relationship between code packet size and number of information modulating characters and by comparing product of modulation order by code repetition frequency with threshold value.

EFFECT: enhanced effectiveness of found process.

29 cl, 6 dwg, 1 tbl

FIELD: radio engineering.

SUBSTANCE: demodulation device for octic phase-keyed signals receives input signal Rk(Xk, Yk) incorporating k quadrature component Yk and k cophasal component Xk and functions to generate L(sk, 0), L(sk, 1, and L(sk, 2) relaxed-solution values. Computer functions to calculate Zk by subtracting |Yk| level of quadrature signal component Yk from |Xk| level of cophasal signal component Xk. First selector chooses Zk for respective most significant bit of quadrature signal component Yk. Second selector chooses Zk for respective most significant bit of cophasal signal component Xk. Third selector is used to select output signal of second selector or "0" for respective most significant bit in Zk.

EFFECT: facilitated processing required in calculating minimal distance from signal received.

4 cl, 5 dwg

FIELD: radio communications; digital communication systems.

SUBSTANCE: proposed spectrum-division frequency modulator that incorporates provision for using frequency-modulated signals of high modulation index in communication systems where frequency resources are limited has two multipliers, two phase shifters, smoothing-voltage generator, two amplitude-phase modulators, carrier generator, adder, and frequency shift control unit.

EFFECT: enhanced noise immunity of communication systems.

3 cl, 15 dwg

FIELD: radio engineering.

SUBSTANCE: first calculator calculates soft value Λ of third demodulated symbol of 4 demodulated symbols by subtraction of distance 2a between two demodulated symbols of same axis of indication table from level , quadrature component Yk. Second calculator determines soft value Λ of fourth demodulated symbol by calculating using first variable α. Third calculator calculates soft value Λ of first demodulated signal by subtraction of distance 2a from level of common-mode component Xk. Fourth calculator determines soft value Λ of second demodulated symbol by calculating using second variable β.

EFFECT: higher efficiency.

5 cl, 14 dwg, 12 tbl

FIELD: radio engineering, possible use during coherent demodulation of signals with combined amplitude-phase manipulation.

SUBSTANCE: prototype device includes second memorizing device and logarithm computation block, while outputs of first and second analog-digital converters are connected, respectively, to first and second inputs of second memorizing device, output of which is connected to input of logarithm computation block, output of which is connected to second input of multiplier.

EFFECT: increased resistance of interference due to removal of false clamp point by phase on discriminatory characteristic.

4 dwg

FIELD: signals transmission equipment engineering.

SUBSTANCE: use of given method in systems for transmitting and receiving signals of quadrature amplitude modulation with low bearing frequency synchronization threshold makes it possible to decrease demodulation threshold due to provision of low synchronization threshold by bearing frequency. Result is achieved by adding to pack of M m-level quadrature amplitude modulation symbols of previously given symbols, part of which does not change from pack to pack, and another part is periodically inverted in some of packs. Due to that at receiving side components of quadrature amplitude modulation signals are singled out, appropriate for additional previously given symbols (frequency of which are known). On basis of these components, inversion frequency is determined, which provides for removal of ambiguousness in adjustment of receipt synchronization frequency, thus making it possible to approach Shannon threshold closely.

EFFECT: decreased demodulation threshold.

4 cl, 1 tbl, 9 dwg

FIELD: radio engineering; demodulation of sixteen-position quadrature amplitude keyed signals.

SUBSTANCE: newly introduced in prior-art sixteen-position quadrature amplitude keyed (KAM-16) signal demodulator are fifth and sixths counters and phase error correction unit; there units make it possible to execute following new operations with signal: counting of signal points within count interval, their quantity enabling evaluation of phase error due to unwanted lock-on; correction of calculated phase error in phase error correction unit.

EFFECT: enlarged functional capabilities.

2 cl, 5 dwg, 1 tbl

FIELD: information technology.

SUBSTANCE: present invention relates to methods of detecting hierarchically encoded data. In one detection scheme, log-likelihood ratio (LLR) is derived for code bits of the first data stream, based on received data symbols. Interference caused by the first data stream is evaluated. LLR is derived for code bits of the second data stream, based on the LLR for code bits of the first data stream and evaluated interference. LLR for code bits of the first data stream is decoded to obtain decoded data from the first data stream. Decoded data are recoded and re-modulated to obtain re-modulated symbols. Interference caused by the first data stream is evaluated based on the re-modulated symbols. LLR for the first data stream can be derived from received symbols in real time without buffering the received symbols. LLR for the second data stream can be derived after decoding the first data stream.

EFFECT: more efficient detection of hierarchically encoded data.

34 cl, 6 dwg

FIELD: physics.

SUBSTANCE: method of relaxed solution for demodulating a received signal α+iβ with quadrature amplitude modulation (QAM) involves deriving several values of a conditional probability vector, where each is a relaxed solution value which corresponds to the position of a stiff solution bit, using a function which includes an operation for conditional definition from the quadrature phase component and inphase component of the received signal. The method of solving for the conditional probability vector for demodulation of the first half of the complete number of bits is identical to the solution method for demodulating the remaining half of bits, and is determined by replacing the value of the quadrature phase component and the value of the inphase component with each other.

EFFECT: more accurate processing a received signal.

29 cl, 15 dwg

FIELD: information technologies.

SUBSTANCE: method is realised using the following facilities, where a DVB-T modulator comprises serially joined units, an interface, a randomiser, a Reed-Solomon encoder, a convolution interleaver, a convolution coder, a bit interleaver, a symbol interleaver, a QAM shaper, a calculator of reverse quick Fourier transform (RQFT calculator), a digital to analogue converter (DAC), a high-frequency unit (HF unit) and a shaper of pilot signals at the inlet of the QAM shaper, and also the following units are additionally introduced: a unit of packets breakdown, receiving information from the interface and sending it to the randomiser and a control unit, a register receiving signals from the randomiser and sending a signal to the Reed-Solomon coder and the convolution interleaver, the control unit receiving information from the unit of packets breakdown, and outlets are connected to all modulator units.

EFFECT: reduced requirements to a computing device due to optimisation of processes of synchronising operation of all units in whole, using less efficient computing devices.

1 dwg

Up!