Compatibility of single-wire and three-wire buses

FIELD: physics, communication.

SUBSTANCE: invention is related to the field of communication realisation between master and slave devices with application of bus interface. According to one aspect, outlet or outlets of three-wire interface are selected in the first mode, and outlet of one or several single-wire interfaces is selected in the second mode. According to the other aspect, converter addresses single-wire bus and generates signals in compliance with three-wire interface. According to another aspect, completion signal is inserted into single-wire interface signal, which facilitates conversion of this signal and connection to three-wire interface. According to the next aspect, in response to detected initial symbol strobe signal and/or clock signal are generated. According to another aspect, strobe signal and/or clock signal are deactivated in response to detected completion symbol.

EFFECT: provision of compatibility between existing serial bus interfaces and single-wire bus interface.

32 cl, 35 dwg, 5 tbl

 

The technical field to which the invention relates

The present invention relates generally to integrated circuits and, in particular, refers to the communication between leaders and subordinates components using a single-wire bus interface.

Prior art

At the present time for communication of various types, such as voice and data, is widely used wireless communication system. Examples of wireless networks include data transmission system based on mobile communication. Among these examples include the following: (1) the "TIA/EIA-95-B compatibility between the mobile station and the base station for dual-mode wideband cellular communication system with spread spectrum" (standard IS-95), (2) the standard offered by a consortium of the Project partnership in the field of communication systems of the 3rd generation (3GPP) and embodied in a set of documents that includes documents on 3G TS 25.211, 3G TS 25.212, 3G TS 25.213, and 3G TS 25.214 (the W-CDMA), (3) the standard offered by a consortium of the Project 2 partnership in the field of communication systems of the 3rd generation" (3GPP2) and embodied in a Standard physical layer TR-45.5 for systems with spread spectrum CDMA2000", (the Standard IS-2000) and (4) high-speed data transfer (HDR), which is compatible with the TIA/EIA/IS-856 (Standard IS-856)

The wireless device typically includes many components. For example, a processor for processing the demodulated signals can interact with one or more radio frequency (RF) or other components. A processor for processing the demodulated signals can create and take unmodulated signals, often in digital form. To provide functions such as analog-to-digital conversion, digital to analog conversion, filtering, amplification, conversion frequency conversion with decreasing frequency, and many others can be used one or more integrated circuits (IC). The master device (such as a processor for processing the demodulated signals) in one or more slave devices can be written in a variety of settings and commands. A master device may need to receive (read) parameters, and other data from one or more auxiliary components (such as radio frequency integrated circuits). Such configuration of the leading devices and slave devices can also be used in devices that are not related to the field of communications.

In the prior art uses the Protocol of the serial bus interface (SBI)in which to implement the communication between the master device and od is them or more downstream devices used three signals (i.e., 3-wire interface). Although the SBI Protocol allows multiple slave devices share the same interface, some components are very sensitive to the work of other components in the shared interface. So some interfaces SBI used with one master device and one slave device in order to avoid these mutual interference. The introduction of the above interfaces may require that the master had three additional pin output (pin) (or contact pads) on each additional interface. This can further complicate the system and/or its cost because of the increased size of the crystal, the total number of pins, etc. Therefore, it is desirable to reduce the number of pins required to interface between the master device and a slave device.

Current technology offers a number of projects for leading devices and slave devices that support the SBI interface. It is desirable that the new interface could provide connectivity with existing components SBI for improved compatibility and allow new devices (leading or subordinate) to operate in phase with each other and with existing components. It is also desirable to provide a means by which to modify existing designs to communicate the interface with a reduced number of pins with a minimum of development to accelerate market entry for new products and speed up mass production of the new interface.

Thus, in the art there is a need for a single-wire bus interface for communication between the master device and one or more slave devices. In addition, there is a need in the leading devices, slave devices and converters that can interact with existing interfaces serial bus, for example, interfaces that are adapted to the SBI Protocol.

The invention

Open options here are designed to meet the needs of compatibility between the existing serial bus interfaces and a single-wire bus interface. According to one aspect of the output or outputs of the three-wire interface selects the first mode, and to output one or more single-wire interfaces choose the second mode. According to another aspect, the inverter takes the signal single-wire bus and generates signals corresponding three-wire interface. According to another aspect of the signal single-wire interface insert the termination character, contributing to the transformation of the specified signal and connection with a three-wire interface. According to the next aspect in response to a detected initial symbol is formed by the gate signal and/or clock signals is. According to another aspect, in response to the detected termination character deactivated the gate signal and/or deactivates the clock signal.

List of figures

Figure 1 is a General block diagram of a wireless communication system capable of supporting multiple users;

figure 2 - part of the famous mobile station 106;

figure 3 - the three modes forwarding for the interface SBI;

figure 4 - type of access mode fast forward (FTM);

figure 5 - type of access mode of mass transfer (BTM);

6 - the access type in the forwarding mode with interrupt (ITM);

Fig.7 is a well - known configuration SBI;

Fig - variant containing a combination of SBI interface and a single-wire serial bus interface (SSBI);

Fig.9 - format forward SSBI;

figure 10 - timing diagram illustrating an exemplary variant of the circuit of the signal transmission SSBI;

11 is an exemplary host device to support SSBI;

Fig - example of a master device configured to support the interface SSBI or SBI;

Fig - approximate slave device to support interface (SSBI;

Fig - approximate slave device to support interfaces SSBI and SBI containing a subordinate unit of SBI and the Converter sub-unit SSBI;

Fig - example of a slave device on Fig configured to communicate tolochenaz interface SSBI;

Fig - approximate slave only for SSBI containing a subordinate unit of SBI and the Converter sub-unit SSBI;

Fig is a timing chart illustrating write SSBI and the signals from the master device SSBI;

Fig is a timing diagram illustrating read SSBI and the signals from the master device SSBI;

Fig - the relationship between the clock pulses of the master and slave devices;

Fig-22 - details approximate logic circuits suitable for use in an exemplary host device SSBI;

Fig - rough version SSBI slave;

Fig is a timing chart illustrating write SSBI and signals SSBI slave;

Fig is a timing diagram illustrating read SSBI and signals SSBI slave;

Fig is an exemplary circuit suitable for use in an exemplary bus interface slave SSBI;

Fig is an exemplary logic circuit suitable for use as a block of registers slave;

Fig - waveforms showing the approximate end of the package, including the termination character;

Fig-31 is an exemplary circuit suitable for use in an exemplary host device SSBI, modified to support FTM mode;

Fig - part of the Converter sub-unit SSBI;

IG - waveforms illustrating the beginning of the forward FTM;

Fig - waveforms illustrating the forward end FTM; and

Fig - part of the additional schema for the example Converter SSBI slave.

Detailed description of the invention

Further, in the context of a digital wireless data transmission the essence of one or more described here approximate variants. Although the use of the invention in this context is primary, the other environments or configurations may include other variants of the invention. In the General case, various system described here can be formed using a processor running software, integrated circuits or discrete logic. These instructions, commands, information, signals, symbols, and chips that are widely referenced in this application, mainly represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or their combination. In addition, the blocks shown in each flowchart may represent hardware or steps of the method.

Figure 1 presents a diagram of a system 100 for wireless communication, which can be designed to support one or more standards and/or the projects CDMA (for example, the W-CDMA standard IS-95, cdma2000, specification HDR system 1xEV-DV). In an alternative embodiment, the system 100 may optionally support any wireless standard or project, other than the CDMA system.

For simplicity, it is shown that the system 100 includes three base stations 104 that are connected to two mobile stations 106. The base station along with its coverage area is often called the "hundredth". In systems IS-95, cdma2000 or 1xEV-DV honeycomb may, for example, include one or more sectors. In the specification, W-CDMA hundredth call each sector of the base station and the coverage of this sector. Used herein, the term "base station" can be used interchangeably with the terms "access point" or "node". The term "mobile station" may be used as interchangeable with the terms "user equipment (UE), subscriber unit, subscriber station," "access terminal, remote terminal or other relevant terms, well-known specialists in this field of technology. The term "mobile station" refers to applications for fixed wireless.

The word "exemplary" is used herein to mean "serving as an example, option, or illustration". Any described here is a variant of the invention, the "approximate" NeoMaster is but should be construed as preferred or have advantages compared with other options.

Depending on the implementation of the CDMA system, each mobile station 106 may, at any given time to communicate with one (or possibly several) base station in a straight line, and can also communicate with one or more base stations through a return line connection depending on whether the mobile station in the soft-switching condition. The term "straight" line (i.e., downward communication refers to transmission from the base station to the mobile station, and the term "reverse link (i.e., upward communication refers to the transmission from the mobile station to the base station.

Figure 2 shows a part of the famous mobile station 106. Illustration, described in detail below, can also be used in other wireless communications devices, such as base station 104, and any other device or devices that require communication between the master and slave devices. In this example, the processor 220 for processing the demodulated signal is used in conjunction with one or more auxiliary integrated circuits (IC), as well as other components that are not shown. The processor 220 for processing the demodulated signals enables processing of communication signals to be transmitted and received in corresponding the one or more systems or communication standards, examples of which are described in detail above. Typical processor 220 for processing the demodulated signals performs digital processing incoming and outgoing signals and can perform the processing of other types, including the execution of various applications. A processor for processing the demodulated signals may contain various components, including one or more microprocessors, digital signal processors, memory, and other circuits General purpose or special schemes of various types. A processor for processing the demodulated signals may include various components for receiving and transmitting signals according to one or more specifications or communication standards, such as coders, premarital, modulators, decoders, reverse premarital, demodulators, search blocks and various other components, examples of which are well known in the art. A processor for processing the demodulated signals may include digital circuitry, analog circuitry, or a combination of both.

Auxiliary integrated circuit IC connected to the processor 220 for processing the demodulated signals, designated as RFIC with 230V on 230N. Exemplary auxiliary circuit IC includes a radio frequency (RF) circuit IC that can perform various functions, for example, a function in which elitely, filters, mixers, oscillators, digital to analog (D/A) converters, analog-to-digital (A/D) converters, and other Components necessary for communication according to the standard, can be part of many RFIC circuits 230. Any RFIC circuit 230 may include components that can be shared by many communication systems. Circuit RFIC shown for illustration only. To the processor 220 for processing the demodulated signals can be connected auxiliary integrated circuit (IC) of any type.

In this example, the RFIC circuit 230 carry out reception and/or transmission via the antenna 210, which may be installed in communication with one or more base stations 104. Antenna 210 may include multiple antennas, as is well known to specialists in this field of technology.

The SBI Protocol

For transmission of various parameters and commands was developed 3-wire interface. This 3-wire interface is a serial bus interface (SBI). 3-wire interface includes a line clock (SBCK), start-stop line (SBST) and the data line (SBDT). The SBI interface is described in detail below. The SBI interface defines a master device and one or more slave devices. In this example, the processor 220 for processing the demodulated signals serves as a presenter at the trojstva, and one or more circuits RFIC 230 serve as slave devices. The SBI interface is not limited to the above and master and slave devices can be of any type. In the following detailed exemplary embodiments, the processor 220 for processing the demodulated signals is interchangeable with the master device 220, and the RFIC circuit 230 is interchangeable with the slave device 230. The processor 220 for processing the demodulated signals may also communicate with various circuits RFIC 230 on various allocated additional lines, either analog or digital (not shown).

Note that, as shown in figure 2, multiple slave devices can share the same three connections master device (SBCK, SBST and SBDT). Between the RFIC circuits 230 and a processor for processing the demodulated signals can be used in various other connections that are not shown in figure 2. The mobile station 106 may also include various other components for use in communication or an application. These details are not shown in order not to obscure the subject of discussion.

The SBI interface defines three types of forwarding behaviors, which formats are shown in figure 3. Fast forward (FTM) provides multiple accesses to any subject which the device including reading and writing. Each access sequence identifies the address to which or from which must be made for the access.

The mode of mass transfer (BTM) provides a set of consecutive accesses to the same slave device. Accesses when sending BTM can be a read or write, but not both. Address for mass shipment must be sent only once. Many reads or records may appear sequentially from the start address.

Forwarding mode with interrupt (ITM) is used to send a single byte coded information. The ID of the slave device (SID) specifies one of the two slave devices to receive the message. 5-bit field of the message provides 32 possible messages. After the message is transmitted bits pause.

Figure 4-6 shows the timing diagram for the FTM, BTM and ITM, respectively. Each access SBI is as follows. The transaction is initiated by transferring the line SBST at a low level. Transactions are completed/finished by transferring the line SBST at a high level. There is at least one clock pulse between transactions (high level SBST and SBDT). All changes in the status line SBDT appear to the rear of the front SBCK (usually installed and derivate parameters set in accordance with the back-to-back SBCK). The first bit of data is recorded on the second trailing edge, after line SBST switched to the low level. First transmitted most significant bit data (MSB), and in the end the least significant bit (LSB). (Recall that the mode ITM one bit identifies one of the two slaves, and then followed by the message). Needresponse slaves are waiting for the start bit of the next transaction. During a single transaction in FTM mode data can be read and written. For each transmitted byte is allocated one or more bits pause. As a master device and the slave device releases the data bus at the time of passing of bits (P) pause in order to avoid conflicts on the bus.

The first two bits indicate the type of access: 01 to FTM mode, 10 mode BTM and 00 mode ITM. The ID of the slave device consists of 6 bits, while the address field and data are 8 bits each. Bits (B) a pause is inserted after every 8 bits to empower the slave device to return data without initiating a conflict situation in the tires. The first bit of the address field indicates whether the access is a read (1) or write (0). For FTM and BTM to the same slave device can be accomplished a lot on what Stepov, moreover, for each access to the register is not required, the job ID of the slave device. The FTM mode is the usual way to perform accesses to the registers. Mode BTM intended for configuration permissions larger group of consecutive addresses. Is specified, only the first register address of the packet. Mode ITM field ID of the slave device is replaced by a 1-bit field SID to set the slave device to be accessed. Instead of the fields of the register and sets the 5-bit field of the message.

In practice it turns out that in some cases, radio frequency (RF) circuit of IC 230 susceptible to mutual interference in the shared bus. To avoid these interferences are additional bus to isolate traffic on the same bus from one or more sensing devices 230. A sample configuration is shown in Fig.7. 7, the processor 220 for processing the demodulated signals communicates with circuits RFIC 230V-230J on a separate 3-wire bus SBI allocated to each device. In this example, the shared bus SBI connected to additional circuits RFIC 230K and 230N. Although adding tires can solve the problem of mutual interference, this leads to an increase in the number of pins required for the processor 220 for processing the demodulated signals, and the number of leading controllers. For example, the processor 20 for processing the demodulated signals can be used with 3 or 4 ports SBI, that will require 9 or 12 pins, respectively. This scheme can be complicated by the need of keying in the service signals to divide the current between ports of different external circuits 230.

The Protocol SSBI

To reduce mutual interference, which is necessary for sensitive circuits 230, while reducing the total number of pins, a new single-wire bus interface, which is described in detail below and is called a single-wire serial bus interface (SSBI). On Fig shows an exemplary mobile station 106 that is used in conjunction with an independent single (SSBI) bus connecting each circuit RFIC 230V-230J processor 220 for processing the demodulated signals. 3-wire bus SBI can also be used in combination with tires SSBI, if necessary. This, as shown in Fig, is achieved through a shared 3-wire bus connecting circuit RFIC 230N-230K and the processor 220 for processing the demodulated signals. Using a single-wire interface allows to reduce the total number of pins, to increase the number of ports, or to achieve both. Increasing the number of ports can prevent the complication of the technical solutions mentioned above which may occur when two or more devices, you must divide is between a single bus interface. Note that in the exemplary embodiments, described in detail below, the interface SSBI for clarity disclosed in relation to the pins and/or contact pads. The Protocol SSBI also applies to the connections between the crystals (i.e., connections between contact areas, without pins), as well as the connections between the chips (i.e., to interconnect connections where there are no pads or pins). Specialists in the art will easily be able to adapt the disclosed here principles to apply to this and other options.

Alternatives may include any number of single-ended buses, as well as any number of 3-wire buses. In various embodiments, examples of which are described in detail below, the pins can be configured for use with either 1-wire or 3-wire bus interface.

A sample Protocol SSBI, which is disclosed in detail here, has the following characteristics. Required total number of pins is reduced compared to the SBI interface. Bandwidth can be comparable or higher than in the SBI interface. Address increases to support additional registers, which provides support for more complex slave devices. In this example, the number of addressable registers is equal to 256.

To reduce the number of the TBA pin interface (SSBI does not contain a line clock (SBCK) and start-stop line (SBST). One line in the Protocol SSBI is called here SSBI_DATA. Instead of line clock pulses addressed in this interface, use the local clock pulses as in the master and in the slave device. The local clock pulses in the host device and all slave devices do not have to be identical. This Protocol takes into account the shifts in phase and frequency, as described in more detail below. Pets certain frequency error, and the magnitude of this error depends on the specific option. The Protocol SSBI is independent of phase relative to the clock pulses of the master and slave devices. The local clock pulses can be generated using local oscillators; they can also be obtained from other sources of clock pulses, or use various other ways to generate clock pulses, known in this technical field.

Interface SSBI

Instead of start-stop line in the data stream is inserted into the initial bits and determines the idle state (IDLE). The receiving device (i.e., slave) can control the data line (SSBI_DATA), selecting pre-defined values IDLE, and then start a transaction when it detects the start symbol. Upon completion of the transaction, the data line may be returned to the IDLE state than severe the fast shipment.

The Protocol SSBI can be developed with time diagrams and waveforms selected in such a way as to facilitate the interaction between the 1-wire and 3-wire interfaces. As will become clear, this allows you to switch from Protocol 3-wire SBI interface to the 1-wire Protocol interface (SSBI. For example, the host device may be equipped with logic to create a format SBI and format SSBI to facilitate communications with subordinate devices of earlier generations, as well as more modern slaves, as they are created. Similarly, the existing slave device may be equipped with a logic conversion, so you can accept formats SBI or SSBI, providing compatibility with leading devices of earlier generations, and new leading device. The slave can be equipped with 3 pins for 3-wire mode, and one of these pins is allocated for line SSBI_DATA when working in SSBI mode. The mode can be selected by setting predetermined values to unused pins when you want SSBI mode. In addition, you can quickly upgrade ogesterone slave device by adding to the existing core logic circuit is converted into the adowanie, so that the signals SSBI_DATA one wire can be converted into existing signal 3-wire SBI interface to communicate with the existing kernel. The specified logical mapping, described in detail below, may be added to the slave device with minimal impact on existing functionality that allows a safe use of your new device. Thus, on the market in the transition from a three-wire devices to a single device can be received benefits, consisting in reducing mutual interference by separating the control lines and by reducing the total number of pins in the master and/or slave devices. Various exemplary embodiments that are described in detail below.

Table 1 shows the interface signals SSBI. Interface SSBI consists of a single pin on each device, designated as SSBI_DATA. Line SBST is excluded, because the beginning and end of the shipment shall be indicated in the data stream. Line SBCK is excluded, as there is a common clock pulses for both the host and slave devices. It is assumed that there are heartbeats available for both the host and slave devices that are designated as SSBI_CLK. You can use any common clock pulses. Between the clock and the heartbeats of master and slave devices do not need the relationship phase. In one embodiment, to simplify routing two of the clock pulse can be obtained from the same source. In the General case, both the clock pulses must have the same frequency, although some frequency error can be corrected. Experts in the art in light of the disclosed approach here will easily be able to assess the magnitude of the error in frequency, valid for any given option. These clock pulses are required whenever necessary to communicate via the interface SSBI.

Table 1
Description modified port of the host device SSBI
The signalDescription
SSBI_DATALine SSBI_DATA; bidirectional; connects the master device (i.e., the processor 220 for processing the demodulated signals to the slave device (i.e., RFIC 230)
SSBI_CLKThe local clock pulses; is generated for each master and slave device for 1-wire mode

In an exemplary embodiment, the master device 220 includes a contact pad for signal SSBI_DATA with the following the features. Pad is bidirectional. It supports the excitation levels 2 mA in the low excitation and 5 mA in the high excitation (this corresponds to the settings used to approximate pads SBI). Exemplary contact pad contains a selectable element that reduces the signal level to the minimum, and then choose the element that supports the signal level. In the field of the present invention can be used in a variety of other pads. In alternative embodiments, such as, for example, interblock connections in a single chip, the pads can be replaced with alternative components, such as devices with three States, multiplexers and the like, well known to specialists in this field of technology.

In the example Protocol SSBI supports only one mode and supports only one access to the register on one shipment. This can be interpreted as a simplification of FTM mode without having to specify a mode or ID of the slave device. Because the bus is expected to only one slave (although addressing schemes can be used, if necessary, two or more devices, as described below), the bits of the ID of the slave device is no longer needed. As a result, when each access will require very little additional service the service signals compared to SBI teams. Lot 3-wire interface SBI provide mechanisms to eliminate unnecessary service signals in order to increase throughput and reduce latency. A single format SSBI provides similar advantages.

Figure 9 shows the format of the forwarding Protocol (SSBI. The frame may be a frame 920 read or frame 910 records. The first bit specifies read or write. Access to read is specified by the value '1'and write access value '0'. This assignment is not arbitrary; it actually prevents a situation where the slave unintentional considers that there are read operations, if the leader block SSBI unintentionally will return to its original state in the middle of the access. The address field is 8 bit full, and since the writing/reading is indicated separately, all 256 addresses will now be available for register read and register write. In an exemplary embodiment, the address space in the interface SSBI increased compared to the SBI interface. In alternative embodiments, it is possible to use the address space of any size.

Parameterization data fields is done in various ways, described below, and the parameter value can be in the range of, for example, from 1 to 16. This is parameter is identified below as SSBI_DATA_WD. For both address fields and data is displayed first bit is the MSB. For the record, as a master device continuously excites the bus, bits (P) are not required. For reads bits are used pause. To perform additional readings or records in the bus is initiated by a new team. Thus, the slave device always know what to expect 17 characters for recording and 19 characters to read (when SSBI_DATA_WD=8).

Although it is anticipated that there will be maintained a single slave device on one port SSBI, can be arranged to support the two slaves, forcing each of them to respond to a different set of register addresses SSBI. For example, one slave can respond to addresses from 0 to 127, while the second slave device will respond to addresses 128 to 255. However, using this approach it is possible to encounter problems loading on Board and with the usual problems of mutual interference, as described above in connection with the SBI Protocol.

Figure 10 presents a timing diagram illustrating an exemplary variant of the circuit of the signal transmission SSBI. In this example, the data line (SSBI_DATA) is low when the status indication of the vacancy. When you want to send data is the start bit, in this example, the high voltage ("1"). Initial bidispersed for centering the sample points of the receiver to sample the incoming data stream. After the start bit is the data flow. Because the command format is strictly defined, the receiver can accurately determine from the data how many bits will be sent. Thus, the receiver knows when it will be completed shipment, and can re-enter the idle state to wait for the next start bit. As the start bit and data bits are each of a length equal in this example, two clock cycles, therefore, the character of the period has a length of two clock cycle. Data bits are transmitted with a high or low level depending on whether 1 or 0 is sent. Alternatively, each bit can have a length of one clock cycle. However, in this case the receiver may have difficulty with the detection center of the symbol, because the accuracy will be only half of the clock cycle. Thus, the receiver cannot guarantee that the sample character will take place during the transition from one symbol to another. When the length of characters is two clock cycles (or more), the receiver can guarantee that he will take the character somewhere between 0.5 and 1.5 cycle in the symbol, therefore, at least at a distance of 0.5 clock cycle from any of the transitions. In alternative embodiments, the number of clock cycles per symbol may vary.

The clock pulses in the receiver optional is entrusted to align the data. Thus, depicted in figure 10 pulses SLAVE CLOCK can be shifted left or right relative to the signal SSBI_DATA. In this example, the receiver starts the sample from the first trailing edge of the clock pulse after coming SSBI_DATA high level. Sample points indicated by vertical dashed lines. Each subsequent character is taken every two clock period from this point until the end of the access. After a bit of IDLE can be transferred to another primary character.

This Protocol SSBI robust frequency. Permissible value specified error may vary depending on the selected technical solutions for the use of any particular option. When using an external clock pulses and direction to one or more of the connected component of this interface has been successfully working in the presence of variable asymmetry of clock pulses between the various components. In an alternative embodiment, one or more connected components (that is, the host device and/or any subordinate device) can generate their own heartbeats within the developed requirements for the error in frequency.

Shipping time for any access does not depend on the data. Time value of shipment are the same as for an approximate 3-wire bus interface (SBI. For R slichnih types of bits can be selected any voltage levels, as it is obvious to experts in the given field of technology. In this example, as described above, the start symbol is chosen equal to “1” (or high voltage) for centering the gate pulse sampling. The idle state is set to "0" (or "earth"). This simplifies the interface, if you use detachable from the power circuit. For example, RF chips (or other slave devices) can connect and disconnect from power supply to save energy. Setting the state of unemployment is equal to the level ground simplifies this condition.

In the General case, the master device initiates the line SSBI_DATA. The master device sets the bus in a third state only when the slave device initiates the data read. In all other cases, the master device initiates a bus. As a master device and slave device driving the data bus at different time intervals in order to avoid conflicts in the data line, the current excitation device bus (driver) releases the bus during one symbol period (in this example, two cycles before the next device is allowed excitation of the tire. This time interval is known as a bit of a pause. Figure 9 bits pause is indicated as “P”. For a bit of pause value in the data line can support the frame element contact pads, supporting the signal level, if available. It is assumed that the slave device will respond by providing data for reading and using temporal correlation, similar to those used by a master device, so the characters read are meant to appear about on those time intervals where they are expected by the master device.

In order to understand how switching from one device to the excitation bus to another, consider the following case. After the master device, sending bits LSB of the address field access for reading, passed bit of a pause, to provide the master device time to release the bus. The slave responds to arouse D7-D0, then release the data line to another bit of pause. Then the host device may again take control of the bus for transmission of the next character. Conflict is avoided, because the slave knows the timing of operation of the host device with an accuracy of up to half of the clock pulse on the basis of the initial bits. As a bit of a pause takes two clock cycle, may receive at least 1.5 cycle or a maximum of 2.5 cycle, depending on the relative phases of the clock pulses of the master and slave devices. Since the delay of the bus and stood at what is below 1.5 cycle, the conflict will not occur.

3-wire interface SBI has a signal SSBI, which is given to the state corresponding to the logical state "true"or activated) at the time of shipment and is found in the state corresponding to a logical state of "false"or deactivated)when the host device has confirmed the execution. This facilitates a rapid transition of the slave device in the idle state at any time. A master device can ensure the removal of the signal SSBI, and depending on, already a slave device in an idle state or is in the middle of shipment, the master device must determine that the transfer no longer occurs, and switch to the idle state. When using the 1-wire interface SBI does not exist signals by which this can be done explicitly. Consider two cases: the first case is during a power reset and the second during normal operation. During power on, the host device may consider the time interval required for installation of various devices in the initial state, and ignore the action SSBI until the end of the installation. During normal operation, while the master device and slave devices operate synchronously, so that podkin the installed devices only respond to the master device and the block SSBI master never forced are in their original condition at the time of shipment SSBI, no problem.

If you need to install the master SSBI to its original state at some arbitrary time, for any reason, then it is likely that the SSBI bus may be in a state corresponding to the middle of reading, and so the slave device will initiate a data bus SSBI. If the host device is forced translates to an idle state, it will also initiate a data bus, and therefore may experience a conflict situation. When the slave does not excite the bus in response to the access to read, the host device converts the idle state, will not cause a conflict situation, the slave will either remain in the idle state, or it will end the current write access, and then go into the idle state. (In this example, since the 1-wire formats are such that writing and reading have a length of 17 and 19 of symbol periods for data width of 8 bits, almost 19 symbol periods later, then it is guaranteed that the slave device is in the idle state). To resolve the question of when the slave can initiate a bus, a master device may refrain from active excitation line SSBI_DATA until it is determined that the period of potential conflict with what the situation is over. In an exemplary embodiment, the master device transfers the line SSBI_DATA in "the third state" and includes an element that reduces the signal level to a minimum in the contact area. To indicate that the reduction of the signal level to the minimum you can block, can be used to reset the control register. Alternatively, to re-enable active control of the bus master device with blocking reducing the signal level to the minimum, if required, can be used for write access.

Convert SBI Protocol in the Protocol SSBI and back

We have described above the two protocols, SBI and SSBI, which can be maintained using a 3-wire or 1-wire interfaces (you may need some conversion functions). Many devices today in operation, capable of using SBI 3-wire interface. Exemplary embodiments, various examples of which are described here, may include a master device 220 and one or more slave devices 230, which communicate over a single-wire interface, using SSBI. Exemplary host device 220 to support SSBI shown at 11, and the corresponding slave device 230 shown in Fig. It is possible that the host device 220 will require the tsya to support both Protocol SBI, and the Protocol SSBI or 1-wire or 3-wire interface, or combinations thereof. An example of such a master device shown in Fig. Similarly, the slave device may be configured to receive any Protocol or 1-wire or 3-wire interface. An example of such a slave device presents on Fig.

Figure 11 shows an exemplary host device 220 configured to communicate according to the Protocol SSBI one wire. The microprocessor or other device communicates with the host unit 1110 SSBI to perform accesses to read and write (details not shown). The leader block 1110 SSBI can also accept or create other commands or signals, examples of which are described in detail below. A master device 220 transmits and receives data on line SSBI_DATA, which is connected to the pad 1120. The approximate contact area described above. Input (PI) pads is input to SSBI_DATA_IN in the host unit 1110 SSBI. The output signal pad 1120 is taken from the output SSBI_DATA_OUT leading block 1110 SSBI. The inclusion (or excitation) pads occurs in response to a signal SSBI_DATA_OE from the host unit 1110 SSBI. Can also be used for other functions, such as functions of the element that supports the signal level, and the item is, reducing the signal level to the minimum (detail not shown). The leader block 1110 SSBI performs transmission and reception according to the Protocol SSBI.

On Fig shows the slave device is configured to communicate according to the Protocol SSBI one wire. With a slave device 1310 SSBI can interact with various units, registers, functions, and so on (details not shown). Subordinate unit 1310 SSBI can provide data access to records and source data for accesses to read controlled by a master device, such as device 220 shown figure 11. Subordinate unit 1310 SSBI can also accept or create other commands or signals, examples of which are described in detail below. Slave device 230 transmits and receives data on line SSBI_DATA, which is connected to the pad 1320. The approximate contact area described above. Signal (PI) pads is input to SSBI_DATA_IN in the slave unit 1310 SSBI. The output signal pad 1320 is taken from the output SSBI_DATA_OUT slave unit 1310 SSBI. The inclusion (or excitation) pads occurs in response to a signal SSBI_DATA_OE from the slave unit 1310 SSBI. Can also be used for other functions, such as functions of the element that supports the signal level, and an element for reducing the level of signal pominimalnei (detail not shown). Subordinate unit 1310 SSBI performs transmission and reception according to the Protocol SSBI.

In the processor for processing the demodulated signals, such as a master device 220 may be configured with a set of pins that provide a combination of a single-wire and 3-wire interface. For example, to provide many different tire combinations can be selected 12 pins that can be configured. For example, you can configure the 12-wire interfaces or four 3-wire interface. Or one 3-wire interface can be used with 9-wire interfaces. Or two 3-wire interface can be used with 6-wire interfaces. Or 3-wire interface can be used with 3-wire interfaces. You can also use a limited subset of pins, configurable in many types of bus interfaces. The pins can also be configured otherwise for options that are not relevant to the Protocol SSBI or not related to the Protocol SBI. Specialists in the art it is obvious that within the scope of the present invention can use many combinations of pins and configurable bus types.

After switching to single-wire bus secondary bus can be used with fewer pins, and is also possible to reduce the number of components, share a single bus. For example, using a single-wire point-to-point tire can reduce mutual interference compared to the shared bus, and traffic scheduling becomes easier and you can avoid problems with delay, as point-to-point connections eliminates the capacity planning required for a shared bus.

On Fig shows an exemplary host device 220 configured to support Protocol SSBI or SBI. Shown here are three pins that can be used for 3-wire interface or, alternatively, for three 1-wire interfaces. There are three leading block A WITH SSBI and the leader block 1220 SBI. Three pads A-accept signals through multiplexers A-and A-s, respectively. The multiplexers are controlled via the signal line SSBI_MODE that shows which mode (SBI or SSBI) will be selected.

The leader block 1220 SBI known to experts in the art and not described in detail here. The approximate variant of the leader block 1220 SBI may be of any type. Specialists in the art will easily adapt the previously developed devices or schemes of SBI or will be able to offer new to comply with the SBI system described above. Approximate wheel blocks 1110 SSBI detail opisyvayutsya. Approximate unit SSBI can perform Protocol SSBI described above, and may also act according to the SBI Protocol to ensure compatibility with other devices (as described below).

The contact area A used to deliver pulses SBCK in the SBI mode and signal SSBI_DATA0 in SSBI mode. Input (PI) pads are fed into the signal SSBI_DATA_IN in the leader block A SSBI. The output pads passes through the multiplexer A and represents the signal SSBI_DATA_OUT from the leading block A SSBI mode SSBI and impulses SBCK of the leader block 1220 SBI in the SBI mode. Enable (OE) output is fed through the multiplexer A and represents the signal SSBI_DATA_OE of the leader block A SSBI in SSBI mode, and during the SBI mode is set to high level (because SBCK is not a signal with three States, and is always output).

Pad V is used to provide signal SBST in the SBI mode and signal SSBI_DATA1 in SSBI mode. Input (PI) pads comes in the form of a signal SSBI_DATA_IN in the leader block V SSBI. The output pads passes through the multiplexer W and represents the signal SSBI_DATA_OUT from the leading block V SSBI mode SSBI and the signal SBST from the leading block 1220 SBI in the SBI mode. Enable (OE) output is fed through the multiplexer W and represents the signal SSBI_DATA_OE of the leader block V SSBI the SSBI mode, moreover, during the SBI mode is set to high level (as SBST is not a signal with three States, and is always output).

Pad S is used to provide signal SBDT in the SBI mode and signal SSBI_DATA2 in SSBI mode. Input (PI) pads comes in the form of a signal SSBI_DATA_IN in the leader block 1110C SSBI and signal SBDT_IN in the leader block 1220 SBI. The output pads passes through the multiplexer S and represents the signal SSBI_DATA_OUT from the leading block S SSBI mode SSBI and the signal SBDT_OUT of the leader block 1220 SBI in the SBI mode. Enable (OE) output is fed through the multiplexer S and represents the signal SSBI_DATA_OE of the leader block S SSBI mode SSBI and the signal SBDT_OE of the leader block 1220 SBI during the SBI mode.

The interface to the microprocessor or other device, issuing access requests, not shown. Leading blocks 1110 SSBI and SBI can be provided on each interface to perform accesses to read and write through the corresponding interface SSBI or SBI. In alternative embodiments, multiple devices can use the same interface with the leading block SBI or SSBI, and, consequently, for arbitration of accesses between multiple devices can be used arbitrator (not shown).

Alternatively, the leader block SSBI can be used to support protocols SBI and SSBI 1-p is vodnoy or 3-wire support on request. Although this option is not described in detail, specialists in the art will easily be able to adapt as described here to perform this support, if required.

A master device 220, depicted in Fig, is one example of a device suitable for the transition from 3-wire how to wire. A master device 220 can communicate with the existing 3-wire slave devices using SBI Protocol. You can also make communication Protocol SSBI with up to 3 different single-wire slave devices, such as slave device 230 shown in Fig. If necessary, the leader block 1110 SSBI can be modified to support all or part of the SBI Protocol by a desire for compatibility with other devices.

One way of transition from a 3-wire interface to a single-wire SBI interface to the slave device 230 shown in Fig. In this embodiment, the slave unit 1410 SBI (which may represent a new development or to be any already developed a device that is compatible with the Protocol SBI) is connected to the Converter 1420 SSBI slave. Accesses (to write to or read from the slave device 230 are performed through the interface to the sub-block 1410 SBI (not p is the cauldron). Slave device 230 SBI communicates using 3 wires and SBI Protocol. 3 wires pass through the Converter 1420 SSBI slave unit, which performs the transformation necessary to ensure a single-wire connection. This example also supports 3-wire connection, so that this slave device 230 may communicate either with the master device SBI or SSBI master device. Exemplary embodiments of the Converter sub-unit SSBI described in detail below, and other ways obvious to experts in the art in light of the disclosed principles. In alternative embodiments, the slave device 230 subordinate unit SSBI can be designed to support both protocols. One of the advantages of the design of the Converter 1420 shown in Fig, is that the current slave device 230 can be designed to fit a 3-wire interface and accelerate their time to market with new single-wire interface, and the probe can simply be inserted into the device without the necessity of processing the existing kernel.

In the slave device 230 on Fig input signal SBCK get through a contact pad 1430 and delivered to the entrance SBCK_IN Converter 1420 SSBI slave unit. Entrance SBST receive via the contact layer is at 1440 and delivered to the entrance SBST_IN Converter 1420 SSBI slave. These inputs are used for communication Protocol SBI and they can also be used to activate SSBI otherwise (as described below). Pad 1450 receives and transmits the signal SBDT in the SBI mode or the signal SSBI_DATA in SSBI mode. Inlet connection pads (PI) to the pad 1450 is connected to the input SSBI_DATA on the Converter 1420 SSBI slave unit and the input SBDT_IN slave unit 1410 SBI. Connecting the output pads (PO) and enable output (OE) to the pad 1450 go with outputs SBDT_PO_OUT and SBDT_OE_OUT Converter 1420 SSBI slave unit, respectively. Converter 1420 SSBI slave unit also receives a clock input CLK on line SSBI_CLK and the reset signal RESET. These signals can be created within a slave device 230 or outside it.

Converter 1420 SSBI slave unit generates and receives signals SBI to communicate with a downstream block 1410 SBI. Signals SBCK_OUT and SBST_OUT are generated and supplied to the inputs SBCK and SBST slave unit 1410 SBI, respectively. Signals SBDT_PO and SBDT_OE caught and accepted Converter 1420 SSBI slave unit in the form of signals SBST_PO_IN and SBDT_OE_IN respectively.

In this exemplary embodiment, the Converter 1420 SSBI slave unit also creates other heterogeneous signals. The signal SSBI_MODE if the confirmation indicates that podkin the TES device 230 operates in SSBI mode. Otherwise, the slave works in the SBI mode. This signal is used for transformation as described in detail below, and it is delivered as an output signal to external units as an option. Also generates signals to control the blocking of clock pulses, which can be used to lock or unlock one or more clocks to save power or other purposes. Set the signal TCXO_DIS for blocking clock pulses. Set the signal RESET_TCXO_DIS to re-unlock the clock pulses. Exemplary embodiments illustrating the use of each of the signals shown in Fig, described in detail below. Block 1420 Converter SSBI slave unit may determine whether the slave device 1-wire or 3-wire mode to perform the multiplexing between these modes. The mode detection can be performed by checking the lines SBCK and SBST coming from the pads (i.e. pads 1430 and 1440). In 3-wire mode is never executed, the condition under which SBST=1 and SBCK=0, so this condition can be used to set the alarm SSBI_MODE, which controls the multiplexing SBI/SSBI. As mentioned above, in this example, the signal SSBI_MODE is you who Odom from the transducer 1420 SSBI slave unit in the case when it is necessary for other purposes. Exemplary embodiments illustrating these features, described in detail below.

Slave device 230 shown in Fig, can be used for 1-wire or 3-wire connection, as described above. In an exemplary embodiment, this slave device 230 can be configured to support only a single-wire connection SSBI. On Fig shows the slave device, consisting of a subordinate unit 1310 SSBI, which is used exclusively for communication SSBI. On Fig illustrates a configuration in which the slave device 230 that contains a subordinate unit 1220 SBI and Converter 1420 SSBI slave unit, as shown in Fig, you can also use mode only SSBI. In this example, the input SBCK can be associated with the earth. Line SBST can be associated with a high voltage level. This will indicate to the Converter 1420 SSBI slave unit to the need to stay in SSBI mode. Note that this does not require pin mode or other device to select. Then line SSBI_DATA can be connected directly to the United pad SBDT/SSBI_DATA and then can be implemented in connection SSBI.

On Fig shows another variant that performs essentially the same as that shown on Fig. However, in this example, the pins for SBCK_IN and SBST_IN can be IP is turned off (i.e., removed or used for other purposes pads 1430 and 1440). Inside the slave device 230 input SBCK in the Converter 1420 SSBI slave unit is attached to a low level, and SBST to a high level. Thus, you can create a combined 1-wire/3-wire slave device, and when such simple changes additional pins for mode SBI become unnecessary. Other connections are identical to the compounds described in connection with Fig.

To convert the 1-wire option 3-wire can be used many different ways. Block 1420 Converter SSBI slave unit analyzes the data flow SBDT and to generate a signal SBCK and SBST. In various exemplary embodiments, described in detail below, illustrate how to perform this conversion. Among other things this kind of transformation can occur three problems. First, the data transfer rate in the 1-wire scheme must comply with 3-wire circuit. Secondly, can support a variable number of reads and records in the register in one shipment. Thirdly, you might be required to blocks SBI slave devices effectively reset to its original state at the time of shipment with multiple accesses.

Regarding the first problem, then, if the 1-wire and 3-wire the AE schemes use the same data rate, this problem is resolved in the obvious way. Otherwise, you can use buffers to adapt to the difference in speeds between the two schemes. Specialists in the art will know how to perform proper buffering in different ways, in connection with which such buffering is not described in detail here. In the exemplary embodiments described below, the total transmission rate is divided between interfaces SBI and SSBI, although one can imagine other options.

Regarding the second problem, the protocols of the 3-wire interface SBI uses the signal SBST to indicate the beginning and end of the shipment, so the shipment may contain one or multiple reads from and entries in the register. When using the 1-wire bus must inform the slave about when the last access to the register for shipment with multiple accesses. In one embodiment, for each shipment, you can add the header that specifies the expected number of accesses to the register. This can lead to wasteful consumption of resources. Alternatively, you can send a termination character after the last access to the register. It also increases overhead resources, but they can be smaller than in the case of using the header. In a variant, the, described in detail below, to resolve the second problem, use a termination character. When the receiver notices the symbol is complete, it receives information about the forward end and may go into an idle state, waiting for the next start bit. The specified termination character will be as an option to insert when using this mode, particularly when interacting with a downstream device that you want to support both 3-wire and 1-wire protocols. In alternative configurations, the termination character is not required.

It is necessary that the termination character was different from the normal data stream. In this exemplary embodiment, the termination character is defined as a sequence of values of high and low levels, which alternate with each clock cycle for 4 cycles. In exemplary embodiments, which are described in detail, this sequence looks like 1 0 1 0, but for specialists in this field of technology is obvious alternative sequences. Since this signal is alternated with each clock cycle in the sequence is complete, instead of any two clock cycles during normal communication, it is uniquely different from what is in the data stream. Therefore, the termination sequence (“T”) can be sent at any time. Below the link is mi on Fig, which illustrates the shape of the signal in the data line, including the termination character, describes in detail an exemplary diagram of a receiver for detecting termination character.

As for the third issue, the unit SSBI slave device waits for the termination character to determine that the shipment is made. Thus, the master and slave have the opportunity to go out of synchronism when the host device goes into idle mode, and the slave is in the middle of shipment. In the circumstances, the slave device remains in this state indefinitely until the end of the next hop, which initiates a master device. Thus, in order to make the slave rapid transition to an idle state, provided the option for an arbitrary termination characters. This method is shown in the embodiments, described in detail below.

The leader block SSBI

In any case, comprising a master device SSBI, can be used one or several of the leading blocks 1110 SSBI. Leading blocks 1110 SSBI may be identical, or one or some of them can be modified in some way upon the user's request. This section describes exemplary leader block 1110 SSBI. Ports for this example are described in table 2. BP is time charts for procedures for recording and reading the details shown on Fig and 18, respectively. The relationship between the clock pulses of the master and the slave device is shown in Fig. In figures 20-22 shows in detail part of the approximate logic circuits suitable for use in exemplary host unit 1110 SSBI. Specialists in the art it should be clear that these exemplary embodiments are only illustrative, and in light of the above here the basic principles it is obvious that you can offer different alternatives.

Exemplary leader block SSBI can have the following properties. It can work with the contact pad (i.e., 1120) for SSBI_DATA with the element that supports the signal level, which provides a constant signal, and an element that reduces the signal level to the minimum that can be included (details not shown). Specialists in the art should be obvious possible modifications for alternate configurations pads. In order to enable the software to determine ended or not the current transaction SSBI, there may be state bit. For reads, the transaction may not be considered completed until the logic circuit or a software application to query does not execute the read data is returned. May be provided in such a mode that the team SSBI may be delayed until you install a hardware enable signal, or, otherwise, the command takes effect immediately, if the enable signal is already installed. This can be useful when reading or writing should be performed in a known time. For example, measurements slave device can be executed when the slave is in a consistent state. May provide an output signal that indicates when the record. Thus, logic circuit or an application for a query may use information about completed recording for the follow-up. This can be useful when configuring slave devices, such as integrated circuit RFIC, which, for example, may need to be calibrated.

The leader block 1110 SSBI is responsible for converting the request to read or write signals on the 1-wire bus SSBI. This unit is also responsible for the conversion from a serial form into a parallel register data read from bus SSBI. Possible optional block arbitrator SSBI (not shown) may be used for arbitration of requests from a set of control parts (called hosts). The arbitrator may receive requests from hosts using the same system signals, the expected leading block 1110 SSBI. The arbitrator may perform arbitration, allowing you to go for the dew "winning unit" and delaying requests from other hosts. Depending on the host type can be used different logic circuits. The leader block 1110 SSBI can be used to provide an interface through which the host, that is, the microprocessor may be programmed accesses with SSBI programmatically. You can use the system, for example, with three hosts, using the standard unit of the arbitrator and one or more blocks leading SSBI, while the system requiring only one host can be used without an arbitrator, and the host can directly communicate with can bus interface (SSBI master unit.

As an example, demonstrating the flexibility of the possible use of the different options is specified hardware option SSBI_DATA_WD to parameterize the different blocks SSBI. Waveforms to the timing charts of read/write on Fig-19, 24-25, 28, 33-34 and related figures correspond to the case where SSBI_DATA_WD=8.

On Fig-22 shows one exemplary variant of the leader block 1110 SSBI. This option is suitable for use when you want to only support native formats SSBI. You can offer different versions for various alternatives. The modification for this option, detailed to support shipments in FTM mode (an example of an existing format SBI) bus SSBI in alternative described in detail, the lower is with reference to Fig-31.

As described above, with the leading block 1110 SSBI can interact with one or more hosts of various types, and to communicate with them, you can use one or more of the arbitrators and other interface logic circuits. In one exemplary embodiment, one or more hosts can be a microprocessor, digital signal processor (DSP), other General-purpose processor or a specialized processor or any other logic circuit used for the specified interface. Signals and/or commands input and output set for illustrative purposes in the following table 2. These signals and commands input and output are described in detail below with exemplary embodiments create them or respond to them. Specialists in the art will be able to offer various alternative projects of interfaces that you can use. Given that different hosts, such as microprocessors, may be changing the interfaces to perform such accesses as write, read, and to return the results and signals about the state, specialists in the art can easily modify shows the interface or to determine the appropriate logic to communicate with a single or multiple hosts of different types. In the following discussion, for clarity, these details are omitted. the AK is an example of a General nature, the host can interact with the leading block SSBI, using any combination of signals read, write, data, address and other signals to create commands and settings. Write in or read from a predetermined register or bit positions can use to configure settings or issue commands manner well known in the art.

A master device 1110 SSBI interacts with SSBI bus. It receives signals describing the team SSBI, requires, and then creates or controls the serial data stream SSBI. This exemplary leader block SSBI ambivalent in relation to how many objects (i.e., hosts) can initiate commands SSBI and what kind of external arbitration or multiplexing will deal with this unit. In this example, the leader block SSBI is in the idle state until it receives a request for access or another team. Then he sets the dial tone confirmation, performs the transaction and after the completion of access creates a pulse in the line of performance confirmation (DONE), indicating that it is ready to proceed to the next access. As for reads and records the confirmation signal will be a pulse that appears when you select by transaction has ended and when a transaction is the beginning of the starts. Whatever the logic circuitry (i.e., the host) or made the request, it can then modify the registered information (address, data, etc. to prepare the following query and can reset the signal line of the query, if necessary. When the first access is completed, set the confirmation signal of execution. Although for a write command, you may not need the control signal of confirmation of execution, if this information is not of interest to some part of the requesting application, the confirmation signal, perform useful for performing the fetch returned data for reads.

Table 2
Description ports leading block SSBI
PortLine ofDescription
SSBI_CLKInputHeartbeats
RESETInputSynchronized version of the reset signal
SSBI_DATA_DEL[1:0]InputSpecifies the amount of delay SSBI_DATA_IN in units equal to 1/2 of the clock period
IDLE_SYMS[1:0]InputSpecifies the minimum number of characters occupied between transmissions in both directions
SEL_RD_DATA [1:0]InputSpecifies what is RD_DATA select
REQInputSets the request to inform the UI about the need to perform read or write; remains at a high level until the set signal ACK
READInputThe control signal indicating that the query should read
ADDR[7:0]InputRegister address slave unit for forwarding
WR_DATA
[SSBI_DATA_WD-1/0]
InputThe record data to register slave
OVR_VALUEInputThe value that should be set on the line SSBI_DATA in replace mode
OVR_MODEInputManaging si the cash to enable replace mode
SSBI_DATA_PDENInputThe inclusion of an element that reduces the signal level to the minimum, pad SSBI_DATA; is set to discharge; is removed by a subsequent command to continue normal operation SSBI
SSBI_DATA_INInputEntrance SSBI_DATA
SSBI_DATA_OUTOutputOutput SSBI_DATA
SSBI_DATA_OEOutputThe inclusion of output pads SSBI_DATA
RD_DATA
[SSBI_DATA_WD-1:0]
OutputRead data returned by the slave registers block
ACKOutputPulses when the received transaction SSBI and when the transaction is started
DONEOutputPulses when completed transaction SSBI; can be used for sampling RD_DATA for readings
STATE_INVOutputSignal inversion STATE
READ_REQ_SERVEDOutputInstalled on the service time of a request to read

Time charts for entries and readings shown on Fig and pig respectively. Arguments relating to these figures, can be applied to approximate variant, described in detail below in connection with Fig-22. For both types of access instead of individual lines SSBI_DATA_IN and SSBI_DATA_OUT shown combined bus SSBI_DATA. In the sample configuration schemes pads that appears in line SSBI_DATA_OUT will appear in the line SSBI_DATA_IN. For the record, the signal SSBI_DATA_IN ignored. For reads the signal SSBI_DATA_OUT excited to pad SSBI_DATA only when an alarm has been set SSBI_DATA_OE. In the form of a signal for SSBI_DATA symbol RW to denote bits read/write (in this example, 1 - read, 0 for write), A7 - A0 to the address bits, D7 - D0 for bit data (SSBI_DATA_WD=8) and P for a bit of pause. Note that alternative options may include fewer or more address spaces, and also to have different data width (i.e., the parameter SSBI_DATA_WD not equal to 8).

The leader block SSBI is reset to the idle state (shown on line STATE) and remains there until it is detected setting signal REQ. Then the leader block SSBI selects the other input signals, set the pouring signal ACK (acknowledge), and generates a serial data stream, shown on line SSBI_DATA. At the end of the access pulse appears DONE to indicate completion of a conversion. Once you have the signal ACK from the next clock cycle, can be set signal REQ for the next access. This access will be delayed until the current access. In this example, the signals REQ, ADDR, WR_DATA (write) and READ will reflect the settings for the next access will not be installed until the ACK for this access (and then these parameters can be changed for the next access). On Fig and 18 and the second access (REQ and ACK) is shown by the dotted line. If the second request is made before completion of the first request, then the leader block SSBI can begin the next shipment, without affecting the character of the vacancy. Slave device to detect the initial symbol not necessary to fix the signal transition from low to high. It is enough to select the initial character without preceding character is not occupied, and in the SSBI master unit may be provided to support this option. However, in this embodiment sets the programmable parameter IDLE_SYMS to insert from 1 to 3 characters unemployment between shipments, if required.

On Fig, when installed in the signal REQ, the shift register (i.e., shift registers 2130 and 2140 and trigger 2110) is sampled from lines ADDR, WR_DAA and READ together with the start bit. In the line STATE is set SAMPLE(1), and the start switch in line STB. Signal STB acts as an enable signal of the counter which initiates counting BITCNT transmitted symbols. All 18 bits forwarding (start bit + READ + ADDR + DATA) are shifted to the shift register with each of the next clock cycle. During the second half of the last character (D0) pulse appears DONE. At this time in the form of a pulse may also receive another signal DONE_DELX (Fig not shown), described below, or the pulse may occur after the number of symbol periods specified in IDLE_SYMS. If there is no request pending, then DONE_DELX moves from state STATE in state Idle (0), and the leader block SSBI waiting for the next installation of the signal REQ. If you have a query that is waiting to run, the signal REQ is observed in the same cycle, which has a signal DONE_DELX that leads to the installation of the ACK signal in the next cycle and the STATE support in the form of a SAMPLE (1). This forwarding continues in the same manner as was described for the first shipment.

On Fig shows the read operation. The unit performs the same steps as when recording except that the signal SSBI_DATA_OE be removed as soon transferred to the address A0. Then the connected slave device controls the bus to return the data register of the slave device. As soon as podchinen the e device returned the specified data, there comes another bit of pause, after which the master device can initiate a bus. The bits read are received in the shift register (i.e., shift registers 2130 and 2140), which again is fixed in the cycle preceding the installation of the signal is DONE. In this example it is thus to prevent unnecessary switching RD_DATA, because the signal RD_DATA can act on a large number of multiplexing schemes or other logic circuits. Logic circuit receiving a signal RD_DATA, can access data using the DONE as an enable signal. Subsequent requests can be processed in the same manner as the records described above.

Consider the moment in which the leader block SSBI must fetch bus SSBI_DATA to obtain a bit of reading. In the ideal case, the bus SSBI_DATA to the host device should appear as shown in Fig. There may be different factors at work that impede the realization of this ideal situation: for example, uncertainty sampling in the receiver due to an erroneous determination phase, as well as various delays, including delays pads, cards, and internal circuits.

On Fig shows this phenomenon. The top row of signals shows the pulses SSBI_CLK in the master unit SSBI. The second pair of signals shows how the look out is it the signal SSBI_DATA in the master and slave devices in the assumption, that the delays are missing. The third set of signals shows what happens when there is a delay equal to 1/2 cycle SSBI_CLK in each direction. The consequence of this delay is that the data read may appear in line SSBI_DATA master device to one full clock period later than in the absence of delays. In addition, the exemplary slave device will select the characters in the range anywhere from 25 to 75% of the clock period. The result is inaccuracy delayed sample data at the master device.

In an exemplary embodiment, for controlling these effects in the leader block SSBI introduces some flexibility. There are two software features that allow you to get a reliable system, capable of processing delay value to 3 clock periods.

The first possibility is to delay SSBI_DATA_IN. As discussed above, uncertainty sampling in the slave device cannot be adjusted in the host device, if you are sure that the phase is defined with an error. However, when using this system delays for a given port SSBI will be relatively fixed. As a result, if there is very little delay, the sample point can be moved to an earlier point. When relatively large delays, the point is uborki can be moved to an earlier point. So it can be easily performed in an exemplary SSBI master unit provides the opportunity for flexible delay the input signal SSBI_IN 0, 0,5, 1 or 1.5 character times. Then for any occasion will get delayed version SSBI_IN at the end of symbol periods. In any given application, you can use other delays (including smaller or large - selection) (i.e., only 0.5 and 1.5 cycle).

The second option allows you to control the cycle BITCNT, which gather data RD_DATA returned by the slave device. On Fig shown that the signal RD_DATA available in cycle 19. However, data collection can also be performed later in the cycle than the cycle 19. The moment when the leader block SSBI will control line SSBI, can also be adjusted in order to give time for preparation RD_DATA. The management of this function is based on the parameter SEL_RD_DATA. For example, when SEL_RD_DATA=0, are shown in bold numbers on Fig and 22, which are described in detail below. When SEL_RD_DATA=01, these numbers are incremented by 1.

These settings can be selected using a number of different ways. One way associated with the developer, which you should carefully review the timing diagram and evaluate various delays. Alternatively, an adequate result can give an approach based on the method of the Rob and error. For example, the procedure may simply be read from register slave, waiting for a specific value, and then adjust the setting if the return value was wrong.

On Fig-22 shows an exemplary circuit suitable for use in exemplary host unit 1110 SSBI. Specialists in the art in light of the guidelines for the apparent various modifications and alternatives. In the upper part Fig shows a logic circuit for signal delay SSBI_IN signal-based SSBI_DATA_DEL. The signal SSBI_DATA_IN_DEL is constructed as follows. The signal SSBI_DATA served in triggers 2010 and 2030. Note that all clocked devices on Fig-22 synchronized signal SSBI_CLK or its inversion (shown in standard notation with a circle before a clock speed). Note that the trigger 2010 synchronizes the signal inversion SSBI_CLK and trigger 2030 synchronized signal SSBI_CLK directly. The output trigger signal 2010 is routed to the input of the trigger 2020. The signal SSBI_DATA_IN is fed to one input of the multiplexer 2040, as well as the outputs of the triggers 2010-2030. The signal SSBI_DATA_DEL is used to select one of the multiplexer input 2040 as output, or SSBI_DATA_IN_DEL.

Below Fig shows the logic circuitry to generate a signal DONE_DELX signal-based IDLE_SYMS. In this example, the signal DONE_DELX is formed in logical CX is IU 2050 in the form of a circuit And to the input of the STB and the other input, which is the output of the circuit OR to the input (NOT SREAD AND BITCNT =17 + IDLE_SYMS) and (SREAD and BITCNT =19 + IDLE_SYMS). Recall that the numbers in bold correspond to the option SEL_RD_DATA = 0, and these numbers can be replaced with other values, as described above.

On Fig shows all of the shift register circuit described above in connection with Fig and 18. Starting with the least significant bit (LSB), this circuit consists of a shift register 2140 c number of bits specified by the SSBI_DATA_WD, 9-bit shift register 2130 and one-bit register (or trigger) 2110, which excites the signal SSBI_DATA_OUT. In this example, one-bit register 2110 pre-loaded with a starting character. The signal REQP is used to record the information about the request in the chain of shift register. 9-bit shift register 2130 preloaded bit read/write and address bits (sign & indicates a concatenation operation). Shift register 2140 with SSBI_DATA_WD bit pre-loaded data entry for write operations, or all zeros for read operations. These zeros ensure that at the end of read operations in a single-bit register 2110, outstanding signal SSBI_DATA_OUT, which in this example is used for state unemployment had reached a value of 0. Signal STB is used to activate the chain of shift registers to perform the shift. During transmission, the signal STB bodø is located on each of the next clock cycle (described below).

Shear input to the shift register 2140 is defined as the output of multiplexer 2150, which takes the value 0 when an alarm has been set SSBI_DATA_OE, and is SSBI_DATA_IN_DEL, otherwise. It is possible to make available a parallel output shift register 2140 as RD_DATA_PRE. Shift out shift register 2140 connected to the shift input of shift register 2130. Shift out shift register 2140 in this example goes to another logical diagram to illustrate another feature, which is optional. Defined in replace mode, allowing the value specified by the parameter OVR_VALUE, to replace the logical function OR 2120 shear output shift register 2130 using signal REQP (used in normal operation SSBI)when an alarm has been set OVR_MODE, which in this example is selected in the multiplexer 2160. The output of multiplexer 2160 is input to the trigger 2110 (shown in the form of a trigger, a reset signal RESET. The trigger output 2110 generates a signal SSBI_DATA_OUT.

On Fig shows additional logic control for a host unit 1110 SSBI. Once the signal STATE becomes equal to 1 (trigger output RS 2220 set/reset), turn counter 2228 to create BITCNT. When running records a chain of shift registers (2110, 2130 and 2140) is included in each of the next clock cycle until you have finished what I am all data while this circuit will be pushed zeros. When performing reads nominated primary symbol and the address bits, when the slide zeros. However, when it is time to sample the incoming data read shift register 2140 used to record data, with the number of bits specified by the SSBI_DATA_WD, selects the signal SSBI_DATA_IN_DEL. As soon as all the bits of the data read will be pushed, they are available on line RD_DATA_PRE and re-recorded in the register 2208 to create RD_DATA in the loop before setting it DONE. The enable signal is in the form of logical functions And inputs SREAD, NOT STB and BITCNT=19.

As the output trigger signal SR 2220 generates a signal STATE. Formed the input set for RS trigger 2220 in the form of the output logic circuit And 2216 with inputs REQP and NOT RESET. The reset input of the RS trigger 2220 is formed as the output of the logic circuit OR 2218 with inputs DONE_DELX and RESET.

Signal STB (denoted as CNT_EN) is formed as an output reset trigger 2224. The entrance to this trigger is output inversion scheme 2226, resulting in a signal STB, changing each clock pulse when the trigger is reset. The reset input is generated as the output of the logic circuit OR 2222 with inputs REQP and NOT STATE.

The signal BITCNT (in this example, 5-bit signal; in alternative embodiments may be provided other the parameters, requiring alternative values in Fig. 20 to 22) is formed as the output of the counter 2228. Reset counter 2228 identical to the reset trigger 2224. The enable signal of the counter 2228 is the signal CNT_EN (or STB), which allows to keep score during transmission or reception, as described above.

The signal SREAD is formed as a trigger output 2210, which is reset by the RESET signal. Trigger 2210 is enabled by the signal REQP. The input D of the flip-flop 2210 signal is READ.

In this example, the signal READ_REQ_SERVED is created to use a different logic And 2230 with inputs SREAD and STATE.

The signal REQP is formed as the output of the logic circuit And 2204 input REQ and a second input received from the logic circuit OR 2202 with inputs NOT STATE (STATE_INV) and DONE_DELX. Output REQP is delayed by one clock pulse in the trigger 2206 to generate a signal ACK.

In this example, after the reset signal STATE and SSBI_DATA_OUT are set to the initial state synchronously. The signal SSBI_DATA_PDEN is set asynchronously, causing the signal transfer SSBI_DATA_OE at a low level. In this example, when the software application initiates some action interface SSBI, it writes to the control register or uses some alternative way of exchanging signals for reset bit SSBI_DATA_PDEN. This changes the signal level SSBI_DATA_OE '1', and the leader block 1110 SSBI triggers the initiation of '0' on line SSBI_DAT (as described above).

Thus, the signal SSBI_DATA_OE is formed as the output of the logic circuit And 2214 input NOT SSBI_DATA_PDEN and a second input which is the output of the trigger 2212. Trigger 2212 reset signal RESET. Trigger 2212 is enabled by signal STB. The input D of the flip-flop 2212 is formed by a logical circuit OR inputs BITCNT<9, BITCNT>=19 and NOT SREAD.

Again recall that the numbers in bold correspond to the case where SEL_RD_DATA=0, and these numbers may be changed as described above. All registers on Fig synchronized with the signals SSBI_CLK.

Subordinate unit SSBI

On Fig shows the approximate variant sub-block 1310 SSBI. Description ports bus interface approximate SSBI slave unit are detailed in table 3. In this example, the bus interface 2310 slave unit is connected to the block 2320 registers slave unit. Single-wire data bus SSBI is connected with the contact pad (not shown), and the incoming data is being received at the bus interface 2310 SSBI slave unit on line SSBI_DATA_IN.

Outgoing data are available on line SSBI_DATA_OUT, and the orientation of the pads is regulated through the line SSBI_DATA_OE. The signal SSBI_DATA_CLK supplied as clock pulses to the bus interface 2310 SSBI slave unit. Block 2320 registers slave unit may also receive a signal SSBI_CLK, but it is not mandatory (optional milling the m to determine generated if the pulse SSBI_CLK, described in detail below). Accesses to the register of the slave unit are performed between bus interface 2310 SSBI slave unit and registers 2320 slave unit via signals ADDR, WR_STB, WR_DATA and RD_DATA. The outputs of registers slave unit are received in the slave device 230 for their use. Values read from the slave device 230 are received in the registers 2320 slave unit for access via the bus SSBI.

The bus interface 2310 SSBI slave unit is responsible for performing serial-to-parallel conversion signal single-wire bus with its subsequent conversion to a request to read or write. This request is sent in block 2320 registers slave unit, which contains the registers record and is responsible for the multiplexing registers are read. In one embodiment, this exemplary configuration has the advantage consisting in the fact that the bus interface 2310 slave unit can be designed so that it was identical for different schemes slaves, while in block 2320 registers slave device uses logic circuits that are specialized for the slave device. Can also be used with different alternatives.

The bus interface 2310 SSBI slave unit check is that the presence of the starting character in the line SSBI_DATA, which means the beginning of shipment. Then it looks for the first character to determine whether it is a character read or write, and then scans the address bits. Once all the address bits are scanned, they are displayed in the form of a signal ADDR in block 2320 registers slave unit. To write data bits are shifted, and then served in the form of a signal WR_DATA in block 2320 registers slave unit together with the gate signal WR_STB. The signal WR_STB used block 2320 registers slave to fetch the fields of the address (ADDR) and data (WR_DATA). To read after the signal ADDR passed in block 2320 registers slave unit, during a bit of pause data register read SSBI (RD_DATA) are selected bus interface 2310 SSBI slave unit, and then bit-shifted in the tire SSBI. As soon as one transaction ends, the bus interface 2310 SSBI slave unit enters a state of waiting for the next start bit.

In this example, it is not permitted to perform a variety of transactions completed by the termination character (for example, BTM, described above). This configuration provides a simplified solution (reducing hardware, reduction of test cases), and it is suitable for use when there is a small benefit from resolving multiple shipments, i.e. the volume of business is x data for individual shipment is relatively small. In alternative embodiments, there are many possible transaction, followed by a termination character.

In alternative embodiments can use other versions of the bus interface 2310 SSBI slave unit. One difference may be the number of output ports. Configuration can have one set of ADDR, WR_STB, WE_DATA and RD_DATA or more sets of these signals. Thanks to the introduction of additional sets may be independent access to multiple registers read and/or write. Another option is to have bi-directional data bus or individual buses for reading and writing data. Specialists in the art of the obvious various other alternative options. For clarity, the discussion of the exemplary embodiments, described in detail below, contain a single set of signals ADDR, WR_STB, WE_DATA and RD_DATA with separate busses for reading and writing data.

Table 3
Description ports bus interface (SSBI slave unit
PortDirectionDescription
SSBI_CLKInputHeartbeats
RESETInputSynchronized version of the reset signal
SSBI_DATA_INInputEntrance SSBI_DATA_IN from the contact pads of the chip
SSBI_DATA_OUTOutputOutput SSBI_DATA on a contact pad of the chip
SSBI_DATA_OEOutputThe inclusion of output pads SSBI_DATA
ADDR[7:0]InputRegistered address SSBI
WR_STBOutputThe gate pulse recording; can be used as a clock pulse for the register record SSBI
WR_DATA
[SSBI_DATA_WD-1:0]
OutputThe recorded data entries in the register SSBI
RD_DATA
[SSBI_DATA_WD-1:0]
InputMultiplexed read data register SSBI; simplified to changes ADDR
TCXO_DISInput'0' in normal RA is h; '1'when SSBI_CLK off; can be stored in the register slave
RESET_TCXO_DISOutputUsed to reset bits register TCXO_DIS

Writing and reading are shown separately on Fig and 25, respectively. Arguments relating to these figures, can be extended to approximate variant, described in detail below in connection with Fig-27. Timing diagram of the read/write head is described for the case when the parameter SSBI_DATA_WD equal to 8. Alternatives for SSBI_DATA_WD described with reference to Fig-27. For both types of access instead of individual lines SSBI_DATA_IN and SSBI_DATA_OUT shows the combined bus SSBI_DATA. In the sample configuration schemes pads all that appears in the line SSBI_DATA_OUT will appear in the line SSBI_DATA_IN. For the record, the signal SSBI_DATA_IN will be ignored. For reads the signal SSBI_DATA_OUT excited to pad SSBI_DATA only when an alarm has been set SSBI_DATA_OE. For waveform SSBI_DATA abbreviated RW to denote bits read/write (1 read, 0 records in this example), A7-A0 to the address bits, D7-D0 for data bits and P bits for pause. Note that alternative options may include fewer or more address spaces, and different values of the width of the data (i.e., SSBI_DATA_WD not equal to 8).

On Fig upon detection of the start bit signal FOUND_ST goes to a high level. He creates a logical circuit, which, when the STATE is equal to Idle(0), simply performs sampling of the signal SSBI_DATA on each clock pulse until it found a high level signal. The signal FOUND_ST created by half a clock cycle later, to account for the metastable resolution. The signal FOUND_ST causes a transition STATE in the state Sample (1)that, in turn, allows changeover signal STB. In turn, the signal STB cause a decrease in the value BITCNT. Signal STB is used as the enable signal for the sample characters in the shift register (i.e., 2628). The shift register has a few bits, shown as INPUT_DATA_SIZE. This constant has a value greater than 8, or equal SSBI_DATA_WD. Bit CNT (i.e., 2646) keeps track of how many bits have been selected. Once all address bits are fixed (designated as BITCNT=8), the contents of the shift register is fixed again (i.e., 2634) and displayed in the ADDR line. This re-fixation is not required, and its purpose is to save energy in the block registers slave ADDR as potentially nourishes quite a large number of logic circuits multiplexing. Similarly, once all data bits recorded (marked as BITCNT=16), the contents of shear is of egistra fixed again (that is, 2636) and displayed in the line WR_DATA. Given the momentum WR_STB as block 2320 registers slave knows that you want to write. Sets the DONE signal when bits CNT=17, to reset the STATE to the Idle state (0), so that the process can be repeated, if necessary.

On Fig shows the read operation. The unit performs the same steps as for the records, making the address on the ADDR line. Not shown in the previous figure, the data RD_DATA can be multiplexed on the basis of ADDR as just for the record, the signal RD_DATA can potentially change when you change ADDR, even if it is ignored. For BITCNT=9 cycles sampled signal RD_DATA in the shift register (i.e 2660) with bit shifting line SSBI_DATA_OUT. Set the signal SSBI_DATA_OE to indicate when to initiate a data pad SSBI_DATA, and this signal remains high until all the data will not be shifted into the tire. When this bit CNT=19, sets the DONE signal to reset STATE to an idle state (Idle), so that the process could be repeated, if necessary.

Note that the read data are output at full clock cycle earlier (1/2 symbol period). This reduces the efficiency bit of pause between address and data reading. In this case, one clock cycle without overlapping. Advantages of the this approach is what if the data read SSBI shifted without saving proposed discharges, when observed data recording SSBI from the point of view of the host device, the data read will appear later due to the delay in acknowledgment. Thanks to output data read in advance they will be displaced by the amount of delay for the ACK, which leads to their appearance closer to that moment when the host device really expect any.

Due to the fuzzy definition phase there is no guarantee that the signal SSBI_CLK will be aligned with SSBI_DATA, as shown in the above figures. These figures SSBI_CLK shown to the extreme, perhaps the "best case". "Worst case" will be when the start bit is one full clock cycle further, as a result, all signals (except SSBI_DATA) shifted to the right by one clock cycle. It does not give rise to problems. Instead of sampling 25% of the characters in the character period, they will be selected by 75% in symbol period. For reads instead excitation data read SBI 1/2 symbol period earlier this will occur on a 1/2 symbol period later. This one cycle variability is reduced to half of the cycle by using a signal LATE. He formed a scheme similar to the scheme for signal FOUND_ST (both schemes are described in detail) except that it operates on about isobologram ends of the clock pulse. When the LATE signal is equal to 0, the signals SSBI_DATA_OUT and SSBI_DATA_OE delayed by half a clock cycle before using them. When LATE is equal to 1, they are used as is. The schema associated with the signal LATE is also available for Converter 1420 SSBI slave unit provided above and described in detail below in connection with Fig-35.

As an option can be entered another possibility, namely that a master device 220 may block the clock pulses of the slave unit by setting some register bit slave unit, designated here as TCXO_DIS. When this bit is set, the pulse SSBI_CLK slave unit off. To enable these clock pulses again the master device sends slave device sequence 0 1 0. It is perceived by the slave device, which generates a signal RESET_TCXO_DIS. This signal resets TCXO_DIS, which, in turn, again includes SSBI_CLK for the slave device. This option allows the host device to transfer the slave SBI in standby mode and therefore provides energy savings (further described below).

On Fig shows the approximate scheme, which is suitable for use in an exemplary bus interface 2310 SSBI slave. You can use various alternatives DL is shown governance mechanisms, using any combination of logic circuits, finite state machines, microcode, software, etc. In this example, bits CNT refers to the various required state. Note that the control signals depend on the parameter SSBI_DATA_WD and are subject to change in accordance with his change.

Parameter INPUT_DATA_SIZE is calculated as the maximum value (2614) of 8 and SSBI_DATA_WD. In an exemplary embodiment, both parameters are known in advance and used to create a logical configuration for the selected parameter SSBI_DATA_WD. Can be used an alternative to adaptation programmable values for SSBI_DATA_WD. For example, the selected bit options for inputs to registers 2632-36 may include previous or subsequent logical processing for adaptation of software changes. Another option is the availability of programmable size ADDR, with similar changes to fit different values for the ADDR. These details are not shown. Specialists in the art can easily adapt these and other options in the light of the principles of the present invention. For clarity of discussion hereinafter, it is assumed that for this use case parameters SSBI_DATA_WD and INPUT_DATA_SIZE are fixed.

Note that all clocked devices on Fig synchronized pulses SSBI_CLK or in what eremi (according to the standard notation shows a circle in front of the clock input). If not mentioned otherwise, the registers are described in detail below, are synchronized by pulses SSBI_CLK.

In this example, the location of the start bit is defined as follows. The signal SSBI_DATA_IN fixed trigger 2602 using inverted signal SSBI_CLK and trigger 2610 using pulse SSBI_CLK. The trigger output 2602 fixed trigger 2604 using pulse SSBI_CLK to generate a signal FOUND_ST_N. The trigger output 2610 fixed trigger 2612 using inverted SSBI_CLK to generate a signal FOUND_ST. All four trigger reset logic OR (2606, 2608) to the input STATE and RESET_EFF. The signal FOUND_ST_N fixed trigger 2618 to generate a signal LATE to be included logic And 2616 to the inputs FOUND_ST and NOT STATE. The signal FOUND_ST fixed trigger 2622 to generate a signal STATE that is synchronized with signal inversion SSBI_CLK. Trigger 2622 is reset asynchronously signal RESET_EFF. Enable trigger 2622 is determined by the output signal of the multiplexer 2620, which selects the DONE signal when the set signal STATE, and selects the signal FOUND_ST, otherwise.

The DONE signal is defined as the output of the logic circuit And the 2626 to the input of the STB and the input of the logic circuit OR 2624 with two inputs. The first entry into the scheme OR 2624 is the output of the logic circuit with inputs NOT READ and BITCNT = 9 + SSBI_DATA_WD. The second entry in the schema is OR 2624 is the output of the circuit And inputs the READ and BITCNT = 11 + SSBI_DATA_WD.

The signal SSBI_IN shifted into the shift register 2628 using inversion signal SSBI_CLK included logic And 2630 with inputs NOT STB and STATE. A parallel output shift register 2628 represents the size INPUT_DATA_SIZE. The least significant output bit is recorded in the register 2632, which is included in the logical circuit And inputs STB and BITCNT=1 to generate a READ signal. In the case 2634 recorded 8 least significant output bits to generate a signal ADDR, which is included in the logical circuit And inputs STB and BITCNT=9. In the case 2636, include a logic circuit And inputs NOT READ, STB and BITCNT=9 + SSBI_DATA_WD, fixed output bits starting with SSBI_DATA_WD - 1 to 0, to create WR_DATA. This enable signal is also recorded in the register 2638, asynchronously reset signal RESET_EFF, to generate a signal WR_STB.

Signal STB is generated as an output trigger signal 2640, the entrance of which is a signal NOT_STB, and the reset trigger signal is NOT STATE. Signal NOT STB is formed by the inverter 2644, which inverts the signal STB. Signal NOT STB is recorded in the trigger 2642 to generate a signal NOT STB_D. The output of the counter 2646 generates a signal BITCNT, which is reset by a logical circuit OR to the input STATE, and NOT DONE, and is enabled by signal STB.

Optional circuit block clock pulses, described above, is implemented in this example as follows. The signal TCXO_DIS f is ciruits in the trigger 2648, a synchronized signal SSBI_DATA_IN. The trigger output 2648 fixed trigger 2650, which is synchronized signal NOT SSBI_DATA_IN, to generate a signal RESET_TCXO_DIS. Both triggers are reset asynchronously by the RESET signal.

The signal RESET_EFF is formed as a trigger output 2672, the entrance of which is the trigger output 2670. The entrance to the trigger 2670 is a trigger output 2668, the entrance of which is '0'. All three are established asynchronously trigger logic OR 2666 with inputs TCXO_DIS and RESET.

The signal SSBI_DATA_OUT is selected through the multiplexer 2664 as out of the output shift register 2660, when a signal LATE. The signal SSBI_DATA_OUT is selected through the multiplexer 2664 as trigger output 2662, when the signal LATE is not installed. Input trigger 2662 is shifted to the output shift register 2660, synchronized by the signal inversion SSBI_CLK. Parallel input in the shift register 2660 is input RD_DATA width SSBI_DATA_WD. Shear input to the shift register 2660 equal to '0'. Shift register 2660 boot logical circuit And inputs the READ, NOT the STB and BITCNT=9. Perform shift shift register 2660 allowed logic And 2658 with inputs NOT STB_D, READ, and SSBI_DATA_OE_REG.

The signal SSBI_DATA_OE is selected through the multiplexer 2656 in the form of a signal SSBI_DATA_OE_REG when an alarm has been set LATE. The signal SSBI_DATA_OE is selected through the multiplexer 2656 as output three is Hera 2654, when the signal LATE is not installed. Trigger 2654, synchronized by the signal inversion SSBI_CLK, as input signal has SSBI_DATA_OE_REG. The signal SSBI_DATA_OE_REG is formed as trigger output 2652. Input trigger 2652 is the output of the logic circuit And inputs the READ, BITCNT>=10 and BITCNT<=(9+SSBI_DATA_WD). Trigger 2652 is enabled by signal STB and asynchronously reset signal RESET_EFF.

On Fig shows an exemplary logic circuit suitable for use as a block 2320 registers slave unit. In this example, the parameter SSBI_DATA_WD is set to 8 for illustrative purposes. Register 2710 is an example of a register for storing the output WR_REGxxx_DATA. This register, which can be synchronized signal WR_STB receives input WR_DATA. You can use a variety of registers recording and xxx can be replaced with the appropriate identifier. Note that for a particular address may need to record not all bits WR_DATA, with corresponding memory elements can be eliminated. Enable signal for each register 2710 may be permitted under the relevant address under the control of the signal ADDR (details not shown). Alternatively, as clock pulses you can use the signal SSBI_CLK signal WR_STB, which is part of the enable signal. If necessary, in the slave device 230 could the t to be filed various output signals WR_REGxxx_DATA.

In this example, the data RD_DATA is generated as the output of the logic circuit 2720 multiplexing selected in accordance with the signal ADDR. You can use different ways of implementing multiplexing, such as standard multiplexers, the combinatorial logic circuit, tire technology with three States, etc. as Inputs to the multiplexer 2720 are n input signals, denoted RDREG0_DATA - RDREGn_DATA, which are assigned according to the designations of their respective addresses. These input signals can come from any blocks in the slave device 230 when it is necessary.

The leader block SSBI supporting FTM mode

This section shows a sample of the leader block 1110 SSBI adapted to support FTM mode for the interface SSBI, described in detail above. On Fig-31 and in the relevant sections describe in detail the changes that are necessary to approximate the master unit SSBI described in connection with Fig-22, discussed above, to support FTM commands on a single-wire bus. This leader block 1110 SSBI able to support team SSBI and team FTM mode selected based on the bit configuration called FTM_MODE). Table 4 shows additional ports for this exemplary variant, which can be combined with the ports in table 2.

Table 4
Description modified ports leading block SSBI
PortDirectionDescription
DISABLE_TERM_SYMInputIn FTM mode during installation will not allow the sending of the termination character in the slave device at the end of the forwarding
SENT_TERM_SYMInputIn FTM mode generates a pulse to make a termination character in slave
FTM_MODEInputEnable bit mode FTM
SLAVE_ID[5:0]InputEnter the ID of the slave device

When installing the signal FTM_MODE it indicates that the access will be in FTM mode. For accesses performed not in FTM mode, waveforms and circuit can be similar modification to the scheme described above in connection with Fig-22. At a high level to support FTM mode the following changes are necessary. First, the format of the command must match the FTM mode 3-wire mode. Secondly, you need a schema for identifying the head of the decision package shipments, so that she could send a termination character. Thirdly, the signal IDLE_SYMS specifies the number of characters of unemployment between the two packages, and not between individual accesses.

To simplify the following description, the term "access" is used to refer to a specific read or write. The term "packet" will be used to refer to the sequence in which first passed the ID of the slave device, followed by one or more accesses and completes all transfer termination character. In alternative embodiments can be implemented alternatives to termination character, examples of which were mentioned above. Thus, the package may be one or more accesses. Note that in the regime of non FTM mode, packets do not. All accesses are treated as a single entry.

For the package, the first access is preceded by the transmission of the start bit, the bits of the mode and ID of the slave device. Subsequent accesses can be carried out without these programs. Sets the signal CONT, an example of which is disclosed in detail in Fig (as the trigger output 3110) and used to indicate whether the access is the first access (0) or later access (1). The signal CONT is set in the same cycle, where it will be installed signal REQP for the second access, and stored until it is sent to ignal complete. Thus, the signal CONT may be used to configure the chain shift to correctly bypass the initial bits, bits mode and the ID of the slave device (as described below).

After completion of the first access set signal CONT and the pulse is DONE. When the DONE signal is at a high level, you can analyze Segal REQ to determine whether this package subsequent access. If so, you may receive the ACK pulse and the scan chain new parameters are fixed as standard except that the scan chain is configured to bypass bits mode and the ID of the slave device. Also bit CNT is loaded with a value of 10 instead of 0, because the initial bits mode bits, the ID of the slave device and the first bit of pause skipped. The DONE signal is set for each access.

At the end of the service (regardless of whether it is in one shipment, or a bunch of shipments) to be output termination character. The TERM signal is installed on the entire interval of sending the termination character. During this interval the value of a bit CNT should increase by one unit with each cycle instead of increasing by one unit every second cycle, and the output sequence is 1010. In alternative embodiments can use alternative combin, is the symbol of completion. As soon as you sent the termination character, it is necessary to generate the internal signal "proof of execution", DONE_DELX, which is delayed in accordance with the signal IDLE_SYMS, so may start the next batch, if any. On Fig shows waveforms representing the end of the sample package. Note that in this exemplary embodiment, the pulse STB appears twice on the symbol interval is complete, although they can be ignored in this scheme (as described below).

On Fig-31 shows an exemplary circuit for use in an exemplary host unit 1110 SSBI, modified to support FTM mode. Specialists in the art in light of the guidelines for other obvious modifications and alternative options.

On Fig shows a modified logic circuit depending on the configuration settings. Creating a signal SSBI_DATA_IN_DEL is the same as in the original scheme. Creating a signal DONE_DELX different from the version on the basis of FTM_MODE. Mode FTM_MODE this signal appears in the form of a pulse at the end of the package. Because at this time the bit CNT is increased by one unit at each clock cycle, the signal STB may be ignored.

As Fig, in the upper part Fig shows the logic circuitry for signal delay SSBI_DATA_IN signal-based SSBI_DATA_DEL. A signal is generated SSBI_DAA_IN_DEL exactly the same as Fig. The signal SSBI_DATA served on the triggers 2010 and 2030. Note that all clocked devices on Fig-22 synchronized pulses SSBI_CLK or their inversion (shown in standard notation circle before a clock input). Note that the trigger 2010 synchronizes the signal inversion SSBI_CLK and trigger 2030 directly signal SSBI_CLK. The trigger output is 2010 is fed to the input of the trigger 2020. To one input of the multiplexer 2040 in the form of the outputs of the triggers 2010-2030 signal SSBI_DATA_IN. The signal SSBI_DATA_DEL is used to select one of the multiplexer input 2040 as output, or SSBI_DATA_IN_DEL.

Again, the signal DONE_DELX is formed on the basis of the signal IDLE_SYMS. As Fig, the logic circuitry 2050 implements a logical function And where the inputs are the signal STB and the output logic circuit OR inputs (NOT SREAD AND BITCNT=17+IDLE_SYMS) and (SREAD AND BITCNT=19+IDLE_SYMS). Added multiplexer 2910 to generate a signal DONE_DELX. The signal DONE_DELX selected as the output logic circuit 2050, when the signal FTM_MODE is not installed, and BITCNT=31+IDLE_SYMS when the signal FTM_MODE installed. Recall that the numbers in bold correspond to the condition SEL_RD_DATA=0, and these numbers can be modified, as described above. As before, for simplicity, all these numbers correspond to the case where SSBI_DATA_WD=8.

Most modifications of the logic circuits belong to the chain of shift registers, while the data on Fig. This chain is extended, so that you can remember bits mode (01) and SLAVE_ID together with bits pauses, which are present after each set of 8 bits. These additional bits pause treated as a transfer (the data values to the case not include) unlike the case of the transfer bus to the third state (how can it be made known block SBI). It is no longer necessary to transfer the bus is in the third state every 8 symbol periods.

This exemplary modified circuit shift register is divided into parts as follows. The signal SSBI_DATA_OUT is created as the output of the register 2110, which is used to hold the initial bits in the first packet access or READ signal for subsequent accesses in the package. Register 2110 still reset signal RESET. The inclusion changed from Fig, and the enable signal is generated as the output of the circuit OR to the input REQP, STB, OVR_MODE, TERM and EN_TERM_CNT. The modification consists of adding a signal TERM and EN_TERM_CNT in logic OR. The input signal is taken from the multiplexer 3004 (compared to the multiplexer 2160 on Fig) and is used to select shear values based on the mode, as described in detail below.

Here I use two shift register 3014 and 3016 width of 8 and 2 bits, respectively. 8-bit shift register 3014 remembers the mode bits (01) and SLVE_ID. 2-bit shift register 3016 remembers bit pause bit and READ the reading for the first access mode FTM_MODE or remembers bits READ address bit 7, when there is no mode FTM_MODE. This input is designated as SHIFT2LDVAL, and it is formed as the output of the multiplexer 3028, as described in detail below. 7-bit shift register 3018 remembers the 7 bit address (recall that according to the Protocol SBI use only 7-bit address). Note that the shift registers 3016 and 3018 replace shift register 2130 (shown in Fig), when there is no FTM mode. These three shift register to form a single chain, in which the shift output of the shift register 3018 connected to the shift input of shift register 3016, and shift out shift register 3016 is connected to the shift input of shift register 3014. All three shift register 3014-3108 included signal STB and loaded signal REQP.

Shift register 2140 identical similar case on Fig. Shift register 2140 width SSBI_DATA_WD bit pre-loaded data entry for write operations, or all zeros for read operations. Shear input to the shift register 2140 is defined as the output of multiplexer 2150, which selects 0 when an alarm has been set SSBI_DATA_OE, and the signal SSBI_DATA_IN_DEL, otherwise. Can be made available parallel output shift register V the form of a signal RD_DATA_PRE. Like other shift registers, shift register 2140 load signal REQP and is enabled by signal STB.

Register 3022 added for use in the mode FTM_MODE to remember a bit of pause. Register 3022 reset signal REQP. The last bit of pause mode FTM is not directly stored and shifted in the register 3022 of the shear output shift register 2140.

Because the leader block SSBI supports standard access mode SSBI, as well as FTM mode, to select or skip an extra bit is required to FTM mode, use different multiplexers. In addition, the mode FTM_MODE use additional logic to skip bit mode, the ID of the slave device and a bit of a pause during the second and subsequent accesses in the package according to the signal CONT.

The multiplexer 3020 is used to select output register 3022 as a shift input to shift register 3018, when the mode is set to FTM. Otherwise, the register 3022 is skipped, and selects the output shift register 2140.

The signal SHIFT2LDVAL is created as the output of multiplexer 3028. In FTM mode pick up the signal READ for the formation of 2-bit values. Otherwise, READ for the formation of 2-bit values concatenate with ADDR (7) (as on Fig).

The multiplexer 3010 can be switched by the signal FTM_MODE to skip or include sdvigovogo the register 3014 in the lateral chain. In FTM mode selects the output shift register 3014 without saving proposed discharges. In the mode of not being FTM mode, selects the output shift register 3016. The output of multiplexer 3010 enters the logical element OR 2120 together with REQP, as described in connection with Fig. The output of logic element OR 2120 is a bit stream during normal operation, SSBI and for the first access in FTM mode (excluding the final part of the access, if it is used).

The multiplexer 3006 selects a different bit streams depending on the current mode. Line selection is formed in the form of the coupling TERM and CONT (shown as the TERM&CONT). In SSBI mode signals TERM and CONT is not always installed, so that it selects the output of logic element OR 2120. The output of logic element OR 2120 is also selected in FTM mode to the first access, and in this case, the termination character is not yet sent (signal TERM is not installed), and the current access is not performed (signal CONT is not installed).

Before ending during the second and subsequent accesses will be set signal CONT, so that the multiplexer 3006 selects the output of multiplexer 3012. The multiplexer 3012 is used to FTM mode and can be used to skip bits of the mode ID of the slave device and a bit of a pause during the second and subsequent accesses in the package. When a signal REQP,as the output of multiplexer 3012 READS selected; otherwise, it selects the shift output of the shift register 3018.

Since in this example, the termination character switches with each clock cycle, the termination character is formed by inserting bits of the symbol resolution cycle in the last register 2110, outstanding signal SSBI_DATA_OUT. To identify the send time of the termination character used the TERM signal. This is implemented by feeding the signal NOT CNT_EN in the register 2110, as it switches every cycle (using inversion signal CNT_EN, as this input provides a coincidence in phase of the output register 2110 signal CNT_EN). As described above, the register 2110 is included on each clock cycle by TERM signal in the logic circuit OR the input signal.

In this example, there are two special cases associated with the termination character. First, to prevent the sending of the termination character on the slave can be set signal DISABLE_TERM_SYM. One example use of this feature is to suspend pulses SSBI_CLK for slave by writing the bits of the register slave device, TCXO_DIS, as described above. After recording line SSBI_DATA should not be activated until when will be re-enabled clock pulses for the slave device. After this particularly is about access signal DISABLE_TERM_SYM can be used to block the signal sending NOT CNT_EN in the last register 2110, outstanding signal SSBI_DATA_OUT. Thus, with the inclusion of the TERM multiplexer 3006 selects the output logic functions And inputs NOT CNT_EN and NOT DISABLE_TERM_SYM.

In the second case, the opportunity to send a termination character without any previous access. This is achieved by installing signal SEND_TERM_SYM. This can be useful when, for example, the leader block 1110 is set to the initial state in the middle of shipment. In this situation, to a slave device, SBI is not stuck in an infinite loop FTM, the host device may send a termination character to switch back to the slave device in the idle state. To ensure the implementation of this second opportunity multiplexer 3004 is used to select input register 2110. As Fig, the signal OVR_MODE is used to select OVR_VALUE, allowing direct control of the lateral chain. When the signal OVR_MODE not installed, install the signal EN_TERM_CNT leads to the choice of NOT TERM_CNT(0) as the output of multiplexer 3004. Creating a signal TERM_CNT discussed in detail below. When you do not have any signal OVR_MODE, no signal EN_TERM_CNT, to enter in the register 2110 selects the output of multiplexer 3006.

On Fig shows additional control logic circuit for driving block 1110 SSBI modified to support FTM mode. Compare this example with the example of the m, described in connection with Fig. These logic circuits perform the same functions as the previous option, but with the following modifications.

As before, the signal REQP is formed as the output of the logic circuit And 2204 signal REQ as one of the inputs. For signal REQP is added to the signal is DONE in order to confirm many of the accesses in the package. REQP is recorded in the trigger 2206 to generate a signal ACK. Another entrance to the scheme And 2204 is formed in the form of the output logic circuit OR 3102 to the input STATE, and NOT the other two inputs, which are outputs of logic functions And inputs DONE and FTM_MODE and logical functions And inputs DONE_DELX and NOT FTM_MODE. Compare this logic with logic OR 2202 on Fig.

As before, Segal RD_DATA is formed as the output of the register 2208, which has at its input the signal RD_DATA_PRE. Enclosing element is modified so that it contains an additional element to FTM mode. The enable signal is generated by the circuit And inputs SREAD, NOT STB, NOT RESET and BITCNT=19/26. The expression BITCNT=19/26interpreted as follows: when FTM_MODE = 0, BITCNT = 19; when FTM_MODE = 1, BITCNT = 26.

In FTM mode, a signal is generated DONE using the later signal BITCNT, which does not depend on SREAD as read and write mode FTM occupy the same amount of time. In this example, this is implemented using the cartoon is of plexor 3114. Line selection for multiplexer 3114 is FTM_MODE&SREAD. When an alarm has been set FTM_MODE, at the output of the multiplexer 3114 appears BITCNT=27, if the signal SREAD is not installed, and BITCNT=27otherwise. When not selected signal FTM_MODE and not selected signal SREAD, the output of multiplexer 3114 is formed in the form of a Boolean function with inputs NOT SREAD and BITCNT=(17+IDLE_SYMS). When the signal FTM_MODE is not selected, and the signal SREAD is selected, the output of the multiplexer 3114 is defined as the value of the Boolean functions And inputs SREAD and BITCNT=(19+ IDLESYMS). The DONE signal is generated as the output of the register 3118, which has as its input the output of the logical circuit And 3116 input NOT the STB and the other input being the output of the multiplexer 3114, and this register is reset by the signal RESET.

To create signals CONT and TERM is added to the logic circuit, which outputs all 0 when the signal FTM_MODE equal to 0. The signal CONT is set to one during the same cycle, which has the DONE signal, and is reset to zero when a pulse is formed DONE_DELX_FTM. The signal CONT is formed as the output of the register 3110. Setting this register occurs when bits CNT=27, and the reset signal output circuit OR input DONE_DELX_FTM, RESET and NOT FTM_MODE (DONE_DELX_FTM represented as either DONE_DELX_FTM_WR or DONE_DELX_FTM_RD depending on whether recording or please take the existence. The signal DONE_DELX_FTM_WR set value BITCNT=31+IDKE_SYMS, and the signal DONE_DELX_FTM_RD set value 23+IDLE SYMS).

The TERM signal is used to increase the per unit values BITCNT with each clock cycle during the lifetime of the termination character. The TERM signal is generated as the output of the multiplexer 3150, which uses line SREAD as their line of choice. When a signal SREAD, selected TERM_READ; otherwise, select TERM_WRITE. The signal TERM_READ is formed as the value of the Boolean functions And inputs FTM_MODE, BITCNT>=28and BITCNT<=31. The signal TERM_WRITE is formed as the value of the Boolean functions And inputs FTM_MODE, BITCNT>=27 and BITCNT<=31.

The signal SREAD, STATE, CNT_EN and STB are the same as Fig. The signal SREAD is formed as the output of the register 2210, and READ is input, and REQP the enable signal. STATE is created as the output of the RS-flip-flop 2220. The input set for RS-flip-flop 2220 is formed as the output of the logic circuit 2216 with inputs REQP and NOT RESET. The reset input for RS-flip-flop 2220 is formed as the output of the logic circuit OR 2218 with inputs DONE_DELX and RESET.

Signal STB (denoted as CNT_EN) is formed as an output reset trigger 2224. The input of this trigger is the inversion of its output, so the signal STB, changing with each clock cycle when the trigger is not reset. The reset input CNT_RES is formed as the output of the logic circuit OR 222 with inputs REQP and NOT an integer.

BITCNT (in this example, the 6-bit signal; in alternative embodiments, there may be other settings that require alternative values for all Fig. from 29 to 31) is formed as the output of the counter 3140 (compare with counter 2228 on Fig). The enable signal of the counter 3140 is the output signal of the logic circuit OR 3138 with inputs CNT_EN (or STB) and TERM. In contrast to Fig, in this example, the width BITCNT increased by 1 bit, because if IDLE_SYMS>0 or SSBI_DATA_WD>8, BITCNT can score after the 31. The load value for BITCNT now dependent on whether the access is the first access to the service. CONT, essentially, is used as the line of choice for multiplexer 3112, which when activated, selects the value BITCNT_LDVAL sequence 001010 and sequence 000000; otherwise.

The signal TERM_CNT, which is used for forming the termination character when an alarm has been set SEND_TEND_SYM, as described above, is formed as follows. The signal EN_TERM_CNT is formed as the output of the RS-flip-flop 3144. The input is the signal EN_TERM_CNT when an alarm has been set SEND_TERM_SYM. The signal EN_TERM_CNT removed, when the termination character, as shown by signal TERM_CO. Thus, the reset signal for the flip-flop 3144 is the output of the logic circuit 3142 OR with the RESET inputs and TERM_CO. TERM_CNT in this note is PE is a 2-bit signal, although within the scope of the present invention can be used for other symbols to complete a different size, as well as other forms of signals. The signal TERM_CNT is formed as the output of the counter 3148, whose output signal of the transfer is assigned to the signal TERM_CO. Counter 3148 enabled always except when it is reset by the output logic circuit 3146 OR with inputs RESET and NOT EN_TERM_CNT. Thus, when a signal EN_TERM_CNT is removed and the reset signal for the counter 3148, which causes the counter to count, until the output signal of the transfer TERM_CO, which, in turn, reduces the signal EN_TERM_CNT.

Recall that the leader block 1110 SSBI does not use the ID of the slave device in SSBI mode, although the SBI mode, the IDs of the slave devices may be required. Since the slave device will decode the ID of the slave device, it is necessary that he was asked by a microprocessor or other leading host via the control register or by other methods well known in the art. The ID of the slave device can be displayed in the leader block 1110 SSBI for each transaction. Note that in contrast to the SBI interface, this field can be programmed once and never have to change if port SSBI connected to a single slave device. In addition, the signal TM_MODE determines whether or not to be performed forward in FTM mode that allows you to use the same leader block 1110 SSBI with a truly 1-wire slave devices, and the 1-wire slave devices that use the transducer block interface (SSBI in the SBI interface, such as a block 1420, described in detail below.

Subordinate unit SSBI supporting FTM mode

For a slave device that needs support 3-wire bus 1-wire bus, one approach is to develop a slave unit for storing block 1220 support 3-wire block SBI, as shown in Fig, and adding Converter 1420 SSBI slave unit, which allows him to interact with the 1-wire bus. Block 1420 of the Converter sub-unit can be used to convert the 1-wire transmitting signals to generate signals SBST and SBCK and feed them into the existing circuit 1220 slave 3-wire SBI. Thus, in this example, in 1-wire mode should be used team FTM as team SSBI cannot be correctly interpreted circuits 1220 3-wire slave device. Table 5 describes the ports for the example Converter 1420 SSBI slave.

Table 5
Descriptions of the ports of the Converter sub-unit SSBI
PortDirectionDescription
SSBI_CLKInputHeartbeats
RESETInputAsynchronous input. This unit stretches the signal until it is enabled oscillator
SBST_INInputEntrance SBST from the contact pads of the chip
SBCK_INInputEntrance SBCK from the contact pads of the chip
SSBI_DATAInputEntrance SSBI_DATA/SBDT from the contact pads of the chip
SBST_OUTOutput3-wire signal SBST going to a subordinate unit SBI
SBCK_OUTOutput3-wire signal SBCK going to a subordinate unit SBI
SBDT_PO_INInput3-wire the th signal SBDT, PO coming from a sub-block SBI
SBDT_OE_INInput3-wire signal SBDT, OE, coming from a sub-block SBI
SBDT_PO_OUTOutput3-wire signal SBDT, PO going on a contact pad of the chip
SBDT_OE_OUTOutput3-wire signal SBDT, OE running on a contact pad of the chip
SSBI_MODEOutputSBCK_IN and SBST_IN, indicating that the slave device operates in 1-wire mode
TCXO_DISInputThe signal comes from a block of registers slave device. It is equal to '0' during normal operation and is equal to '1'when SSBI_CLK off
RESET_TCXO_DISOutputThe signal enters the unit registers of the slave device to reset the bits of the register TCXO_DIS

Approximate Converter 1420 SSBI slave unit can be used to convert signals SSBI signals in SBI when working in 1-wire mode or lowering the specified transformation is when working in 3-wire mode. In particular, the Converter sub-unit SSBI, among other things, receives signals from the line SSBI_DATA and generates a signal SBCK and SBST for standard 3-wire slave SBI. In this example, there is no need to create a signal SBDT in the Converter 1420 SSBI slave unit, as it can be directly inserted between the contact pad and a 3-wire slave unit, as described above in connection with Fig.

Inputs SBST and SBCK can be used to determine whether the work in 1-wire or 3-wire mode. 1-wire mode is selected when SBST=1, and SBCK=0, as specified combination never occurs during normal 3-wire transfers. This option to select the mode eliminates the need to have a dedicated pin or register mode selection. If you select 3-wire mode, then the signals SBST and SBCK multiplexed through the outputs of this block, as described in detail below.

1-povodnom mode block 1420 Converter SSBI slave unit checks the line SSBI_DATA the presence of an initial symbol which is used to set signal SBST and start switching signal SBCK. Block 1420 Converter SSBI slave unit also looking for the termination character, which is used to remove signal SBST and termination switch SBCK. Data entries come directly subordinate unit SBI, and read data is returned directly in line SBDT. A sample illustrating these features, described in detail below with reference to Fig-35.

On Fig shows a portion of the transducer 1420 SSBI slave unit. Shows the scheme are responsible for determining whether the mode 1-wire or 3-Provodnik. The signal SSBI_MODE goes to a high level for 1-wire mode, when SBCK=0, while SBST=1, as can be seen from the logic circuit And 3250 with inputs SBST_IN and NOT SBCK_IN. In this example, the signal SSBI_MODE is served as the output signal, when other functions or units operate according to the selected mode. The signal SSBI_MODE is also used to control the multiplexers 3260 and 3270. When working in 3-wire mode, i.e. when the signal SSBI_MODE is not selected, the input pads SBCK and SBST (SBST_IN and SBCK_IN respectively) is selected for output in line SBST_OUT and SBCK_OUT respectively. When working in 1-wire mode, i.e. when an alarm has been set SSBI_MODE, multiplexers 3260 and 3270 select signals SBST_GEN and SBCK_GEN for output on lines SBST_OUT and SBCK_OUT respectively.

RESET_EFF is extended by a reset signal generated in such a way that it lasts for at least two clock cycle. This ensures that Seagal RESET_EFF, in the end, schemes will be noticed, even if the clock pulse is turned off. Asynchronously set the triggers 3220, 3230 and 3240 are set by the outputs of the logic circuit OR 3210 with inputs TCXO_DIS and RESET. The signal RESET_EFF is formed as a trigger output 3240. Input trigger 3240 is the trigger output 3230, whose input is the output of the trigger 3220. Input trigger 3220 is set equal to zero.

In this example, the signal SSBI_DATA should be very similar to the signal SBDT, so timing diagrams of read and write relatively similar regardless of whether we have the transformation SSBI in SBI or not. Consider the example, when the selected data SSBI_DATA and SBDT is generated with a delay of exactly one clock cycle. This will cause the slave unit SBI (i.e., 1220) notice all accesses in one cycle later. For the record, this shouldn't be a problem. However, for reads when data is returned, they will go to one cycle later than waiting for a master device. The result will be necessary to SSBI_DATA moved in SBDT without any delay in registers. Essentially, the next challenge is the detection of the starting character and the timely establishment of the signals SBST and SBCK to negotiate with a time chart of the operation sub-block SBI. This can be quite difficult, because the interval of two symbols (first symbol and the first symbol of the data Converter 1420 SSBI slave unit should perform is resolved as follows: 1) to recognize the initial symbol; 2) initiate the installation SBST (translated into low level); 3) translate SBCK at a low level, and then to provide the possibility of switching, so that the rear front appeared every two clock cycle; 4) falling edge of the second SBCK will be used for sampling SBDT in a sub-block SBI.

Consider an example in which the line SSBI_DATA is in the idle state, and the inverter 1420 slave unit then produces a sample line SSBI_DATA on the leading edge SSBI_CLK until you notice the initial symbol. On Fig shows waveforms at the beginning of the shipment. The start symbol is detected and the signal skips half of the clock cycle, causing the installation of the signal FOUND_ST. It asynchronously forces the signal transfer SBST at a low level, which, in turn, blocks the scheme that searches for the starting character. The signal FOUND_ST is delayed by half a clock cycle, undergoes surgery "And" with yourself, and then used to create the first trailing edge and the leading edge SBCK. Signals SBST and FOUND_ST used together to allow a switch SBCK. Because the slave SBI chooses a character at the trailing edge SBCK, in fact they are selected by 25% of the symbol period.

Note that the pulses SSBI_CLK may not be as smooth, as shown here. What is shown on Fig, is in the ejstitelnosti "ideal" case. In the "worst case" initial symbol not found at once, and detected with a delay of a cycle. In this case, all signals FOUND_ST, SBST, SBCK shifted to the right by 1 clock cycle. Accordingly, the data symbols are selected by 75% in symbol period. As will be clear, in both cases, the signals SBST and SBCK can be formed correctly in relation to SSBI_DATA. The LATE signal similar to the signal with the same name, which was described in detail above in connection with Fig; this signal helps to reduce the specified one cycle variability (SBDT_PO and SBDT_OE) to half of the clock cycle.

Waveforms at the end of shipment shown on Fig. Fixing the termination character in some degree, it can be difficult, because it switches every clock cycle in four consecutive clock cycles. This sample termination character is selected because it has the most abbreviated form, distinguishable from any character data. The approximate scheme used for sampling this signal, mainly selects SSBI_DATA within 4 clock cycles, searches through the template. In parallel, there is a separate circuit, which samples the trailing edge of the clock pulse. This is necessary because, if the leading edge SSBI_CLK aligned with the transitions of the termination character, there is no guarantee that this symbol will be fixed first the scheme. Therefore, by acting together, both schemes guarantee the detection of the termination character.

On Fig shows a portion of the additional schemes for the approximate Converter 1420 SSBI slave unit. Extended reset signal RESET_EFF causes asynchronous signal transition SBST_GEN and SBCK_GEN at a high level. Extended reset signal is used to ensure that it remained at a high level, until you enable signal SSBI_CLK. This reset signal also resets the part of the schema that generates the signal FOUND_T and described below.

SSBI_DATA are detected using SSBI_CLK in the register 3508, which reset signal NOT SBST_GEN. The output of register 3508 is input to register 3510, synchronized by the signal inversion SSBI_CLK and reset signal NOT SBST_GEN. The output of register 3510 designated as FOUND_ST that indicates the detection of the beginning of the shipment.

Data SSBI_DATA also be entered in the register 3502, synchronized by the signal inversion SSBI_CLK. The output of register 3502 is input to the register 3504, the output of which is designated as FOUND_ST_N. Both register 3502 and 3504 are reset signal RESET_EFF. FOUND_ST_N is recorded in the register 3506, a synchronized signal SSBI_CLK, to generate a signal LATE. Register 3506 is enabled by the signal FOUND_ST.

The signal FOUND_ST is used to asynchronously set the trigger 3518, the output of which is inverted (3520) to generate a signal SBST_GEN. Thus, the detected starting the first bit sets (excites low level) signal SBST_GEN. Recall that the signal is NOT SBST_GEN resets the registers 3508 and 3510, which create FOUND_ST, so FOUND_ST remains set until you have completed the current access or accesses and will not be discovered by a new start bit. Trigger 3518 synchronization signal inversion SSBI_CLK and reset signal RESET_EFF. The zero introduced by the signal FOUND_T that indicates the detection of the termination character, as described in detail below.

Register 3522, a reset signal RESET_EFF, perceives the input signal FOUND_ST and delays it for one cycle. Its output, SBCK_EN comes in logic AND-NOT 3524 together with the signal FOUND_ST, which is used to signal SBCK_GEN at a low level through logic And 3526. The other input to logic And 3526 is used to create a signal SBCK_GEN when logic AND-NOT 3524 does not accelerate the transition SBCK_GEN at a low level, and this input signal is supplied from the output of the register 3514. Register 3514 synchronization signal inversion SSBI_CLK and asynchronous set signal RESET_EFF. Its output, in addition to submitting it to the logical schema And 3526, is inverted in the inverter 3516. Its input is generated as the output of the logic circuit OR 3512 with inputs SBST_GEN, FOUND_ST, FOUND_T, and the entrance, which is the output of the inverter 3516. Signals SBCK_EN and FOUND_T used for termination switch SBCK until the signal is removed SBST.

As has been described what about the above, to identify the termination character using two schemes. In each diagram the data SSBI_DATA shifted in two rows of 5 registers 3528-3536 and 3542-3550 respectively. Template termination character is found two logical elements And 3538 and 3552. The first circuit includes a register 3528, synchronized by the signal inversion SSBI_CLK, and registers 3530-3536, synchronized signal SSBI_CLK. Registers 3528, 3530 and 3532 reset asynchronously signal RESET_EFF. Pattern completion is detected by the logic And 3538 from the following input signals: inversion of the output of the register 3530, output register 3532, inversion of the output of the register 3534 and output register 3536. The second circuit has a register 3542, a synchronized signal SSBI_CLK, and registers 3542-3550 that are synchronized to the signal inversion SSBI_CLK. Registers 3542, 3544 and 3546 reset asynchronously signal RESET_EFF. Pattern completion is detected by the logic And 3532 from the following input signals: inversion of the output of the register 3544, output register 3546, inversion of the output of the register 3548 and output register 3550. Logic OR 3540, consisting of two circuits whose inputs are the outputs of the logic circuits 3538 and 3552), generates a signal FOUND_T indicating the detection of the termination character.

Note that the signal FOUND_T may have a length of 1 or 1.5 cycle depending on whether one or both schemes have discovered the termination character. This may limit zmoney speed then passing over the bus. In the present exemplary embodiment, it does not cause any problems. Alternatively, the host device can force the forward line SSBI_DATA character is not occupied by at least one symbol period, if necessary.

Note further that this scheme will not install signal FOUND_T, if not the signal is present is complete. Assuming that the data symbols change every two clock cycle, if the clock cycle is not aligned symbolic transitions, sample character in two consecutive clock cycles will give the same value (not a variable value for the termination character). If the clock pulses of the sample aligned with the fronts of the characters, then it is possible to sample either the previous or new value of the symbol. For example, consider the case when the front of the first sample is aligned with the transition of the symbol, and therefore, is a third front, but not the second and fourth, as those appear in the middle of the symbol. If we bear in mind that the desired combination is 1010, then, that during the second and fourth samples to detect 0, two data symbols must be zero. If so, then the third sample should be equal to 0 because the data has not changed. As a result, the signal FOUND_T will not install. Similar arguments apply to the case where the second and fourth sampling vyrovna the s on the limits of the symbol, while the first and third are not aligned.

Note again that the pulses SSBI_CLK may not be aligned as shown on Fig and 34. These figures actually shows the "ideal" case. In the "worst" case, the termination character is found half clock cycle later. In this case, the signal FOUND_T shifted to the right by half a clock cycle that does not affect SBST or SBCK. As you can see, and in the "ideal"and "worst" cases in the subordinate block SBI receive additional pulses SBCK. It should be expected that the subordinate unit SBI will ignore the additional data bits, as soon as the signal is removed SBST.

The LATE signal is used to modify timing diagram of the output SBDT when operating in mode SSBI_MODE. The signal SBDT_OE_OUT is formed as the output of the multiplexer 3560, which as its inputs uses the signal SBDT_OE_IN and its delayed version, recorded in the register 3558. Register 3558 receives at its input the signal SBDT_OE_IN and delays it for one cycle. The signal SBDT_PO_OUT is formed as the output of the multiplexer 3566, which uses as its inputs the signal SBDT_PO_IN and its delayed version, recorded in the register 3564. Register 3564 receives a signal SBDT_PO_IN and delays it for one cycle. The select signal of the two multiplexers and 3560 3566 is formed in the form of the output logic circuit is WHETHER 3562 to the inputs of LATE and NOT SSBI_MODE. Thus, when there is no mode SSBI_MODE, the signal SBDT_OE_OUT is in SBDT_OE_IN, and the signal SBDT_PO_OUT is in SBDT_PO_IN. The same choice is made when the mode SSBI_MODE, and the LATE signal is not set. When the LATE signal is set in the mode SSBI_MODE, for the corresponding outputs are selected delayed versions of the signals SBDT_OE_IN and SBDT_PO_IN.

The signal RESET_TCXO_DIS is formed as the output of the register 3556 that as input receives the output signal from the register 3554. Register 3554 as its input receives the signal TXCO_DIS. Register 3554 synchronized signal SSBI_DATA. Register 3556 synchronization signal inversion SSBI_DATA. Both registers are reset asynchronously by the RESET signal. Thus, when a signal TCXO_DIS, front SSBI_DATA sets the register 3554, and the next falling edge SSBI_DATA sets the register 3556, resulting in a set signal RESET_TCXO_DIS. Essentially the signal SSBI_DATA can be used to set the alarm RESET_TCXO_DIS, when the clock pulses (i.e., SSBI_CLK and other heartbeats) is locked. In one exemplary embodiment, the signal RESET_TCXO_DIS can be used to unlock one or more types of locked clock pulses.

Additional alternatives

Consider additional options. For example, you will need organizovat the interaction of existing leading devices SBI with more modern slaves SSBI. You can use a Converter 3-wire interface 1-wire, providing reception of signals SBST, SBCK and SBDT and creation on their basis of a single signal SSBI_DATA. The specified Converter can be set in the slave device SSBI, to support the interface of any type without the use of slave SBI, as described in detail above. Alternatively, the specified Converter can be added to an existing host device to interrupt the direct use of 3-wire Protocol and create on its basis a single-wire interface. In other alternative embodiments described converters can be used as a stand-alone component that is outside the master or slave device, any type (SBI or SSBI).

Another option slave device may include interfaces slave as type SBI and type SSBI. To control the line of incoming data (which may be common for SSBI_DATA and SBDT) can be used with a sensor which determines the type of Protocol used in the inbound lines. Alternatively, the slave device may be programmable to select one or the other interface slave (SBI or SSBI). Experts in the art in light of the above is here and principles can easily offer many combinations of 3-wire and 1-wire leading device, slave devices and transducers that can be used within the concept corresponding to the present invention.

Specialists in the art it should be clear that information and signals may be represented using any of a variety of different technologies and methods. For example, data, instructions, commands, information, signals, bits, symbols and signal elements, to which reference was made throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Specialists in the art also should be clear that the various illustrative logical blocks, modules, circuits, and steps of the algorithms described in connection with the disclosures provided here options for implementation may be implemented as electronic hardware, computer software, and combinations thereof. For clarity, this interchangeability of hardware and software, various illustrative component, blocks, modules, circuits, and steps have been described above in General terms of their functionality. By what means hardware or software, you must implement the specified functionality, thevisitor particular application and design constraints imposed on the whole system. Specialists in the art can implement the described functionality in different ways for each particular application, but such decisions on their implementation should not be interpreted in such a way that they can lead to going beyond the scope of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with open options here, can be implemented or performed using a General purpose processor, a digital signal processor (DSP), application of specialized integrated circuits (ASICS), gate arrays, user-programmable (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described here. General-purpose processor may be a microprocessor, but in an alternative embodiment, the processor may be any processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a variety of microprocessors, one or more high performance embedded is sorow in conjunction with a DSP core, or any other specified configuration.

The stages of a method or algorithm described in connection with open options here, can be embodied directly in hardware, in a software module, executable by the processor, or a combination of both. A software module may be located in random access memory (RAM), flash memory, permanent memory (ROM), electrically erasable programmable ROM (EPROM), a non-volatile electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, the ROM on the CD-ROM (CD-ROM) or any other form of storage medium known in the art. An exemplary storage medium connected to the processor so that the processor can read from it and write information. Alternatively, the medium may be integral with the processor. The processor and the storage medium may be located in the integrated circuit ASIC. Integrated circuit ASIC can be located in the user terminal. In an alternative embodiment, the processor and the storage medium may be located in the user terminal as a separate component.

The previous description of the disclosed embodiments the image is placed proposed for to enable specialists in the art to make or use the present invention. Specialists in the art will easily be offered various modifications of these options, as defined here, the fundamental principles can be applied to other variants of implementation, without going beyond being and scope of the invention. Thus, it is assumed that the present invention is not limited to the options shown here implementation, and corresponds to the widest extent consistent with the disclosed here, the principles and new features.

1. The device is configured to communicate with a second device via a single wire bus and/or three-wire bus and contains:
one or more pads;
three-wire bus interface for:
the formation of the gate signal
the formation clock signal and
receiving data for writing to the remote device and delivery data read from the remote device via the first signal in accordance with a strobe signal and a clock signal;
one or more single-wire bus interfaces, each single-wire bus interface is designed to receive data for writing to the remote device and delivery data read from the remote is trojstva through the second signal; and circuitry for summing the first signal to the pad in the first mode and the second summing signal of the first-mentioned one or more single-wire bus interfaces to the pad in the second mode.

2. The device according to claim 1, additionally containing circuitry for summing gate signal to the pad in the first mode and the second summing signal of the second of the above-mentioned one or more single-wire bus interfaces to the pad in the second mode.

3. The device according to claim 1, additionally containing circuitry for summing the clock signal to the pad in the first mode and the second summing signal of the second of the above-mentioned one or more single-wire bus interfaces to the pad in the second mode.

4. The device is configured to communicate with a second device via a single wire bus or a three-wire bus, containing a clock input;
the gate input;
one-wire bus;
a single-wire bus interface connected to a single-wire bus, for receiving and transmitting over a single-wire bus in the first mode;
three-wire bus interface for receiving the second mode clock input and a gate input for connection to a single-wire bus for transmission and reception over a single-wire W is not, include the gate entrance, and in accordance with a clock input;
the tool of choice for guidance on when the device is in the first mode or the second mode.

5. The device according to claim 4, in which the selector is programmed to operate in the first mode or the second mode.

6. The device according to claim 4, in which the selector indicates the second mode, if the clock input has a first predetermined value, and the gate input of the second predetermined value.

7. The device according to claim 6, in which the first predetermined value is low voltage and the second predetermined value is determined by a high voltage.

8. The device is configured to communicate with a second device via a single wire bus, comprising:
the means of excitation for excitation of a single-wire bus service access access pack contains:
the initial symbol;
one or more characters mode;
one or more characters indicating the device ID;
one or more of the accesses and the termination character;
this contains a frame read or write, but a means of excitation frees one-wire bus during pauses and to return the data characters are read.

9. The device according to claim 8, in which the package is DOS the UPA contains the character pause before one or more accesses.

10. The device according to claim 8, further containing a clock generator for generating a clock signal with a clock period, and each symbol contains two or more clock periods, and the termination character contains a sequence of two or more alternate values, the values are interleaved in each clock period.

11. The device according to claim 10, in which the complete sequence is given as "1010", where 1 indicates a high voltage, and a 0 indicates low voltage.

12. The device according to claim 8, in which the reading frame contains the character read indicator, one or more symbols indicating an address of the first pause character, one or more temporary character segments to return the data read in accordance with the address and a second pause symbol.

13. The device according to claim 8, in which the frame entry contains the character recording indicator, one or more symbols indicating an address of the first pause character, one or more characters account for storage in accordance with the address and a second pause symbol.

14. The device is configured to communicate with a second device via a single wire bus, comprising:
the first circuit to receive signals over a single-wire bus and forming from it a strobe signal and the clock signal.

15. The device according to 14, more is tion containing a three-wire bus interface for receiving the gate signal and the clock signal and a three-wire bus and implemented in response to the receiving communication with the second device.

16. The device according to 14, further comprising:
the gate input;
clock input and
a second circuit for selecting the gate signal of the first circuits and the clock signal of the first schemes in the first mode, and to select the gate input and the clock input in the second mode for forming the gate signal and the clock signal respectively.

17. The device according to 14, in which the gate input is held at a high level and the clock input is held at a low level to indicate the first mode, and otherwise indicates a second mode.

18. The method of signal processing when converting a single-wire bus wire bus, comprising:
the signal on the single wire bus;
the detection of the starting character in the input.
the establishment of a Gating signal in response to a detected initial symbol;
the detection of the termination character, and
deactivation Gating signal in response to the detected termination character.

19. The method according to p, optionally containing formation clock signal and the clock signal contains periodic pulses, when a gate signal, and maintains a constant level when the gate signal is disabled.

20. Way to interact with a three-wire bus interface, contains:
the selection gate in the ode, clock input and a single-wire bus for connection to a three-wire bus interface in the first mode;
forming gate and clock signals with regard to a single-wire bus in the second mode, and
the choice of the formed gate and clock signals and a single-wire bus for connection to a three-wire bus interface in the second mode.

21. The method according to claim 20, additionally containing the operation in the second mode, when the gate input is high and the clock input is low, and the operation in the first mode otherwise.

22. The way of communication over a single-wire bus, comprising:
the transmission start symbol;
the transfer of one or more characters mode;
the transfer of one or more characters indicating the device ID;
the transfer of one or several accesses, and access can be access to read or write,
for each access:
the transfer of one or more characters of data for a write access, reception of one or more characters of data access for reading and
transfer termination character.

23. The way of communication over a single-wire bus, comprising:
the initial symbol;
receiving one or more characters mode;
receiving one or more which of ingelow, specifies the device ID;
receiving one or more accesses, and access can be access to read or write,
for each access:
receiving one or more characters of data for a write access, the transfer of one or more characters of data for access to read and receive termination character.

24. A device for signal processing when converting a single-wire bus wire and containing:
means for receiving signals on a single wire bus;
means for detecting the initial symbol in the signal;
means for establishing a Gating signal in response to a detected initial symbol;
means for detecting termination character in the signal and
means for deactivation Gating signal in response to the detected termination character.

25. The device is made with the possibility of interaction with a three-wire bus interface and contains:
means for selecting the gate input, clock input and a single-wire bus for connection to a three-wire bus interface in the first mode;
the means for forming the gate and clock signals in response to the fact that the one-wire bus is in the second mode; and
means for selecting the generated strobe and clock signals and agnoprotein for connection to a three-wire bus interface in the second mode.

26. The device is configured to communicate over a single-wire bus and contains:
means for transmitting the starting character;
means for transmitting one or more symbols mode;
means for transmitting one or more symbols indicating the device ID;
means for transmitting and receiving one or more accesses, and access can be access to read or write, with this tool:
transmits one or more data characters for write access and accepts one or more characters of data access for reading; and
means for transmitting the termination character.

27. The device is configured to communicate over a single-wire bus and contains:
means for receiving the starting character;
means for receiving one or more characters mode;
means for receiving one or more characters indicating the device ID;
means for receiving one or more accesses, and access can be access to read or write;
means for receiving one or more characters of data for write access;
means for transmitting one or more data symbols to access the reading and
means for receiving the termination character.

28. Machinesit is emy media designed to perform the following steps:
the signal on the single wire bus;
the detection of the starting character in the input.
the establishment of a Gating signal in response to a detected initial symbol;
the detection of the termination character, and
deactivation Gating signal in response to the detected termination character.

29. Machine-readable media on p, additionally intended for forming the clock signal and the clock signal contains periodic pulses when the gate signal is selected, and maintains a constant level when the gate signal is disabled.

30. Machine-readable carrier, for performing the following steps:
the selection gate input, clock input and a single-wire bus for connection to a three-wire bus interface in the first mode;
forming gate and clock signals in response to the fact that the one-wire bus is in the second mode; and
the choice of the formed gate and clock signals and a single-wire bus for connection to a three-wire bus interface in the second mode.

31. Machine-readable carrier, for performing the following steps:
the transmission start symbol;
the transfer of one or more characters mode;
the transfer of one Il is the number of characters specifies the device ID;
the transfer of one or several accesses, and access can be access to read or write,
for each access:
the transfer of one or more characters of data for a write access, reception of one or more characters of data access for reading and
transfer termination character.

32. Machine-readable carrier, for performing the following steps:
the initial symbol;
receiving one or more characters mode;
receiving one or more characters indicating the device ID;
receiving one or more accesses, and access can be access to read or write,
for each access:
receiving one or more characters of data for a write access, the transfer of one or more characters of data for access to read and receive termination character.



 

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