Storage device and leading device

FIELD: physics, computer facilities.

SUBSTANCE: invention concerns a storage device and to the leading device using this storage device. The storage device contains semiconductor storage, the controller which is carrying out the instruction for data recording in semiconductor storage according to inquiry which accepts the controller, and the register provided in the controller and retaining the information of a class of speed, showing one of classes of speed classified on speed, and mentioned one of speed classes specifies, that the storage device provides a guaranteed minimum of speed designated mentioned by one of speed classes, thus the storage device is executed with possibility of delivery the information of a class of speed in reply to the instruction, exterior in relation to a storage device.

EFFECT: obtaining of possibility of predicting of of a storage device speed.

14 cl, 24 dwg

 

This application is based on and claims priority to applications for the grant of the Japan patent No. 2004-204028 registered on 12 July 2004, and No. 2004-342275, registered on November 26, 2004, the full content of which is included in the materials of the present application by reference.

The technical FIELD TO WHICH the INVENTION RELATES.

The present invention relates to a storage device and a host device (electronic device)that uses the storage device. In particular, the present invention relates to a storage device, such as a nonvolatile semiconductor memory device and the memory card it uses. The present invention also relates to an electronic device, such as a recordable device; for example, a digital camera and a digital camera contains a built-in storage device. For example, a storage device such as flash memory, universal serial bus (USB), and an electronic device, such as a personal computer (PC, PC) and personal digital assistant (PDA), included in the category of the present invention.

The LEVEL of TECHNOLOGY

In recent years, a memory card containing the embedded non-volatile semiconductor memory, came into wide use as a storage device, storing the various types of digital information, such as image data and music data. Data non-volatile semiconductor memory are beyond the risk of loss, even if turns off the power source, and are rewritable. NAND flash™ often used as a nonvolatile memory (for example, see the publication No. 2003-30993 KOKAI patent application for the grant of a patent in Japan).

In recent times the memory capacity of the flash memory has increased due to advances in semiconductor manufacturing technology.

For example, a storage device such as memory card, containing built-in flash memory, is used by the master device. In this case, the host device directly controls the flash memory, built-in storage device in normal conditions. So, the host device perceives the time of programming the flash memory and programming time, can to some extent predict the memory speed and the allowable storage time.

However, at the present time is often the case, when the storage device has a built-in controller; for this reason, management has become complicated. As a result, it is impossible to predict the memory speed using a simple calculation. Setting the baud rate of the bus connecting the host device and the storage device, the op is Adelaide. However, it is not a real speed when the host device writes data in the storage device. For this reason, the transmission speed does not work as a means of identification performance.

In order to predict the performance of the storage device that includes the NAND flash™requires the calculation in combination with the method of block processing by master device. For this reason, it is difficult to determine the performance using only the mass storage device.

Accordingly, it is desirable to provide an electronic device, which can in a simple way, to some extent, to predict the performance of the storage device, even if the storage device of large capacity is controlled by the controller, and a method for predicting the performance and mass storage device.

DISCLOSURE of INVENTIONS

According to the first aspect of the present invention, provided is a storage device, comprising: a semiconductor memory that stores data; a controller that executes instructions to write data in the semiconductor memory in accordance with the request, which the controller receives; and a register that holds the information of the class, showing a single class, is required to provide is awiti storage device the opportunity to demonstrate the best performance, which supports mass storage device, class performance, defined in accordance with performance.

According to the second aspect of the present invention, is provided a master device that reads data from a storage device that stores data and information class, showing a single class, is required to provide a storage device with an opportunity to demonstrate the best performance that the storage device supports, from the classes of performance defined in accordance with the performance, the host device writes data in a storage device, a single class, is required to provide the host device to demonstrate the best performance, which supports a master device, of the class performance, which is set for the master.

BRIEF DESCRIPTION of DRAWINGS

1 is a block diagram showing the configuration of a NAND flash™ according to the first variant implementation of the present invention;

2 is a block diagram showing the configuration of a storage device containing a built-in memory on the first version of the implementation, and the host device using the storage device;

figure 3 - view for the German division of the space of the storage device, the proposed master device in the first embodiment, and the actual division of the space in the storage device;

4 is a view for explaining the movement of data in the first embodiment;

5 is a view to explain the temporal characteristics of the write operation when using the multi-account;

6 is a view showing an example of the performance curve in the first embodiment;

Fig.7 is a view for explaining the update of the file system while recording in real time in the first embodiment;

figs 8A through 8C is a view showing the sequence of accounts;

Fig.9 is a perspective view showing the external appearance of the host device and storage device according to the first variant of implementation;

figure 10 is a view showing the classification performance curves in the first embodiment;

11 is a table showing the required characteristics maps each class;

Fig is a table showing the measurement conditions required characteristics maps each class;

Fig is a view showing the content stored in the register SD memory card™;

Fig is a view showing the classification of AU relative to the area of the memory card in the first variant implementation of the ia;

Fig view to explain the principle of the host buffer in the first embodiment;

Fig is a view showing the case where all the EN are collected in the front position of the AU;

Fig is a view showing the configuration of a memory card according to the second variant of implementation of the present invention;

Fig - table to explain the distribution of signals on the signal contacts in the memory card according to the second variant of implementation;

Fig block diagram showing the hardware configuration of the memory card according to the second variant of implementation;

Fig block diagram showing the configuration register of the memory card according to the second variant of implementation;

Fig is a view showing the configuration of a memory cell and a buffer in the memory card according to the second variant of implementation; and

Fig - table to explain the distribution of the signals relative to the signal contacts of the SD bus in various operating modes.

The IMPLEMENTATION of the INVENTION

Embodiments of the present invention will be described below with reference to the accompanying drawings. These embodiments of do not limit the present invention.

(The first version of the implementation)

The first variant of implementation relates to a storage device containing built the Noah nonvolatile semiconductor storage device, and to the master device using the storage device.

[1] the Configuration of the storage device and the host device

In the following description NAND flash™ used as a nonvolatile semiconductor memory device, built-in storage device used for driving the device according to the first variant implementation of the present invention.

1 is a block diagram showing the configuration of a semiconductor memory device (semiconductor memory) in case of realization of the semiconductor memory device according to the first variant implementation using NAND flash™.

Figure 1 number 11 references denotes the matrix of memory cells. The matrix 11 of memory cells are equipped with multiple numeric lines, lines, Gating the sample and bit lines (not shown). Some numeric lines and bit lines connected to multiple memory cells (not shown). Multiple memory cells are divided into several blocks, as described later.

The matrix 11 of memory cells connected to the circuit 12 of the fixation data and the decoder circuit 13 rows. Scheme 12 of the fixation data contains a large number of circuits-latches. Scheme 13 row decoder selectively excites some numeric lines Gating selection is key.

Scheme 12 of the fixation data temporarily holds data read via the bit line when reading data from a matrix 11 of memory cells. Scheme 12 of the fixation data temporarily holds write data when writing data with respect to the matrix 11 of memory cells, and then delivers them in a matrix 11 of memory cells through the bit line.

Scheme 12 of the fixation data attached to the buffer 14 input/output buffer I/O) and figure 15 of decoder columns. When reading data, the read data held in the circuit 12 of the fixation data, i.e. only the selected data is read out of the semiconductor storage device with, and in accordance with the output signal of the circuit 15 of decoder columns. When you write data write data supplied from outside the semiconductor storage device via the buffer 14 I/o, fixed circuit-latch circuit 12 of the fixation data, which is selected in accordance with the output signal of the circuit 15 of decoder columns.

Scheme 13 row decoder selectively excites mentioned line number of the line and Gating of the sample, are included in the matrix 11 of memory cells when reading and writing data. In this manner, the memory cells corresponding to one page of a matrix 11 of memory cells are selected simultaneously.

Latch 16 address latches an input address signal, and then supplies and the RES line to the decoder circuit 13 rows along with the filing of the address column in scheme 15 of decoder columns.

The latch 17 command accepts input commands. The latch 17 of the team attached to the decoder 18 teams. The decoder 18 decodes commands command to output various control signals. On the basis of control signals output from the decoder 18 teams, managed the operation of the circuit 12 of the fixation data, schema 13 decoder row buffer 14 input/output circuit 15 of the column decoder and latch 16 address.

In NAND flash™ latch address latch command is attached to the buffer 14 I/o (not shown). Thus, the address and command are served with input/output pin of NAND flash™.

Semiconductor memory device provided with a circuit of the generator high voltage and intermediate voltage (not shown), in addition to these schemes. The circuit of the generator high voltage and intermediate voltage generates a high voltage and intermediate voltage supplied to the decoder circuit 13 rows and the matrix 11 of the memory cells when writing and erasing data.

Figure 2 shows a storage device into which the memory of figure 1, and the host device using the storage device. Storage device 19 is a memory card such as an SD memory card™. Explanation of use case SD memory card™ will be given later.

As shown in IG, flash memory (i.e. the space 21 memory figure 2) and a controller 22 for controlling flash memory built-in memory card. Flash memory has the configuration shown in figure 1.

The controller device 22 includes a register 23 version information, the register 24 identifying code performance and the register 25 parameter performance. The register 23 version information holds version information. Version information is used to identify the version of the memory card. The register 24 identifying code performance holds the identification code performance. The identification code performance is used to identify the group's performance (class). Register 25 performance parameter holds the performance parameter (described later) of the storage device.

When the storage device 19 is attached to the host device 20, the host device 20 controls embedded master controller 26 using the built-in processor 28 for performing communication with the storage device 19.

In order to send data from the host device 20, the data is temporarily recorded in the host buffer (buffer memory) 27, and then sent to the storage device 19 via the drive controller 26. In this case, the leading buffer 27 may to some extent dampfer is to change the performance of the storage device in dependence on time.

Leading the buffer 27 can be implemented using portions of system memory 29. In this manner there is no need of providing a special memory, such as a leading buffer 27, and, in addition, is effective to reserve it in system memory 29, as they usually require a large leading the buffer 27.

The host device 20 can record data using one-time team of multi-unit recordings (i.e. commands to write multiple contiguous blocks using a single write command).

[2] the Definition of performance standards map

The storage device 19 holds the class that corresponds to their own performance and various information of the performance options, so that the host device 20 can know the performance of the storage device 19. The definition of performance parameter will be explained below. In the following explanation, the memory card, including SD memory card™, is given as an example of the storage device 19.

Performance data from the host device 20 in a storage device (memory card) 19 accepted as transfer speed bus 30 control. In this case, the tire 30 of the control corresponds to the thick arrow in both directions connecting the master controller 26 and con the roller 22 of the device in figure 2. The baud rate is set under the assumption that a master device writes to an optimal state.

[2-1] the definition of the performance curve

[2-1-1] the Division of memory space

First, below will be explained the division of the memory space of the master device 20 and the storage device 19. Because it is necessary to explain the performance curve used to define the class.

The host device 20 divides the space 21 of the memory elements requiring entry element (EN) 16 kilobytes for recording data such as video data, for each RU. More precisely, RU (space writer) is equivalent to the item, recorded by a single team of multi-unit recording.

For example, RU is the same as the cluster defined by the file system SD™or has a size of integer multiples of the quantities of the cluster.

Element EN can be specified as 32 KB, 64 KB, 128 KB, etc. As described later, the host device 20 counts the number of RU, allowing the write data, and thus can calculate the remaining recording time.

Figure 3 shows the division of the space 21 of the memory, the estimated master device 20 and the actual division of the space 21 of the memory according to the map 19 memory. The left side of figure 3 corresponds to the division of the space 21 of the memory, alleged the master device 20. On the other hand, the right side of figure 3 corresponds to the actual division of the space 21 of the memory device 19 memory.

As can be seen from figure 3, EN 32 is a memory element, as viewed from the host device 20. Item 31 selection (AU) is defined as a set of several EN 32. AU (area control) is a control and is defined as the element that is used to divide the entire space 21 of the memory storage device 19 on the size of SAUAU.

The relationship between EN 32 and AU 31 like the relationship between page 34 and the block 33 when considering the space 21 from the memory storage device 19 (controller 22). Page 34 is an element of access, when the controller device 22 performs recording or reading with respect to the space 21 of the memory. Unit 33 consists of several pages 34 and is used as the element when the controller 22 of the device erases the space 21 of the memory.

For example, if the NAND flash™ TC58512FT, manufactured by Toshiba Corporation, it is used as a space 21 of the memory page size 34 is 512 bytes, and the size of the block 33 is 16 kilobytes. (In this case, the excess capacity is ignored for simplicity). NAND flash™whose page size is 2 Kbytes or 4 Kbytes, can also be used.

Page 34 RU 32 do not need to match each other. EN 32 can be set to integer multiples of the number of pages 34. In this way the size of SAUAU is an integer multiple of the number of RU size. AU 31 can be set to integer multiples of the block 33. In the subsequent provides an explanation of the use of EN 32 and AU 31 as a main element.

[2-1-2] How to determine performance curve

Curve speed will be described below with reference to figure 4, representing the following case as an example. Namely, the host device 20 successively writes the data element EN from position a to position in space 21 of the memory.

Typically the area from a to b corresponds AU 31. In the subsequent description of the data newly written to the AU, including EN 31 as an example. As shown in figure 4, the logical address AU 31 is set as LA. When data is newly recorded in each RU AU 31 32 actually requires the following steps. First, the data in EN 32 (shown by "Busy" on figure 4), which retains data in the existing physical block PAA, written in EN another physical block PAB. Then it should be written to the new data record. In this case, the physical block PAB is displayed again on the logical address LA.

Time a new data record in EN 32 (shown by "Free" in figure 4), which initially does not hold data corresponds to the time the new account. The recording time is defined as the performance Pw entry.

On the other hand, when the already written data is copied to another EN 32, the time taken to read the data from the old EN 32 (for example, EN 32a), in addition to recording time data in the RU32 (for example, EN 32b) of the new physical block PAB.

When there is a busy EN 32 in the old physical block PAA occupied EN 32 is skipped, and the data is written into the free EN 32 (for example, RU "Data 3"). Data in the busy EN 32 must enroll in EN 32 (for example, EN 32b) destination before the recorded new data. Writes the new data is stopped while data is moved in the busy EN 32. The time spent on the operation, is defined as the performance of Pm data movement. Thus, the total time spent on writing new data, is the sum of the total recording time and total time of the move.

In the preceding explanation, when the average speed of the P(Nu) is expressed by the formula, we get the following mathematical expression 1.

[Mathematical expression 1]

Average performance:

P(Nu) = [Sc × (Nt - Nu)] / [Sc × (Nt - Nu) / Pw + Sc × Nu/Pm] = [(Nt - Nu) × Pm × Pw] / [(Nt - Nu) × Pm + Nu × Pw],

where

Sc: RU size,

Nt: total number of RU, successively recorded from a to B (the number of RU, forming AU),

Nu: the Number of employees between EN and the (number of employees RU, included in AU),

Pw: Performance record (unit: MB/s)

Pm: the Speed of movement (unit: MB/s)

The above mathematical expression is defined under the assumption that performance is determined using the Pw performance record and performance Pm move.

Performance Pw account varies with time programming card 19 memory (flash memory [space 21 memory]). Moreover, the performance of the Pw entry is defined as the smallest value of the average values of the performance, when recording is performed continuously in all EN 32 AU 31, which consists of three EN 32.

Note that the performance record varies depending on the time sequence of operations, spent a client part. The time sequence of operations of the client part depends on the clock frequency set by the SD card™, as an example. This subject will be described below. 5 is a view showing timing characteristics write operation, when used as a team of multi-unit recordings. At the first stage of a write operation, the server part is waiting up until these records are not received from the client side. In the second stage, the server part is driven together with the client part. Therefore, the recording time, RA is houenou on multi-unit recording, should be considered regardless of the client part and server part. In the second stage, the recording time is the server part dominates the recording time compared to the time sequence of operations of the client part.

Time tWBwrite the server part is the amount of time until until you have finished all the recording, after the recording has been started in flash memory (space 21 memory).

On the other hand, the time tWFthe sequence of operations of the client part is the amount of time a team of multi-unit recording before recording to flash memory. As described above, if in the example given SD memory card™, tWFthe sequence of operations of the client part depends on the clock frequency SD. Therefore, the time tWFthe sequence of operations of the client part is expressed using a ratio of CSDand the clock frequency fSDthe SD. Thus, the time tWFthe sequence of operations of the client part is expressed using the following mathematical expression 2 in the SD card™.

[Mathematical expression 2]

The time sequence of operations of the client part:

tWF= CSD/ fSD.

If data is written to one AU 31, the time tWFthe sequence of operations of the client part is proportional number is the number of write commands. The number of write commands is equal to the number of NENEN 32. If the number of NENincreases, i.e., the size SENEN becomes low, the speed of recording is reduced.

Performance Pm move is defined as the smallest value of the average speed of movement. Performance Pm move is calculated as the average value when the continuous RU 32 are moved to form one complete AU 31. Time travel is determined on the server side part and is not under the influence of the clock frequency SD. If the card 19 memory does not need to move EN 32, performance Pm move is defined as being infinite. This is expressed as "1 / Pm = 0".

Moreover, performance Pm displacement varies depending on the time of reading, described later, and move data in addition to the time of programming the flash memory. In this case, the data movement is performed within the card 19 memory; therefore, the host device 20 does not control the movement of data directly.

These two values are determined, when considering the performance of the reader.

1) the Speed of reading the data

Speed reading in relation to the data (hereinafter indicated by reference as speed reading) Pr is defined as the least of these is about the values of the average read performance data among elements of EN 32 randomly. The average value can be calculated based on the 256-fold random readings among the elements EN 32. Moreover, the worst case must be considered in the time spent for remediation using a code with error correction (ECC) with respect to each block 33. Performance Pr reading should be greater than or at least equal to the performance of the Pw entry.

2) read the file system (FAT)

Reading time TFR(4 Kbytes) file system, such as a file allocation table (FAT), defined as the maximum time when reading FAT in 4 KB. In this case, the reading of the FAT should be possible during the recording of AU. This is because, considering the case of recording in real time, the host device 20 should read the FAT between records AU. Moreover, the worst case must be considered in the time spent for remediation using a code with error correction (ECC) with respect to each block 33. Read FAT relative to the size of the file system (size FR) SFRexpressed using the functions CEIL, as set forth below.

Read FAT in relation to the size of SFR[KB]:

[x] represents the CEIL function, which converts a decimal fraction x to the smallest integer less than or equal to x.

6 shows the performance of the card 19 memory calculated according to mathematical expression 1. Figure 6 shows the performance when the number Nt EN 32, forming AU 31, is set as 16.

As can be seen from Fig.6, the performance (vertical axis) is determined for each share of employed EN (horizontal axis). Then the performance for each share of r employed EN are connected and thereby obtained curve performance. Curve performance is important information for manufacturers of leading edge devices.

Curve performance is specified using the Pw performance record and performance Pm move. Performance Pw record is full speed when the proportion r = 0 employed EN.

The share of r employed EN is expressed as the following mathematical expression using the number Nt EN 32 of AU 31 and the number of Nu-employed EN 32.

r = Nu / Nt

This equation is also expressed as set forth below.

Nu = r × Nt

The share of r employed EN varies in the range from 0 to 1. When r = 0, this means that all EN 32 unoccupied. On the other hand, when r = 1, this means that all EN 32 are employed, that is, the speed is 0; in other words, the set P(1) = 0.

You can see that any performance curves pass through the point (1, 0). When you write a mathematical expression 1 using the "r" produces the following mathematical expression 3.

[Mat is political expression 3]

Curve average performance:

P(r) = [(1 - r) × Pw × Pm] / [r × Pw + (1 - r) × Pm],

where 0 ≤ r ≤ 1.

Performance is shown graphically using expression 3, and thereby the obtained performance curve shown in Fig.6.

[2-1-3] the Position of the area of memory and accuracy performance

If the starting address of the write data EN 32 is not a boundary of the block 33 space 21 of the memory required next time. More precisely, the time to move the recorded data is required so that the initial position of the record corresponds to the boundary of block 33. For this reason, in this case, the actual performance is worse compared to the expected performance. In order to measure the exact performance you need to meet the requirements that addresses a and b correspond to the element boundary erase (block 33). Setting item selection follows from the reasons described above.

[2-2] the Parameter related to the update of the file system during recording

Upgrade the file system is inserted in the record sequence, and thus the total (actually received) performance record decreases. For this reason, the host device 20 requires the parameters related to the update of the file system, when calculating the performance of the card 19 memory, as described later. The host device the TWT 20 may expect a decline in the actual performance by influencing those the update file system inserted in the record sequence.

Fig.7 shows a typical sequence of update of the file system while recording in real time. In the following description of the FAT is used as a typical example of the file system.

Upgrade the file system (FAT)may occur after any record EN 32. FAT is updated periodically. The number of EN 32, recorded between specific update file system and the next update of the file system specified period of TFUupdate the file system. The number of EN 32, recorded between updates of the file system is Nd.

Loop recording FAT contains three write operations. 7 FAT1 and FAT2 symbolize the information recording FAT, respectively, in FAT1 and FAT2, using the same team of multi-unit recordings. Write file system (FAT) can begin to address arbitrary bytes and can be defined as records that are in the range from 16 kilobytes to an arbitrary length.

7 DIR refers to the directory item. DIR is formed before recording, and recording is performed only in a portion of the 512 bytes that contains the catalog item of currency. Time TFWwrite file system is defined as a complete cycle time write file system, i.e. the total recording time FAT1, FAT2 and DIR. Time TFWwrite the file the new system varies depending on the technical conditions of the controller 22 of the device.

[2-2-1] the measurement Conditions of the average value of time TFWwrite file system

Time TFWwrite file system is defined as the value obtained from the average of several measured values. Subsequent mathematical expression 4 is used to set the average time TFW(ave.) write file system. As can be seen from the subsequent mathematical expression 4, the worst value of the average values of arbitrary vosmerikova writes file system is used as a secondary recording time file system TFW(ave.).

[Mathematical expression 4]

The average recording time of the file system:

(TFW(ave.)) = [max (TFW(1) + TFW(2) + ... TFW(7) + TFW(8))] / 8.

[2-2-2] Maximum recording time of the file system

As described later, the host device 20 temporarily holds data using the host buffer 27 during the update of the file system. Thus, the maximum period of update of the file system must be taken into account when determining the minimum size of the host buffer 27. Requirements for the size of the host buffer 27 will be explained in the following [4-5].

The following mathematical expression 5 is used to set the worst values recording time of the file system (FAT).

[Mathematical expression 5]

N is audree value recording time of the file system (FAT): (T FW(max) ≤ 750 [MS].

[2-2-3], the Independence of the write data and write file system

Write file system can be inserted between the RU or AU for recording in real time. The controller 22 of the device must be able to exercise control without affecting the performance of the Pw record the data.

The impact of recording the file system on the performance of the Pw entry can be eliminated as follows. More precisely, recording resumes after interruption of the recording by the recording of the file system is performed with the physical realm, following the one in which data is written last before the interruption.

In order to implement the control may be a data block cache for file system entries, and the controller 22 of the device can control, as described below. As shown in figa, the space 21 of the memory includes a normal physical block and the data block of the cache. When recording the file system is requested during sequential write continuous data in a normal physical block, as shown in figa, information management files in a row is recorded in the spare area (page 34) block data cache, as shown in figv. After that, as can be seen from figs, data recording is resumed from the field (page 34), following the one in which data is written is the last one before the interruption.

When the recording is interrupted data recording resumed in the physical realm, which is not following the physical area (e.g., area in the new unit or unit 2), in which data is written last before resuming, like the prior art, is related entry data movement. As a result, the performance of the Pw account changes due to file system entries.

The study addresses, size, and sequence allows to classify normal data and information management files.

[3] Classification of memory card

So without delay, and to compare the performance of the card 19 memory and performance required by the master device 20, the card 19 memory is classified into several classes (class performance) in accordance with the speed of the card. The class can be classified in accordance with the parameters of performance, such as performance curve described earlier, and the time TFW. A device controller holds information about the class as a code 24 identification performance card 19 memory.

Card 19 memory displays its own class, respectively. Figure 9 shows a label that displays the identification of the class. Fig.9 shows the case where the device 19 storage card is PA is ATI SD™ .

As can be seen from Fig.9, the card 19 memory has a body 71 and a tag 72 to show the class on the housing 71. The housing 71 at least partially covers the space 21 of the memory and the controller 22 of the device.

Moreover, the host device 20 has a predefined class. Class on the master device 20 is, what is the best speed it can demonstrate, when it uses the card 19 memory with the same class as the master device 20. The host device 20 may record information when it uses the card 19 memory lower class, although its performance is not the best. Fig.9 shows that the housing 73 of the host device 20 has a label 74, showing his class on it. The host device is not necessarily to show his class.

[3-1] the Requirement from the application

The application in the host device 20 requires high performance from the card 19 memory used by the application. Typical examples will be described below.

(1) Digital video recording

In MPEG2 and JPEG motion requires direct entry in map 19 memory. The performance of the card about 2 MB/s is required in order to get the quality and resolution of a standard television image. The performance of the card is approximately 4 MB/s you want to record high quality images./p>

(2) a Digital camera having a continuous shooting

Manufacturers of digital cameras require card 19 memory with high performance in order to realize the function of continuous shooting. Manufacturers of digital cameras can use the speed of the card and the control method of the host device to calculate a user-available speed continuous shooting.

[3-2] Classification

Figure 10 is a graph to explain the relationship between the curve of speed and class. Figure 10 there are three areas, separated by two performance curves. As can be seen from figure 10, the area formed by the vertical axis P(r) and the horizontal axis r, is divided into three areas curves performance class 2 and class 4.The vertical axis P(r) represents the speed, and the horizontal axis, r is the proportion of employed EN.

Traditional memory cards belong to the region, lower in relation to the origin of coordinates, among the three regions, i.e. class 0 (the map area class 0 figure 10). Figure 10 region includes a memory card that has the lowest performance.

Curve performance class 2 assumes the low performance card class 2. This performance curve is specified by two parameters Pw1 (the intersection curve performance class 2 and the Y-axis) and Pm1.

Similarly distorting what I performance class 4 assumes the low performance card class 4. This performance curve is specified by two parameters Pw2 (intersection curve speed class 4 and the Y-axis) and Pm2.

When the application generates additional increased requirement should be specified performance curves of class 8, class 10, with a higher level. However, there is no need to change the principle. If defined curve performance class 8, scope of class 6 is a region indicating a higher speed than the curve speed class 6 and lower than the performance curve of class 8. Area of class 8 covers an area indicating a higher performance than the performance curve of class 8.

11 is a table showing the specifications for each card class. The parameters required for the card class 2 (Class 2), class 4 (Class 4 and class 6 (Class 6), are as set forth below and as shown in figure 11.

Class 2: Pw = 2[MB/s], Pm = 1[MB/s], Pr = 2[MB/sec]

Class 4: Pw = 4[MB/s], Pm = 2[MB/s], Pr = 4[MB/sec]

Class 6: Pw = 6[MB/s], Pm = 3[MB/s], Pr = 6[MB/s].

Average time TFW(ave.) write file system, the maximum time TFW(max) write file system and reading time TFR(4 Kbytes) file system are the same parameter in each class; for example, 100 [MS]750 [MS] and 4 [MS], respectively.

According to the parameters, while the data of figure 11, curve speed card class 2 intersects the Y axis at point 2 [MB/s], and with the X - axis at the point 1, and becomes closer to the origin in the middle. Area of class 2 is a region indicating a higher speed than the curve of performance class 2 and lower than the curve speed class 4 (described below), in the first quadrant.

Similarly, the curve speed class 4 intersects the Y axis at point 4 [MB/s], and with the X - axis at the point 1, and goes much farther from the origin than the curve speed card class 2. Area card class 4 is the region on the side opposite the beginning of the curve speed card class 4.

Similarly curve defined speed class 6, which intersects the Y axis at point 6 [MB/s].

Fig is a table showing the measurement conditions required characteristics card of each class is shown figure 11. As described above, the time tWFthe sequence of operations of the client and the size of SENRU affect the performance of the Pw account. Clock frequency fSDSD affects the time tWFthe sequence of operations of the client part. Clock frequency fSDSD and size SENEN is set to the values shown in Fig, as the measurement conditions required characteristics of each class. Leading device is Wu preferably 20 to access the card 19 memory using larger RU, in order to improve performance.

[3-3] the Relationship between capacity and maximum AU size

The host device 20 makes a request of another parameter related to the block size. Register, send size SAUAU, set according to physical standards card 19 memory. Then, the memory card may show an optimum size SAUAU the host device 20. As a result, the host device 20 effectively uses AU 31. The size required for the host buffer 27, is set according to the maximum value of AU 31 as described below.

The maximum AU size corresponding to the capacity of the card 19 memory may be the same as set forth below.

Card capacity/maximum AU size = 16 to 128 MB/128 KB, 256 MB/256 KB, 512 MB/512 KB, 1 GB/1 MB, 2 GB/2 MB, 4 to 32 GB/4 MB.

[3-4] the Requirement of speed reading

Speed reading at least 2 [MB/s], 4 [MB/s] and 6 [MB/s] for the card class 2, 4 and 6, respectively, is set when a read is performed in the elements of EN 32. However, this does not guarantee the performance of reading the host device 20. This is because the hardware in the host device 20 is not taken into account in the previous note.

[3-5] Requirements determine the physical standard cards

When the speed is set using the class and the hypoxia parameters and standardized, the standard of performance must take into account the standards of both current and next generation. Therefore, the standard of performance should take into account the memory card of the next generation in addition to the previous standards. So, in the current SD cardTMparameters such as the Pw performance record, performance Pm move and the time TFWwrite file system must be set in accordance with the physical standard 1.01, 1.10.

Given card 19 memory of a certain class (for example, high class defined in the future). Memory card class is not made in accordance with a certain physical standard (e.g., physical standard 1.01), because of the limitation conditions (for example, clock frequency SD)required for a class definition. This kind of card 19 memory must be performed in accordance with a higher physical standard. For example, card class 6 cannot be carried out in accordance physical standard 1.01, as they are equipped with high-speed mode. Therefore, they must correspond to the physical standard of 1.10.

[3-6] the data Storage class and parameters

Under the new standard, the case can hold the class, size SAUAU, performance Pm move and the coefficient CSDas state information cards the memory. More precisely, the class is stored in the register 24 identifying code performance. Size SAUAU, performance Pm move and the coefficient CSDstored in the register 25 performance parameter.

As described above, the card 19 memory holds the class and parameters. In this case, the host device 20, allowing the identification of the class can be more accurately calculate the performance along with effective use of the card 19 memory.

Fig is a table showing the bit width in bits of the register information in the SD card™. In the SD card™ size SAUAU, performance Pm move and the coefficient CSDdescribed in the register of option performance. These data can be recorded in a separate register cooked. The fields for these data can hold 0 in the memory card which does not support the standard performance. This memory card is recognized as a map of class 0.

Information class can be installed in the field, which keeps a constant value (for example, 0) in a traditional storage device. Thus, conventional devices that do not support this version of the implementation, can be identified as being outside the object classification performance.

Note that the performance of the Pw account is unique in each class definition is but performance records, required for each class). Thus, the host device 20 reads the class, thereby asking about the performance of the Pw entry.

The information in the register 24 identifying code performance and the register 25 performance parameter may be output to the host device 20, when the card 19 memory receives a predetermined command from the host device 20.

The value set in the register 24 identifying code performance and the register 25 parameter performance can be recorded as a pre-calculated values during manufacture, or may be defined by the card 19 memory at initialization.

In circulation SD memory card™ has no funds (dedicated register) to display the option performance. Code performance and the performance options can be added in the reserved area of the programmable register. A master device detects code performance for publicizing the performance of the card. Therefore, in circulation SD memory card™ suitable for use without changing the current controller card.

[4] the Sequence of operations of the host device when recording in real time and requirements

[4-1] the Sequence of operations of the host device when recording in real time,/p>

When recording in real time the host device 20 performs a write operation in addition to performing calculations according to the following sequence, using the curve, class and performance options. Preferably, the host device 20 performs the following sequence when recording in real time.

(1) to Determine the speed (in materials of this application, indicated by reference as application performance) Pa requested from an application that is included in the host device 20.

(2) Select the proper number Nd EN recording between updates of the file system.

(3) to Determine the performance of Pc required to implement performance Pa application, taking into account the update of the file system.

(4) to Determine the maximum proportion of r(Pc) employed EN.

(5) to Classify AU 31 in AUfastand AUslow.

(6) to Estimate the available time Trecrecord.

(7) to Adjust the number Nd EN recorded between updates of the file system. When the number Nd EN recorded between updates to the file system, more performance is improved.

(8) When sufficient performance and enough available recording time does not work after these calculations, need to erase the card.

A special method of operations (1 by (8) and the requirements of the host device 20 will be described below.

[4-2] the calculation Method of the performance with the update of the file system

The update cycle of a typical file system (FAT) when recording in real time is shown in Fig.7. Preferably, the host device 20 is performed in the following sequence when updating the file system.

[4-2-1] terms of performance maps taking into account the update of the file system

The host device 20 determines performance Pc card that is required to meet Pa, performance Pa application and the average time TFWwrite file system. As described above, is inserted into the sequence of recording of the file system, and thereby deteriorates the performance record. Thus, the host device 20 requires a map, in General, outstanding performance Pc card that is higher than the speed of the Pa application.

Some of the top devices 20 can support some different types of modes of bit rate in accordance with the type of application. In this case, the host device 20 determines the performance of the Pa application in accordance with the mode selected by the user.

Preferably, the host device 20 was due not to reject the card 19 memory that does not match the performance of Pa applications, and to adjust the speed of the host device 20 in accordance with the class card 19 memory.

the example when the speed of card the card 19 memory is the worst relative performance Pa applications, it is desirable that the host device 20 has changed the mode on the lower, requiring lower performance Pa applications. For example, can be increased by a data compression ratio can be reduced to the resolution of the image or may be reduced frame rate to provide the host device 20 can correspond to a lower performance Pa applications. In order to implement a method, the host device 20 preferably contains some variety of modes to use card 19 memory with poor performance.

The host device 20 has several modes with different performance records, and thus it can write at a lower speed, even if a failover occurs. Failure can occur when using a map class 0, due to the fact that the host device 20 does not know whether it can work in a certain mode before it will not actually try mode.

Performance Pa application and performance Pc card that is required to meet the Pa (in the materials of the present application performance cards)expressed in the following mathematical expressions 6 and 7, respectively.

[Mathematical expression 6]

<> The performance requested by the application:

Pa = (Sc × Nd) / (Sc × Nd/Pc + TFW).

[Mathematical expression 7]

Performance Pc that is required to meet:

Pc = (Sc × Nd × Pa) / (Sc × Nd - Pa × TFW).

Performance Pc card varies depending on the number Nd EN recording between updates of the file system. As can be seen from Fig.7, the number Nd EN recording between updates of the file system changes depending on the frequency of update of the file system. Thus, the frequency of update of the file system affects the performance of the Pc card. The method of determining the frequency of update of the file system will be described in the following [4-2-2].

[4-2-2] the Condition of the refresh period of the file system

The update time of the file system (FAT) (from filesystem updates until the next update of the file system) is determined by inserting a sequence of file system entries in the data transfer. Therefore, the refresh period of the file system depends on the write speed; however, the accuracy of time is not important. A simple method can be applied to a master device 20 just hoped the update period of the file system.

The update period of the file system is expressed using the following mathematical expression 8.

[Mathematical expression 8]

Period obnovleniya system:

TPF= Sc × Nd / Pa

= Sc × Nd / Pc + TFW(ave.).

The host device 20 can configure the number of RU, recorded between updates to the file system, taking into account the performance of the card, which is the result of recording a file system. In this case, the period TPFpreferably is one second or more.

When selected a greater number of RU, performance Pc card approaches the performance of Pa applications. In this manner the card 19 memory having a low performance capable of satisfying performance Pa applications.

The following method is provided as another way of determining the period of update of the file system. According to the method, the period TFU(this is equivalent to TPF) is determined using a timer included in the host device 20. In this case, TFUis permanent. Upgrade the file system is inserted between the entries EN. Thus, the number of RU, recorded between updates of the file system varies from period TFUupdate the file system.

In this case, the amount of data of period TFUupdate the file system is expressed using the following mathematical expression 9.

[Mathematical expression 9]

The number of data time Tsub> FU: Pa × TFU.

The mathematical expression 9 converted, and thus the performance of the Pc card are expressed using the following mathematical expression 10.

[Mathematical expression 10]

The performance of the card to meet Pa:

Pc = (Pa × TFU) / (TFU- TFW(ave.)).

[4-3] Classification item selection (AU)

The host device 20 determines which AU 31 available for recording in real time. In other words, the host device 20 determines satisfies or not each AU 31 requested performance Pc card. The performance of each AU 31 varies depending on the number of people employed EN, as seen in Fig.6. Therefore, each AU 31 is determined using the share of employed EN as the threshold value.

[4-3-1] the Maximum proportion of employed EN

As shown in figure 4, if the position And start recording and the position At the end of the record are on the border of AU 31, performance AU 31 is calculated using the mathematical expression 3.

Thus, it is possible to deduce the maximum proportion of r(Pc) employed EN from performance Pc card as an inverse function of the mathematical expression 3.

AU 31 having a share r busy RU, less than the maximum proportion of r(Pc) employed RU, AU is 31 satisfying performance Pc card. The smaller the share of r employed EN, which has AU 31, those who more suitable recording in real time. AU 31 classified in AUfastand AUslowusing the maximum fraction r(Pc) employed EN as the boundary, as described below.

Maximum share of r(Pc) employed EN is expressed using the following mathematical expression 11.

[Mathematical expression 11]

The maximum proportion of employed EN:

r(Pc) = [(Pw - Pc) × Pm] / [(Pw - Pm) × Pc + Pw × Pm].

[4-3-2] Classification of AU into two categories :

The master unit 20 classifies AU 31 into two categories. One is AUfast(area of element of adaptive management). This AU 31 has a speed sufficient to record real-time performance Pc card. The other is AUslow(area of element non-adaptive control). This AU 31 is unsuitable for recording in real time, because the memory is too fragmented.

The host device 20 counts the number of Nu-employed EN for each AU 31, and then calculates the share of r employed EN number Nu employed EN. Determines whether AU AUfastor AUslowusing the following mathematical expression 12.

[Mathematical expression 12]

If Nu / Nt < r(Pc), AU is AUfast,

if Nu / Nt ≥ r(Pc), AU is AUslow.

More precisely, if (number Nu employed EN) / (total number Nt EN in AU) is less than the maximum proportion of r(Pc)employed EN, AU is classified as AUfast. On the other hand, if Nu / Nt is equal to or greater than the maximum fraction r(Pc) employed RU, AU classified as AUslow.

Fig shows the allocation of AU 31 in the space 21 of the memory and shows the distribution of AU 31 in two space 21 of the memory. The top AU 31 includes a file system; for this reason it is an area that is unsuitable for recording in real time. Therefore, the topmost AU 31 classified as AUslow. Moreover, the element directory should not be created in AU 31, the recording data.

AU1 and AU4 not include the file system; however, it is determined that they are too fragmented, as (the number of Nu-employed EN) / (total number Nt EN in AU) is greater than the maximum percentage r(Pc) employed EN.

[4-4] Available recording time

The host device 20 can calculate the time available for recording in real-time using the following mathematical expression 13. In this expression Nr Nr represents the number available EN 32 of all AU 31 defined as AUfast. If enough available recording time is not prepared, the host device 20 issues instructions to transfer these records to another location, or reformat the card 19 memory.

[Mat is political expression 13]

Available recording time:

TREC= Sc × Nr / Pa.

The host device 20 again calculates the available recording time when it sets the number Nd EN recording between updates to the file system, that is, the period TPFupdate the file system, great. This is because a greater number Nd EN between updates file system improves performance. In other words, the maximum value of the fraction r(Pc) employed EN increases, and the number of AUfastincreases; therefore, increases the available recording time.

[4-5] the Requirements for the master buffer

Leading the buffer 27 must have a capacity sufficient to store data temporarily. Leading the buffer 27 must meet the following requirements.

[4-5-1] Requirements to the size of the host buffer

The host buffer 27, you must have the capacity of satisfying the following queries.

(1) the Demand from the pack file system (FAT)

When the host device 20 updates the file system, the host of the buffer used for temporary storage of data, which are assumed to be recorded during recording of the file system. For this reason, requires a large buffer size. The buffer size is specified as the maximum value of TFW(max) recording time of the file system. Example is, the maximum value of TFW(max) recording time of the file system is 750 [MS], as can be seen from the mathematical expression 5. In General, the buffer size is presented as the data recording time, which can store the buffer.

(2) Demand-side bug fixes

Leading the buffer 27 is used to Supplement the delay in the correction of errors in the data record. If an error occurs the account, the card 19 memory does not return the status of the CRC and does not stop multi-record or does not display the occurrence of an error event. The host buffer 27 to store the data up until the recording is completed, in order to provide a re-recording the opportunity to run if an error occurs.

Leading the buffer 27 must be properly sized, for example 250 [MS], so that the host device 20 continued recording in real time, even if an error occurs. This is because the value of 250 [MS] is set as the maximum time to complete the recording. Therefore, the size required in combination with a maximum value of TFW(max) recording time of the file system. If the maximum value of TFW(max) recording time of the file system is 750 [MS], require a buffer allowing data storage, in the amount equivalent to 1 [s].

(3) the Demand compensation write latency AU

If RU 32 exist in AU 31, includes case, when employed EN 32 is collected in the upper part of the AU 31, data cannot be written until the data stored in the busy EN 32, not moved to another EN 32. Therefore, these records should be stored in the host buffer, while the move recorded EN 32.

Fig shows the principle of the host buffer 27. As shown in Fig, it is assumed that the data are continuously in the host buffer 27 of the host device 20 at a constant speed Pa, and the host device 20 reads the data stored in the host buffer 27 to record the data in AU 31.

On the other hand, the transmission speed of the data output from the host buffer 27 depends on the fragmented structure AU 31. More precisely, if AU 31 there is recorded EN 32, as described above, the data records are held by the leading buffer; therefore, they are not displayed. If no written EN 32 does not exist in AU 31, or when completed move EN 32, host buffer 27 outputs the data with a speed of Pw.

As can be seen from the description, the size required for the host buffer 27 is determined by how long the action takes to move all employed EN 32 in AU 31.

If the size of the host buffer 27 becomes insufficient, overflow may occur (lack of buffer) host buffer 27 depending on the fragmented structure of the data is x in AU fast. For this reason, we may additionally require consideration in accordance with the size of the host buffer 27 and fragmented data structure AUfast.

(4) Preparation for data entry

Preparing data recording takes a certain time from the host device 20, and, accordingly, the data records are formed discretely. In this case, data can be once stored in the buffer 27 and can be written master controller 26. In this manner, the transfer can be performed continuously; therefore, can be achieved efficient transfer.

In particular, when recording in real-time real-time data once stored in the host buffer 27, working as a FIFO (first-in, first-out), and then written to the card 19 memory. In this manner it is possible to keep the time spent on training (calculation) real-time data. In other words, the data is now written to the card 19 memory.

If the data is written directly to the card 19 memory once were calculated in system memory, the procedure is consistent. For this reason, the calculation and recording of data must be performed serially. If sequential operation, no data can be written into the card 19 memory at the time of calculation, and because of this map 19 n is Mati demonstrates performance worse than the class that it represents.

The required size of the buffer provided in the form of the function using the performance Pa applications, performance Pw displacement, the maximum fraction r(Pc) employed EN and size SAUAU.

In the following mathematical expression 14 shows the required size of SBUFbuffer. In terms 14 of the first element (Pa) on the right side corresponds to the description columns (1) and (2). The second element on the right side corresponds to the description column (3). Description column (4) is not included in the mathematical expression 14. Moreover, an additional buffer may be required depending on the standards of the host device 20.

[Mathematical expression 14]

Required buffer size:

SBUF> Pa + [r(Pc) × SAU× Pa] / Pm.

If the performance of the Pa application is less than the speed of the Pm move, and the host buffer 27 is large, exceeding (Pa + SAUthe mathematical expression 14 is always satisfied.

[4-5-2] Processing when the size of the host buffer is small

Regardless of the above discussion, the following is a clarification about the way to find AUfasthaving a small degree of fragmentation, if the size of the host buffer 27 is insufficient. Preferably, the leading buffer 27 is better to have a sufficient size than the execution of ways which a, here.

Fig shows the case where all occupied EN 32 is collected in the upper part of the AU 31. Maximum share of r(Pc) employed EN represents the boundary that divides busy EN 32c and the free EN 32d. When the host device 20 writes the data to the first free EN 32d, the conclusions of the card 19 memory long busy until then, until you have moved all occupied EN 32c. During this duration the data record stored in the host buffer 27. In this case, the time required to move all employed 32c EN in AU 31, is expressed as below.

(r(Pc) × SAU) / Pm

Therefore, the size of the host buffer 27 that is required in this case, is expressed as the following mathematical expression 15.

[Mathematical expression 15]

The size of the host buffer: SBUF> Pa × [(r(Pc) × SAU) / Pm].

The following mathematical expression 16 derived from a mathematical expression 15.

[Mathematical expression 16]

The proportion of employed EN, limited by the size of the host buffer

= r(Pc) < [(Pm × SBUF) / (Pa × SAU)].

As can be seen from the mathematical expression 16, if the size of the host buffer 27 is small, the maximum share of r(Pc) employed EN is limited by the size of the host buffer 27. In this case, AU 31 should be classified using the maximum fraction r(Pc) employed EN, limited by the size of the host buffer 27 as r(Pc) in matematicheskoi expression 12.

Moreover, if the size of the host buffer 27 is small, the observed size of the data stored in the host buffer 27, during recording of data in real-time. In accordance with the observed result, control can be performed so that the bit rate of the transmission data temporarily made smaller or can be controlled by a refresh period of the file system to prevent buffer overflow. There is a problem that the host buffer 27 overflows; as a result, lost data. For this reason, data loss must be prevented, even if the quality of the data.

If the recording is done using performance records, predicted on the basis of performance information (performance parameter) of the storage device 19, the host device 20 generates a mode change. More precisely, when there is a buffer overflow or often an error occurs during access to a storage device 19, the host device performs the change of mode lower rate than the rate based on the performance information of the storage device 19.

[4-6] Other

The host device 20 may include means for comparing the performance information (e.g., class, parameter performance) with his performance information (same as above).

The host device 20 may be provided with a comparator for comparing the performance information read from the card 19 memory, with its own performance information. This is based on the following considerations. For example, even if one of the card 19 memory and the host device has a very high speed, the other may not have performance equivalent to the above. In this case, lower performance, in the end, restricts the transfer of data between the master device 20 and the card 19 memory.

The performance that users expect, may not be obtained when using the card 19 memory lower class. In order to avoid the disadvantage, the host device 20 can compare the performance information read from the card 19 memory with his performance information and to inform users about the result via the display.

For example, the card 19 memory is inserted in the host device 20, and then the host device 20 displays the following message. That is "This device belongs to class M; however, the work is performed on the basis of class N (N < M), as a class, inserted a memory card is N". In this way users can understand why the expected speed is not obtained, even when using the fast memory card class N. The display screen can be performed automatically when the card 19 memory inserted in the host device 20, or the user can perform a predefined operation to make a message appear on the screen.

The comparison function information of the performance described above is not necessary for the host device 20 to use the card 19 memory that stores information performance.

(The second variant implementation)

Memory card SDTMto which is applicable the first version of the implementation will be explained below.

Fig is a schematic view showing the configuration of an SD memory card™ according to the second variant of implementation of the present invention. SD memory card™ (hereinafter indicated by reference just as a memory card) 41 communicates with the host device 20 via the bus interface 45. Map 41 memory includes a memory chip NAND flash™ (hereinafter indicated by reference just as flash memory), the controller 43 cards, managing chip 42 flash memory, and multiple signal contacts (contacts with the first through ninth) 44. Number 45 links indicates the bus interface.

The controller 43 of the map is equivalent to the controller 22 of the device according to the first variant of implementation (see figure 2). Flash memory 42 is equivalent to protrans the Wu 21 memory at 2.

The signal contacts 44 are connected via electrical connections to the controller 43 of the card. The distribution of signals on the signal contacts 44, that is, from first to ninth pins is as shown in Fig.

Data 0 to data 3 are assigned to the seventh, eighth, ninth and first contacts, respectively. First contact also allocated for signal detection card. The second contact is selected for the team. The third and sixth contacts allocated to the reference potential Vss, and the fourth contact is allocated to the potential Vdd of the power source. The fifth contact is allocated to the signal clocking.

Map 41 memory can be inserted into the slot formed in the host device 20. The master controller 26 (not shown) of the host device communicates various signals and data with the controller 43 of the card the card 41 memory through, from first to ninth pins. For example, when data is written to the card 41 of the memory, the controller 26 sends a write command to the controller 43 cards in the form of a serial signal through the second contact. In this case, the controller 43 card samples the write command is supplied to the second contact in response to a clocking signal supplied to the fifth contact.

As described above, the write command sequentially entered into the controller 43 of the map using only the showing of the contact. A second contact that is allocated to input commands placed between the first point of contact for data 3 and the third contact to the reference potential Vss. The bus interface 45, the corresponding multiple signal contacts 44, is used to link a master controller 26 of the host device 20 with the card 41 memory.

On the other hand, the connection of the flash memory controller 42 43 card is performed through the memory interface NAND flash™. Therefore, although it is not shown, the flash memory 42 and a controller 43 of the memory are connected via the 8-bit input/output (I/O).

For example, when writing data in the flash memory controller 42 43 cards sequentially enters the following information into the flash memory 42 through the line I/O. the Information includes the command 80H data input, a column address, page address, data and command 10H programming. "H" command 80H denotes hexadecimal number, and, in fact, an 8-bit signal "10000000" is fed parallel 8-bit I/O. namely a multi-bit command is fed in parallel through the memory interface NAND flash™.

In the memory interface NAND flash™ command and data to the flash memory 42 is exchanged on the same line I/O. Thus, the interface used for the communication master controller 26 of the host device 20 with the card 41 of the memory is different from that used to communicate the flash memory controller 43 of the map./p>

Fig block diagram showing the hardware configuration of the memory card according to the second variant implementation.

The host device 20 includes hardware and software for accessing the map 41 memory through the bus interface 45. Map 41 memory works, being connected to the master device and the receiving power, and in this case performs the procedure in accordance with the access from the host device 20.

Map 41 memory includes a flash memory 42 and a controller 43 memory, as described above. In the flash memory 42, the size of the block erase (i.e., the size of the block in erase) the erase operation is set at a predetermined size (for example, 256 Kbytes). Moreover, the recording and reading of data are performed in an element called the page (e.g., 2 KB).

The controller 43 card controls the physical structure of the flash memory 42 (e.g., the address of a logical sector is included in the address of a physical block, or any block is erased). The controller 43 of the card has a leading front-end module 53, the microprocessor (MPU) 54, a controller 55 flash memory, a persistent storage device (RAM, ROM) 56, a random access memory (RAM, RAM) 57 and buffer 58.

Senior front-end module 53 performs the interface between the controller 43 maps and leading at what trojstva 20 and includes the register 59. Fig block diagram showing the configuration register 59. The register 59 contains a status register map and registers, such as CID, RCA, DSR, CSD, SCR and OCR.

The registers are defined as set forth below. The status register map is used during normal operation and, for example, stores information about the errors described later. Registers CID, RCA, DSR, CSD, SCR and OCR are used mainly when initialized memory card.

Identification number of the card (CID) stores the card identification number 41 memory. The relative address (RCA) stores the relative address of the card (dynamically defined the master device during initialization). The driver stage register (DSR) accumulates the energy of the excitation bus card.

Map specific data (CSD) store the values of the characteristic parameters of the card 41 memory. CSD, in addition, holds the version information, the identification code performance and setting performance described in the first embodiment.

Register configuration data SD (SCR) stores the array data card 41 memory. Case operating conditions (OCR) stores the operating voltage of the card 41 memory having a limited voltage operating range.

MPU 54 controls the operation of the card 41 memory, taken as a whole. When the card 41 memory receives power, the MPU 54 reads the firmware (control is a TEP), stored in ROM 56, a RAM 57 to perform a predefined sequence of operations. In this manner MPU 54 prepares a table in the RAM 57.

MPU 54 also receives a write command, read and erase to perform a predefined sequence of operations with respect to the flash memory 42, or controls the transfer of data through the buffer 58.

The ROM 56 stores a control program, managed MPU 54. RAM 57 is used as workspace MPU 54 and stores control programs and various tables. The controller 55 flash memory provides the interface between the controller 43 card and flash memory 42.

The buffer 58 temporarily stores a predetermined amount of data (e.g., one page) when writing data sent from the host device 20 in the flash memory 42, and temporarily stores a predetermined amount of data when sending data read from the flash memory 42 to the host device 20.

Fig shows the data array of the flash memory 42 in the map 41 memory. Each page of the flash memory 42 contains 2112 bytes (512-byte area of data memory × 4 + 10-byte area reserve × 4 + 24-byte area of memory management data). 128 pages are one element erase (256 Kbytes + 8 Kbytes (K means 1024). In the following description of the item erase flash memory 42 is set to 256 KB for convenience of explanation.

Fluorescence is W memory 42 includes a buffer 42A pages for input and output data in the flash memory 42. The memory capacity of the buffer 42A page is 2112 bytes (2048 bytes + 64 bytes). When you write data buffer 42A page performs input/output of data in the flash memory 42 when the item in one page, equivalent to its own memory capacity.

If flash memory has a memory capacity of 1 GB, the number of blocks of 256 KB (element erase) is 512.

Fig shows the case where the element erase is 256 Kbytes; however, it is particularly effective to build the item erase 16 Kbytes. In this case, each page contains 528 bytes (512-byte memory area data + 16-byte area of the reserve), and 32 pages are one element erase (16 KB to + 0.5 KB).

Area (memory data), which records data in the flash memory 42, is divided into several areas, in accordance with the stored data, as shown in Fig. Flash memory 42 contains the following memory areas of the data, i.e. the region 61 management data area 62 confidential data region 63 data protection and region 64 user data.

Region 61 management data stores control information relating to the memory card, that is, the security information card 41 memory and the card information, such as media ID.

Region 62 confidential data stores key information used for encryption, and privacy is social data used for authentication, and is an area that is not accessible from the host device 20.

Region 63 data protection keeps meaningful data and is an area that is available only when the host device 20 is tested for accuracy, despite the mutual authentication with the host device 20 attached to the map 41 memory.

Region 64 user data stores user data and is an area that is freely accessible and available to users of the card 41 memory.

The explanation for the second variant implementation is directed to a case where the operation mode of the card 41 memory is a 4-bit SD mode. The present invention is applicable to a case where the operation mode of the card 41 memory is 1-bit mode SD and SPI mode. Fig shows the distribution of signals corresponding to the signal contacts 4-bit SD mode, 1-bit SD mode and SPI mode.

The operation mode of the card 41 memory, in General, classified into SD mode and SPI mode. Mode SD card 41 memory installed in 4-bit SD mode or 1-bit SD mode according to the command of changing the bus width of the host device 20.

Four contact contact data 0 (DAT0) contact data 3 (DAT3), are all used to transfer data in 4-bit SD mode, which transmits data on the elements of the 4-bit bit is STI.

1-bit SD mode, which transmits the transmission data items 1-bit wide, the contact data 0 (DAT0) is used only for data transmission, and contact data 1 (DAT1) and data 2 (DAT2) is not used at all. Contact data 3 (DAT3) is used, for example, for asynchronous interrupts the host device 20 of the card 19 memory.

In SPI mode the contact data 0 (DAT0) is used as the signal line data (Data to output) of the card 19 memory in the host device 20. Contact command (CMD) is used as the signal line data (Data input from the host device 20 in card 19 memory. Contact data 1 (DAT1) and pin 2 (DAT2) are not used. In SPI mode the contact data 3 (DAT3) is used for signal transmission of the chip select (CS) from the host device 20 in card 19 memory.

When the flash memory 42 contains a single chip card 19 memory is used for not so high-speed operation and is classified as class M (M is zero or a positive integer).

When the flash memory 42 has class N (N is a positive integer greater than M), more high-speed than the card 19 memory on one chip, some flash memory chips 42 can represent some chips in card 19 memory. In this manner, the card controller writes data to the one flash memory chip, while transmitting data in other flash memory chip. Thus, the external data transfer rate between the controller 43 of the card and the flash memory 42 is improved.

Moreover, it can be applied to the flash memory chip, having at disposal a copy of the page (or backup), and thus data stored in a page of flash memory chips, are copied to another page of the same flash memory chip. In this manner improves the performance of the Pm movement.

The present invention is described based on the first and second embodiments; however, the present invention is not limited in scope. Digital camera, digital camcorder, PC and PDA are given as the leading device to which the present invention is applicable.

In addition to NAND flash™flash memory AND NOR flash memory™, that is, the memory device containing the floating gate electrode as a layer charge memory, can be used as a semiconductor memory used as a storage device by the first and second variants of implementation. Moreover, there may be used a memory device containing insulating layer MONOS as a layer charge memory. Moreover, there may be used non-volatile semiconductor memory device, is such as magnetic random access memory (MRAM) and ferromagnetic random access memory (FeRAM).

Additional advantages and modifications will easily come to mind are the specialists in this field of technology. Therefore, the invention in its broader aspects is not limited to particular details and typical choices of implementation shown and described in materials of this application. Accordingly, various modifications can be made without leaving the essence or scope of the General inventive concept, which is defined by the attached claims and their equivalents.

1. A storage device containing:

semiconductor memory that retains its data;

the controller executes instructions to write data in the semiconductor memory in accordance with a query that takes the controller; and

the register provided for in the controller and secure the information class, showing one of the classes of performance are classified by speed, and referred to one of the classes of performance indicates that the storage device is guaranteed to provide a minimum performance marked the mentioned one class performance

when this storage device configured to issue information to the class in response to the instruction, external to Zap menudemo device.

2. The device according to claim 1, in which case optionally keeps information of the performance parameter related to the performance of the semiconductor memory and the controller.

3. The device according to claim 2, in which the information of the performance parameter includes at least one of the speed required to move the data in the semiconductor memory, and the size of the area of the control memory space used by the host device that uses a mass storage device.

4. The device according to claim 1, whereby the device is made with the ability to maintain performance when writing data both before and after the update information file.

5. The device according to claim 1, additionally containing:

the body covering the semiconductor memory and the controller; and

part of the display provided on the housing and representing the class.

6. The host device supporting multiple modes of data transfer rate, and transmitting data with a memory device that stores information class, and referred to the host device includes a processor configured to

determine the maximum transfer rate of data from multiple modes of data transmission speed information of the class bistromath what I mentioned using information about the class,

selecting at least one of transmission modes mode maximum data transfer speeds and modes of transmission speed lower than the maximum data transfer rate.

7. The device according to claim 6, reading performance parameter related to the performance of the storage device from the storage device, and performing a calculation using the performance parameter.

8. The device according to claim 7, the control memory space of the semiconductor memory through the areas of controls, each of which contains the Toolbox, recording, and classifying the field controls on the usable area of the control that allows saving the data with the requested performance, and not the area of the control, which does not allow saving data with the requested performance, in accordance with the condition of the item record in the areas of controls, using the performance parameter.

9. The device according to claim 8, using a suitable area of the control for recording in real time.

10. The device according to claim 9, calculates the available recording time for each data that is recorded with the requested performance, using the performance and the number of unoccupied suitable about the t controls.

11. The device according to claim 6, specifies that the class is not defined in the storage device, when information class storage device is "0".

12. The device according to Pb, recording data in a storage device with a second speed lower than the first speed, when the speed of the storage device does not meet the first performance that is required by the master device.

13. The device according to claim 6, store the data requested on the entry in the buffer of the host device, while writing data in the storage device.

14. The device according to claim 6, further containing:

housing; and

part of the display provided on the housing and showing the class set for the master.



 

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