High-speed multichannel device for data transmission between computer and remote terminal units, executed in form of universal serial busbar

FIELD: physics, computer facilities.

SUBSTANCE: invention concerns computer facilities, namely to field of local computer networks. The device contains the computer, signal lines (SL1, SL2), four cables, a microcircuit of the controller of the computer, a microcircuit of controllers of remote terminal units, microcircuits of controllers of hubs (H1, H2) and the universal serial busbar, the optimum loads (OL1, ..., OL10), voltage regulators (VR1, VR2), filters (F1, ..., F5), intended for noise reduction on supply, compensation circuits (CC1, ..., CC4) of transitive performance of the cable signal lines, the shared bus (SB1), the supply busbar (SBB1), the power supply (PS1), and also N data links DL1, ..., DLM.

EFFECT: increase of the peak speed of data transmission between the computer and remote terminal units to 480 Mbit/with at simultaneous magnification of quantity of data links with connected remote terminal units and lengths of a used cable on which packages of the numeral information including with high speed can be transmitted.

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The invention relates to computing, and in particular to the field of local area networks for universal serial buses.

Known serial bus data intended for a peripheral device type mouse, keyboard, printer, modem and hard disk [1].

It is also known a device for data transmission between a computer and peripheral devices, made in the form of universal serial bus, includes cable with signal lines, power rails and connectors on the ends for connecting peripheral devices to a personal computer, a controller chip that generates commands that define the operation of peripheral devices, and chip located in the peripheral device [2].

The disadvantages of these devices for connection of a personal computer peripheral devices are:

- restrictions on the length of the packet of digital information,

- high complexity, due to the complexity of the electrical signal repeaters,

- high complexity, due to the presence of devices - splitters cables.

Closest to the invention is a device for data transmission between a computer and peripheral devices [3], made in the form of a universal serial bus include the cable from the signal lines, power rails and connectors on the ends for connecting peripheral devices to a personal computer, a controller chip computer that generates commands that define the operation of peripheral devices, the controller chip device that controls the directions of flows of the transferred data that is located in the peripheral device, which contains at least two chip-relay first and second external electrodes connected to the output circuits of the controllers, and the third and fourth external electrodes connected to the cable, the termination impedances of the cable and controllers and converts the signal levels of the output circuits of controllers located in a personal computer and a peripheral device, to ensure their transmission cable without reflection signals in it.

Functional diagram of the device according to the prototype [3] for data transmission between a personal computer and a peripheral device illustrated in figures 1 and 2.

Device for transferring data between the personal computer 1 and the peripheral device 2, shown in figure 1 and selected as a prototype, made in the form of universal serial bus, includes cable with signal lines 3 and 4, a power bus (not shown) and connectors 5 and 6 at the ends for connecting the peripheral the applications of the device with a personal computer, the controller chip 7 computer that generates commands that define the operation of peripheral devices, the controller chip 8 device that controls the directions of flows of the transferred data that is located in the peripheral device 2. The device further comprises two identical circuits 9 and 10, a functional block diagram of which is shown in figure 2. The first chip 11 and second 12 external electrodes connected to the output circuits of the controllers 7 and 8, and the third 13 and fourth 14 external electrodes with the signal lines 3 and 4 of the cable. Chip 9 and 10 agree the impedances of the cable and controllers and convert the levels of the signals from the output circuits of the controllers 7 and 8, located in the personal computer 1 and the peripheral device 2, for transmission over the cable without reflection.

As shown in figure 2, each additional chip 9 and 10 includes first and second receivers 15 and 16, the United differential inputs, respectively, with the first 11, second 12, third 13 and fourth 14 external electrodes of the chip 9 and 10, and outputs - inputs, respectively, of the first and second transmitter 17 and 18, which are differential outputs connected to the third 13 and fourth 14, the first 11 and second 12 external electrodes of the chip 9 and 10. Chip 9 and 10 contain the timer device 19 connected to log the economic unit 20, the inputs of which are connected to the outputs of the receivers, and outputs to the control inputs of the first and second transmitters 17 and 18, for generating transmitter signals permit data transmission to the external electrodes 11, 12, 13, 14 circuits 9 and 10.

Analysis of technical solutions, declared in the prototype [3], shows that it does not completely eliminate the disadvantages of the known devices used for connection of a personal computer peripheral devices.

So serious disadvantage of the device, as claimed in the prototype [3], is a fundamental limitation of the length of the communication lines 3 and 4 in the device data by the value of the order of 25 meters Is due to the fact that the prototype is not taken into account:

1) the transient response of the signal line cable section is very slow rise near stationary values, which leads to a significant impact on the distortion of the pulse shape of the signals into digital packets of information and, as a consequence, a significant increase in jitter (deviation indicative of signal sites from their desired position in time),

2) the voltage drop on the power bus, resulting in increased jitter digital signals,

3) not taken into account the effect of noise on the amount of jitter at longer signal line cable.

In the prototype is not provided with the agreement in full of the amount of wave resistance of the cable with the output circuits of the relay due to real variations of the resistors in the technology of integrated circuits. In addition, limit the types of cables and their parameters. Chip repeaters must be developed for each nominal value of the wave resistance of the cable. The maximum data rate in the prototype is not high and is 12 Mbit/s

The challenge which seeks the invention is to achieve the following technical results:

1) increase the maximum data transfer rate between the computer and peripheral devices 40 times up to 480 Mbit/s

2) increasing the number of data channels with the plug peripheral devices

3) increasing the length of the cable used, which can be transmitted in packets of digital information, including high speed, to a value limited only by the Protocol of data exchange (response) in the serial bus in accordance with the specification of this bus, and the ability to reconcile the wave resistance of the cable when using different types of cables through the use of chip controller hub universal serial bus with external concerted loads and provide the necessary data transfer rate, correction schemes of the transition characteristics of the cable, an additional voltage regulators, power supplies, and Phi is trow, designed to reduce noise on the power.

To achieve the mentioned technical result in the device to transfer data between your computer and peripheral devices [3], made in the form of universal serial bus, includes cable with signal lines, a power bus, the controller chip of the computer that generates the commands that define the operation of peripheral devices, the controller chip device that controls the directions of flows of the transferred data located in the first peripheral device additionally incorporates new elements, which are essential features of the invention: the first hub controller chip universal serial bus, in which the first and second findings of the rising port connected respectively with the first and second pins of the controller of the computer and also connected respectively through the first and second agreed load with the third and fourth conclusions of the rising port of the first chip controller hub universal serial bus, a third output circuits of the controller computer is a General output and is connected to the fifth output of the first chip controller hub universal serial bus, the first output of the first voltage regulator, the first conclusions of pervos and second filters, designed to reduce noise on the power supply, the sixth output of the first chip controller hub universal serial bus is connected to the second pins of the first filter designed to reduce noise on the power supply and the first voltage, the fourth output circuits of the controller of a computer is the power supply pin and connected with the second output of the second filter designed to reduce noise on the power, and the third output of the first voltage regulator, and N data channels, each j-th of which contains L series-connected extension cable is a universal serial bus, including the first extension universal serial bus, intermediate (s=2, ..., L-1) extension cables universal serial bus and the last L-th extension cable, universal serial bus, while the first and second findings of the first extension universal serial bus are respectively the first and second terminals of the data transmission channel, the first output of the first extension universal serial bus through the first correction pattern transition characteristics of the cable is connected to the first output of the third of the agreed load, a second output which is connected to the third output data channel, the second terminal of the first extension, University of the existing serial bus through the second correction pattern transition characteristics of the cable is connected to the first output of the fourth agreed load, the second output of which is connected to the fourth output data channel, the third and fourth findings of the first extension universal serial bus connected respectively with the first and second findings of the third filter designed to reduce noise on the power, and are respectively the fifth and sixth terminals of the data transmission channel, the first, second, third and fourth conclusions s-th (s=2, ..., L-1) extension universal serial bus connected respectively with the fifth, sixth, seventh and eighth pins (s-1)-th extension universal serial bus, and the fifth, sixth, seventh and eighth conclusions s-th extension universal serial bus connected respectively to the first, second, third and fourth output (s+1)-th extension universal serial bus, fifth and sixth conclusions the last L-th extension universal serial bus connected respectively with the first conclusions of the first and second signal lines, seventh and eighth conclusions the last L-th extension universal serial bus connected respectively with the first conclusions of the first shared bus and the first power rail, the second the conclusions of the first and second signal lines are connected respectively with the first and second conclusions the rising port of the second chip controller hub of the University of the universal serial bus, the second output of the first signal line connected in series through the third correction pattern transition characteristics of the cable and a fifth matched load is connected to the third output of the rising port of the second chip controller hub universal serial bus, a second output of the second signal line connected in series through the fourth correction pattern transition characteristics of the cable and the sixth matched load is connected also with the fourth output of the rising port of the second chip controller hub universal serial bus, a second output of the first shared bus is connected to the fifth output of the second chip controller hub universal serial bus, the first findings from the fourth and fifth filters for noise reduction on diet, the first findings of the second voltage and the first power source, the sixth output of the second chip controller hub universal serial bus is connected to the second pins of the fifth filter designed to reduce noise on the power supply and the second voltage, the second output of the first power rail is connected with the second output of the fourth filter designed to reduce noise on the power supply, the third output of the second voltage and the second output PE the first power source, each j-th channel data contains M downstream ports of the second chip controller hub universal serial bus and M controllers M peripheral devices, each j-th channel data to each i-th of the M downlink ports of the second chip controller hub universal serial bus connected to the corresponding i-th controller of the i-th peripheral device, the first output of each i-th of the M downlink ports of the second chip controller hub universal serial bus is connected to the first output of the i-th controller corresponding to the i-th peripheral device, the second output of each i-th of M downstream ports of the second chip controller hub universal serial bus is connected with the second output of the i-th controller corresponding to the i-th peripheral device, the first output of each of the i-th downstream port of the second chip controller hub universal serial bus is connected through appropriate this conclusion is consistent load with the third output of the same i-th port of the second chip controller hub universal serial bus, a second output of each of the i-th downstream port of the second chip controller hub universal serial bus is connected through appropriate this conclusion according to the EN load with the fourth output of the same i-th port of the second chip controller hub universal serial bus, the third conclusion of each i-th of the M controller M peripheral devices connected with the second output of the first shared bus, the fourth output of each i-th of the M controller M peripheral devices connected with the second output of the first power rail, the first and second findings of the first downstream port of the second chip controller hub universal serial bus connected respectively with the first and second findings of the first controller of the first peripheral device, the first output of the first downstream port of the second chip controller hub universal serial bus is connected through the seventh matched load that corresponds to the first output of the first downstream port of the second chip controller hub universal serial tires with the third output of the first downstream port of the second chip controller hub universal serial bus, a second output of the first downstream port of the second chip controller hub universal serial bus is connected through eighth matched load corresponding to the second output of the first downstream port of the second chip controller hub universal serial bus, with the fourth output of the first downstream port of the second chip controller hub universal sequentially the bus, the third and fourth findings of the first controller of the first peripheral device is connected respectively with the second pins of the first shared bus and the first power rail, the first and second findings of the M-th downward port of the second chip controller hub universal serial bus connected respectively with the first and second findings of the M-th controller M-th peripheral device, the first output of the M-th downward port of the second chip controller hub universal serial bus is connected through ninth matched load that corresponds to the first output of the M-th downward port of the second chip controller hub universal serial bus with the third output of the M-th downward port of the second chip controller hub universal serial bus, a second output of the M-th downward port of the second chip controller hub universal serial bus is connected via a tenth matched load corresponding to the second output of the M-th downward port of the second chip controller hub universal serial bus, with the fourth output of the M-th downward port of the second chip controller hub universal serial bus, the third and fourth conclusions M-th controller M-th peripheral devices connected respectively with the which the conclusions of the first shared bus and the first power rail, the first hub controller chip universal serial bus contains N downstream ports, which correspond to the N data channels, each j-th of the N downstream ports of the first chip controller hub universal serial bus connected to the corresponding j-th channel data, the first output of each of the j-th of the N downstream ports of the first chip controller hub universal serial bus is connected to the first output of the corresponding j-th channel data, the second output of each of the j-th of the N downstream ports of the first chip controller hub universal serial bus is connected with the second output of the corresponding j-th transmission channel data, the third conclusion of each j-th of the N downstream ports of the first chip controller hub universal serial bus connected to the third output of the corresponding j-th data channel, the fourth output of each of the j-th of the N downstream ports of the first chip controller hub universal serial bus is connected to the fourth output of the corresponding j-th data channel, the third output of the controller computer connected with patmi conclusions N data channels, the fourth output controller computer is connected also with sixth forms conclusions N data channels, the first is AVOD first downstream port of the first chip controller hub universal serial bus is connected to the first output of the first data channel, the second output of the first downstream port of the first chip controller hub universal serial bus is connected with the second output of the first channel data, the third output of the first downstream port of the first chip controller hub universal serial bus connected to the third output of the first channel data, the fourth output of the first downstream port of the first chip controller hub universal serial bus is connected to the fourth output of the first channel data, the third output of the controller computer is connected with the fifth output of the first channel data, the fourth output controller computer is connected also with the sixth output of the first channel data, the first output of the N-th downstream port of the first chip controller hub universal serial bus is connected to the first output of the N-th data transmission channel, the second terminal of the N-th downstream port of the first chip controller hub universal serial bus is connected with the second output of the N-th data transmission channel, the third output of the N-th downstream port of the first chip controller hub universal serial bus connected to the third output of the N-th data transmission channel, the fourth output of the N-th downstream port of the first chip controller hub universal the serial bus is connected to the fourth output of the N-th data transmission channel, the third output of the controller computer is connected also with the fifths conclusions of the N-th data transmission channel, the fourth output controller computer is connected also with the sixth output of the N-th channel data.

The second option is a specific embodiment of the high-speed multi-channel device for transmitting data between a computer and peripheral devices, made in the form of a universal serial bus according to the present invention differs in that each of the said extensions universal serial bus contains a third and a fourth signal line, the second common bus and the second power rail, the first conclusions which are respectively the first, second, third and fourth terminals of the extension universal serial bus, second third and fourth signal lines connected respectively with the first and second findings of the rising port of the third chip controller hub universal serial bus, a second output of the third signal line through connected in series fifth correction pattern transition characteristics of the cable and the eleventh matched load is connected to the third output of the rising port of the third chip controller hub universal serial bus, a second output of the fourth signal is the real line connected in series through sixth correction pattern transition characteristics of the cable and the twelfth matched load is connected also with the fourth output of the rising port of the third chip controller hub universal serial bus, the first and second findings of the downstream port of the third chip controller hub universal serial bus connected respectively to the fifth and sixth output extension cable universal serial bus, the first output of the downstream port of the third chip controller hub universal serial bus connected in series through the seventh correction pattern transition characteristics of the cable and the thirteenth matched load is connected to the third output of the downstream port of the third chip controller hub universal serial bus, a second output of the downstream port of the third chip controller hub universal serial bus connected in series through eighth correction pattern transition characteristics of the cable and the fourteenth matched load is connected also with the fourth output of the downstream port the third chip controller hub universal serial bus, a second output of the second shared bus is connected to the seventh output extension cable universal serial bus, with the fifth output of the third chip controller hub universal serial bus, the first conclusions of the sixth and seventh filter designed to reduce noise on the power supply, the first conclusions t is Atego voltage and the second power source, the sixth output of the third chip controller hub universal serial bus is connected to the second pins of the seventh filter designed to reduce noise on the power, and the third voltage, the second output of the second power rail is connected to the eighth output extension cable universal serial bus, with the second output of the sixth filter designed to reduce noise on the power supply, the third output of the third voltage and the second output of the second power source.

The present invention is illustrated by drawings and oscillograms shown in figure 3, 4, 5 and 6.

Figure 3 shows a functional diagram of the device proposed in the invention, for transferring data between a personal computer and a peripheral device, which includes a computer 1, a signal line (SL, SL) 3, 4 cable, the controller chip 7 computer, controller chips 8, 24 peripheral controller chips hubs (X1, x2) 25, 26 universal serial bus coordinated load (SN, ..., SN) 28, ..., 37, stabilizers 42,43, voltage (STN, STN), filters (F1, ..., F5) 45, ...,49, designed to reduce noise on the power circuit 52, ..., 55 correction (W1, ..., SK4) transition characteristics the signal lines of the cable, the first common bus (OS) 64, the first bus 66 power (CHP), first the source 69 power (IP), and N data channels CPD, ..., N, of which the first channel 60 data KD (j=1) are presented in full, intermediate j-e channels are represented as points, and the last (j=N) channel 61 data N presented in the form of graphic symbols. Each data channel contains M peripheral devices (control Desk 1 incorporates thermal, ..., pumas) with the controller chip in each peripheral device, of which the first (i=1) peripheral device (control Desk 1 incorporates thermal) 2 with controller 8 and the last (i=M) peripheral device (pumas) 21 with the controller 24 is presented in the form of graphic symbols, and intermediate i-e peripheral device is shown as points. Each data channel contains L extension cords (N1, ..., L) universal serial bus of which the first extension (U1) 62 universal serial bus and the last extension (L) 63 universal serial bus is presented in the form of graphic symbols, and the intermediate s-e extension cables universal serial bus devices are shown as points. Each of the chips controller hubs (X1, x2) 25, 26 universal serial bus contains the upstream port of the EAP and N downstream ports (HP1, ..., NPM).

4 shows a functional diagram of the version of the extensions universal in sledovatelei bus of the device, proposed in the invention, which includes a signal line (SL, SL) 22, 23 cable, chip controller hub (X3) 27 universal serial bus coordinated load (SN, ..., CH14) 38, ..., 41, stabilizer 44 voltage (STN), filters (F6, ..., F7 still apply) 50, ..., 51, designed to reduce noise on the power circuit 56, ..., 59 correction (SK, ..., SK8) transition characteristics the signal lines of the cable, the second common bus (OS) 65 the second bus 67 power (CHP), the second source 70 power (IP2). The chip controller hub (X3) 27 universal serial bus contains the upstream port of the EAP and N downstream ports (HP1, ..., NP).

While the proposed high-speed multi-channel device is presented on figure 3, for transferring data between the computer 1 and the peripheral device 2 is made in the form of universal serial bus, includes cable with signal lines 3 and 4, the power bus, the controller chip 7 computer that generates commands that define the operation of peripheral devices, circuit 8 of the first device controller that controls the directions of flows of the transferred data located in the first peripheral device. The device further comprises a first chip controller hub 25 of the universal serial bus, in which the first and second findings of the rising port with dynany respectively with the first and second pins of the controller 7 computer and also connected respectively through the first and second agreed load 28, 29 with the third and fourth conclusions of the rising port of the first chip controller hub 25 of the universal serial bus, a third output circuits of the controller 7 computer is a General output and is connected to the fifth output of the first chip controller hub 25 of the universal serial bus, the first output of the first stabilizer 42 voltage, the first conclusions of the first and second filters 45, 46, designed to reduce noise on the power supply, the sixth output of the first chip controller hub 25 of the universal serial bus is connected to the second pins of the first filter 45, designed to reduce noise on the power and the first stabilizer 42 voltage, the fourth output circuits of the controller 7 computer is the power supply pin and connected with the second output of the second filter 46, which is intended to reduce noise on the power, and the third output of the first stabilizer 42 voltage, and N data channels, with each j-th of which contains L series-connected extension cable is a universal serial bus, including the first extension 62 universal serial bus, intermediate (s=2, ..., L-1) extension cables universal serial bus and the last L-th extension 63 is integrated serial bus, while the first and second findings of the first extension 62 universal serial bus are respectively the first and second terminals of the channel 60 data, the first output of the first extension 62 universal serial bus through the first circuit 52 correction of the transition characteristics of the cable is connected to the first output of the third of the agreed load 30, the second output of which is connected to the third output channel 60 data, the second output of the first extension 62 universal serial bus through a second circuit 53 correction of the transition characteristics of the cable is connected to the first output of the fourth coordinated load 31, the second output of which is connected to the fourth output channel 60 data, third and fourth the findings of the first extension 62 universal serial bus connected respectively with the first and second findings of the third filter 47, designed to reduce noise on the power, and are respectively the fifth and sixth terminals of the channel 60 of the data transmission, the first, second, third and fourth conclusions s-th (s=2, ..., L-1) extension universal serial bus connected respectively with the fifth, sixth, seventh and eighth pins (s-1)-th extension universal serial bus, and the fifth, sixth, seventh and eighth conclusions s-th extension universal in sledovatelei bus connected respectively with the first, the second, third and fourth output (s+1)-th extension universal serial bus, fifth and sixth conclusions the last L-th extension 63 universal serial bus connected respectively with the first conclusions of the first and second signal lines 3, 4, seventh and eighth conclusions the last L-th extension 63 universal serial bus connected respectively with the first conclusions of the first shared bus 64 and the first bus 66 power, the second the conclusions of the first and second signal lines 3, 4 are connected respectively with the first and second findings of the rising port of the second chip controller hub 26 universal serial bus the second output of the first signal line 3 connected in series through the third circuit 54 correction of the transition characteristics of the cable and a fifth matched load 32 is connected with the third output of the rising port of the second chip controller hub 26 universal serial bus, a second output of the second signal line 4 connected in series through the fourth circuit 55 correction of the transition characteristics of the cable and the sixth matched load 33 is connected with the fourth output of the rising port of the second chip controller hub 26 universal serial bus, a second output of the first shared bus 64 is connected to the fifth output of the second chip is a controller hub 26 universal serial bus, the first findings from the fourth and fifth filters 48, 49, designed to reduce noise on the power supply, the first findings of the second stabilizer 43 voltage and the first source 69 power, the sixth output of the second chip controller hub 26 of the universal serial bus is connected to the second pins of the fifth filter 49, intended to reduce noise on the power, and the second stabilizer 43 voltage, the second terminal of the first bus 66 power supply is connected with the second output of the fourth filter 48, designed to reduce noise on the power supply, the third output of the second stabilizer 43 voltage and the second output of the first source 69 power, each j-th channel data contains M downstream ports of the second chip controller hub 26 of the universal serial bus and M controllers M peripheral devices, each j-th channel data to each i-th of the M downlink ports of the second chip controller hub 26 universal serial bus connected to the corresponding i-th controller of the i-th peripheral device, the first output of each i-th of the M downlink ports of the second chip controller hub 26 of the universal serial bus is connected to the first output of the i-th controller corresponding to the i-th peripheral device, the second output of each i-th of M downstream ports of the Torah chip controller hub 26 of the universal serial bus is connected with the second output of the i-th controller corresponding to the i-th peripheral device, the first output of each of the i-th downstream port of the second chip controller hub 26 of the universal serial bus is connected through appropriate this conclusion is consistent load with the third output of the same i-th port of the second chip controller hub 26 universal serial bus, a second output of each of the i-th downstream port of the second chip controller hub 26 of the universal serial bus is connected through appropriate this conclusion is consistent load with the fourth output of the same i-th port of the second chip controller hub 26 universal serial bus, the third output of each i-th of the M controller M peripheral devices connected with the second output the first shared bus 64, the fourth output of each i-th of the M controller M peripheral devices connected with the second output of the first bus 66 power, while the first and second findings of the first downstream port of the second chip controller hub 26 universal serial bus connected respectively with the first and second findings of the first controller 8 of the first peripheral device 2, the first output of the first downstream port of the second chip controller hub 26 of the universal serial bus is connected through the seventh matched load 34 corresponds to the first output of the first n the down port of the second chip controller hub 26 of the universal serial bus with the third output of the first downstream port the second chip controller hub 26 universal serial bus, the second output of the first downstream port of the second chip controller hub 26 of the universal serial bus is connected through eighth matched load 35 corresponding to the second output of the first downstream port of the second chip controller hub 26 universal serial bus, with the fourth output of the first downstream port of the second chip controller hub 26 universal serial bus, the third and fourth findings of the first controller 8 of the first peripheral device 2 is connected respectively with the second pins of the first shared bus 64 and the first bus 66 power supply, the first and second findings of the M-th downward port of the second chip controller hub 26 universal serial bus connected respectively with the first and second the conclusions of the M-th controller 24 M-th peripheral device 21, the first output of the M-th downward port of the second chip controller hub 26 of the universal serial bus is connected through ninth matched load 36 that corresponds to the first output of the M-th downward port of the second chip controller hub 26 universal serial bus, with the third output of the M-th downward port of the second chip controller hub 26 universal serial bus, a second output of the M-th downward port of the second chip controller the ABA 26 universal serial bus is connected via a tenth matched load 37, corresponding to the second output of the M-th downward port of the second chip controller hub 26 universal serial bus, with the fourth output of the M-th downward port of the second chip controller hub 26 universal serial bus, the third and fourth conclusions M-th controller M-th peripheral devices connected respectively with the second pins of the first shared bus 64 and the first bus 66 power, the first chip controller hub 25 of the universal serial bus contains N downstream ports, which correspond to the N data channels, each j-th of the N downstream ports of the first chip controller hub 25 of the universal serial bus is connected the corresponding j-channel data, the first output of each of the j-th of the N downstream ports of the first chip controller hub 25 of the universal serial bus is connected to the first output of the corresponding j-th channel data, the second output of each of the j-th of the N downstream ports of the first chip controller hub 25 of the universal serial bus is connected with the second output of the corresponding j-th data channel, the third conclusion of each j-th of the N downstream ports of the first chip controller hub 25 of the universal serial bus is connected to the third output of the corresponding j-th channel transfers the data the fourth conclusion of each j-th of the N downstream ports of the first chip controller hub 25 of the universal serial bus is connected to the fourth output of the corresponding j-th data channel, the third output of the controller 7 computer is connected also with the fifths conclusions N data channels, the fourth output of the controller 7 computer is connected also with sixth forms conclusions N data channels, the first output of the first downstream port of the first chip controller hub 25 of the universal serial bus is connected to the first output of the first channel 60 data, the second output of the first downstream port of the first chip controller hub aniversaries serial bus connected to the second the output of the first channel 60 data, the third output of the first downstream port of the first chip controller hub 25 of the universal serial bus is connected to the third output of the first channel 60 data, the fourth output of the first downstream port of the first chip controller hub 25 of the universal serial bus is connected to the fourth output of the first channel 60 data, the third output of the controller 7 computer also connected to the fifth output of the first channel 60 data, the fourth output of the controller 7 computer also connected to the sixth output of the first channel is 60 data the first output of the N-th downstream port of the first chip controller hub 25 of the universal serial bus is connected to the first output of the N-th channel 61 of the transmission data, the second output of the N-th downstream port of the first chip controller hub 25 of the universal serial bus is connected with the second output of the N-th channel 61 data, the third output of the N-th downstream port of the first chip controller hub 25 of the universal serial bus is connected to the third output of the N-th channel 61 data, the fourth output of the N-th downstream port of the first chip controller hub 25 of the universal serial bus is connected to the fourth output of the N-th channel 61 data, the third output of the controller 7 computer is connected also with the fifths conclusions of the N-th channel 61 data, the fourth output of the controller 7 computer also connected to the sixth output of the N-th channel 61 data.

As shown in figure 4, each additional extension universal serial bus contains the third and fourth signal lines 22, 23, the second common bus 65 and the second bus 67 power, the first conclusions which are respectively the first, second, third and fourth terminals of the extension universal serial bus, second third and fourth signal lines 22, 23, are connected respectively with first the m and second findings of the rising port of the third chip controller hub 27 of the universal serial bus, the second output of the third signal line 22 connected in series through fifth circuit 56 correction of the transition characteristics of the cable and the eleventh matched load 38 is connected with the third output of the rising port of the third chip controller hub 27 of the universal serial bus, a second output of the fourth signal line 23 connected in series through sixth circuit 57 correction of the transition characteristics of the cable and the twelfth matched load 39 is connected with the fourth output of the rising port of the third chip controller hub 27 of the universal serial bus, the first and second findings of the downstream port of the third chip controller hub 27 of the universal serial bus connected respectively to the fifth and sixth output extension cable universal serial bus, the first output of the downstream port of the third chip controller hub 27 of the universal serial bus connected in series through seventh circuit 58 correction of the transition characteristics of the cable and the thirteenth matched load 40 is connected with the third output of the downstream port of the third chip controller hub 27 of the universal serial bus, a second output of the downstream port of the third chip controller hub 27 of the universal serial bus is connected in series through eighth circuit 59 correction of the transition characteristics of the cable and the fourteenth matched load 41 is connected with the fourth output of the downstream port of the third chip controller the hub 27 of the universal serial bus, a second output of the second shared bus 65 is connected to the seventh output extension cable universal serial bus, with the fifth output of the third chip controller hub 27 of the universal serial bus, the first conclusions of the sixth and seventh filters 50, 51, designed to reduce noise on the power supply, the first conclusions of the third stabilizer 44 voltage and the second source 70 power supply, the sixth output of the third chip controller hub 27 of the universal serial bus is connected to the second pins of the seventh filter 51, designed to reduce noise power, and a third stabilizer 44 voltage, the second output of the second bus 67 power is connected with the eighth output extension cable universal serial bus, with the second output of the sixth filter 50 is designed to reduce noise on the power supply, the third output of the third stabilizer 44 voltage and the second output of the second source 70 power.

For more understandable subsequent perception of the description of the operation of the proposed device, it is necessary to note some features of universal serial bus, see the specification [4].

In accordance with the specification universal serial bus (USB) is an industry standard extension to the architecture of the North-South Expressway is the first computer, focused on integration with peripheral devices. The USB bus provides bi-directional transmission of packets of digital data between the computer and the multiple peripheral devices in accordance with the USB 2.0 specification. Allowable segment length (length of the USB 2.0 cable from the device to the hub, or between two hubs or between the computer and the hub) up to 5 meters Restrictions on the length of the segment is dictated by the attenuation (distortion) of the pulse signal and insertion delays. Pets inclusion between your computer and peripheral devices up to 5 intermediate hubs. The maximum transmission rate of the packet of digital data between a computer and peripheral devices is 480 Mbit/s, and the minimum length of the front and slice pulse signals of 0.5 NS. The amplitude of the pulse signals is ˜0.4 V, which provides low power consumption and less noise generation in the device. High data transfer rate 480 Mbit/s requires careful matching of the output impedance of the transceivers and wave resistance lines. Transmitters at high speed (HS mode) are current sources, focusing on the presence of the resistors on the signal lines.

The device according to the present invention, operates as follows. After selecting a transmission channel given the s and non peripherals (see 3) is setting the direction of data transfer between the controller 7 of the personal computer 1 to the controller selected PU in accordance with the USB 2.0 specification. For example, control Desk 1 incorporates thermal transfer mode from the controller 7 to the personal computer 1 to the control Desk 1 incorporates thermal transfer of the packet of digital data from the first and second pins of the controller 7 of the computer 1, respectively on the first and second findings of the rising port of the first chip controller hub 25 of the universal serial bus, which transmits the packet of digital data respectively to the first and the second output of the first downstream port of the first chip controller hub 25 of the universal serial bus. With the first and second output of the first downstream port of the first chip controller hub 25 of the universal serial bus packets of digital data are transmitted respectively to the first and the second output of the first channel 60 of the data transmission, and further, through the L series-connected extension cable is a universal serial bus, with the fifth and sixth of the conclusions of the last L-th extension 63 universal serial bus are transmitted respectively to the first conclusions of the first and second signal lines 3 and 4. Second findings of the first and second signal lines 3, 4 packets of digital data are transmitted respectively to the first the second the conclusions of the rising port of the second chip controller hub 26 universal serial bus, which transmits the packet of digital data respectively to the first and second findings of the first downstream port of the second chip controller hub 26 universal serial bus, and then with the first and second findings of the first downstream port of the second chip controller hub 26 universal serial bus packets are transmitted respectively to the first and second findings of the first controller 8 of the first peripheral device 2.

When another channel number and another number of the peripheral device is selected downstream port of the first chip controller hub 25 of the universal serial bus corresponding to the selected data transmission channel, and downstream port of the second chip controller hub 26 of the universal serial bus in the selected channel corresponding to a number of peripheral devices.

In transmission mode, from the controller 7 to the personal computer 1 to the peripheral device, the first and second findings of the downstream ports of the chipset controller hubs 25, 26, 27 universal serial bus are a source of pulse current, are connected to external concerted load, and the first and second findings of the ascending ports chipset controller hubs 25, 26, 27 universal serial bus receivers are packages digital is new data.

In transmission mode, from the peripheral devices to the controller 7 of the personal computer 1, the first and second findings of the downstream ports of the chipset controller hubs 25, 26, 27 universal serial bus are receivers of packets of digital data and the first and second findings of the ascending ports chipset controller hubs 25, 26, 27 universal serial bus are a source of pulse current, are connected to external concerted load. Therefore, the first and second conclusions all ports chipset controller hubs 25, 26, 27 universal serial bus connected external concerted load 28, ..., 41. The agreed value of the loads is equal to the wave resistance of the cable used and therefore, the device ensures reliable transmission of data without the reflection of signals in the signal lines 3, 4, 22, 23 cable. The first and second findings of the signal lines 3, 4, 22, 23 cables connected to the consistent loads 30, ..., 33, 38, ..., 41 through the appropriate circuit 52, ..., 59 correction of the transition characteristics of the cable. Having agreed external loads 30, ..., 33, 38, ..., 41 allows you to negotiate different types of cables with different wave impedance. Scheme 52, ..., 59 correction of the transition characteristics of the cable allow you to adjust the transient response of the cable on the site IU the slow rise and therefore significantly improve the shape of the pulse signals into digital packets of information. Serial connection circuit correction of the transition characteristics of the cable and consistent load allows you to adjust the transient response of the cable without reducing the amplitude of the pulse signals.

Figure 5 presents the waveform of the pulse signal at the output of the signal line without correction schemes of the transition characteristics of the cable. Figure 6 presents the waveform of the pulse signal at the output signal line from the correction circuits of the transition characteristics of the cable. Waveform analysis shows a significant improvement in the form of a pulse signal and having a steep front and a slice of the pulse using the serial connection circuit correction of the transition characteristics of the cable with a matched load. Signal line cable is bidirectional transmission lines. Therefore, to ensure the identity of the form of pulse signals when they are transmitted in different directions, the correction patterns of the transition characteristics of the cable and consistent loads are determined at the beginning and at the end of the signal lines. The incoming pulse signals with steep fronts and cut into the first and second findings ports chipset controller hubs 25, 26, 27 universal serial bus operating in the receive mode, allows the shape of the output pulse signals, not for issuu from the transmitted information, therefore, to reduce the jitter of the pulse signals into digital packets of information.

When using long transmission lines is the supply voltage drop on the power bus that affects the magnitude of the threshold komprimovane receiver in the chip controllers, hubs 25, 26, 27 universal serial bus. As a result, when the canopy front and slice pulse signal that affects the change of pulse duration in digital packets of information, and therefore increases the jitter of the pulse signals. The use of stabilizers 42, ..., 44 and voltage source 69, 70 power allows you to maintain the value of the supply voltage by changing the length of the cable, and consequently, to reduce the jitter of the pulse signals.

When the length of transmission lines increases the length of the front and slice pulse signal, and the presence of noise on the power leads to an increase in noise on the pulse signal and to an increase in the jitter of the pulse signals into digital packets of information. Connect a filter 45, ..., 51, designed to reduce noise on the power to the first and second output power bus and to the stabilizers 42, ..., 44 voltage reduces the noise power, and hence the jitter of the digital signal.

The transmission of data packets from the peripheral device 2 to the personal computer 1 is proizvoditsa in the sequence, reverse the above.

This allows us to achieve significantly better compared to the prototype of the technical results:

1) to increase the maximum data transmission speed between the computer and peripheral devices 40 times up to 480 Mbit/s

2) to increase the number of data channels with podklyuchenie peripheral devices,

3) increase the length of the cable which can be transmitted in packets of digital information, including high speed, to a value limited only by the Protocol of data exchange in the serial bus. This is done by increasing three times the length of each segment of the universal serial bus (each of the signal lines 3, 4, 22, 23) in the device data to a value of 15 meters (i.e. increased three times compared to the USB 2.0 specification to the length, limited only by the Protocol of data exchange in the serial bus in accordance with the specification of this tyre), and use different types of cable and coordinate their wave resistance.

Conducted patent studies have shown that the set of features of the present invention is a novel that proves the novelty of the claimed device. In addition, patent research showed that in the literature there are no data showing the impact of otlichitelnym characteristics of the claimed invention to the achievement of the technical result which confirms the inventive step of the proposed device.

This set of distinctive features allows you to achieve the mentioned technical result.

High-speed multi-channel device for transmitting data between a computer and peripheral devices, made in the form of universal serial bus, according to the invention can find wide application not only in home computer networks and in networks with different types of peripheral devices located at a considerable distance from each other.

Literature

1. M.Dolle, A Dynamic Line-Termination Circiut for Multireceiver Nets, IEEE Journal on Solid-State Circuits, vol. NO.12, December 1993, p. 1370-1373.

2. Han Shu, Usb Multi-Function Connecting Device, United States Patent 6058441, May 2, 2000.

3. RF patent №2275682.

4. Universal Serial Bus Specification Revision 2.0 A.

http : //www.usb.org/developrs/docs/usb_20_040907.zip

1. High-speed multi-channel device for transmitting data between a computer and peripheral devices, made in the form of universal serial bus, includes cable with signal lines, a power bus, the controller chip of the computer that generates the commands that define the operation of peripheral devices, the controller chip of the first device that controls the directions of flows of the transferred data located in the first peripheral device that is different is eat, it includes the first chip controller hub universal serial bus, in which the first and second findings of the rising port connected respectively with the first and second pins of the controller computer, and also connected respectively through the first and second agreed load with the third and fourth conclusions of the rising port of the first chip controller hub universal serial bus, a third output circuits of the controller computer is a General output and is connected to the fifth output of the first chip controller hub universal serial bus, the first output of the first voltage regulator, the first conclusions of the first and second filters for noise reduction on diet, the sixth output of the first chip controller hub universal serial bus is connected to the second pins of the first filter designed to reduce noise on the power supply and the first voltage, the fourth output circuits of the controller of a computer is the power supply pin and connected with the second output of the second filter designed to reduce noise on the power, and the third output of the first voltage regulator, and N data channels, each j-th of which contains L series-connected extension of the University of the universal serial bus, including the first extension universal serial bus, intermediate (s=2, L-1) extension cables universal serial bus and the last L-th extension cable, universal serial bus, while the first and second findings of the first extension universal serial bus are respectively the first and second terminals of the data transmission channel, the first output of the first extension universal serial bus through the first correction pattern transition characteristics of the cable is connected to the first output of the third of the agreed load, a second output which is connected to the third output data channel, the second terminal of the first extension universal serial bus through the second correction pattern transition characteristics of the cable is connected with the first output of the fourth agreed load, a second output which is connected to the fourth output data channel, the third and fourth findings of the first extension universal serial bus connected respectively with the first and second findings of the third filter designed to reduce noise on the power, and are respectively the fifth and sixth terminals of the data transmission channel, the first, second, third and fourth conclusions s-th (s=2, ..., L-1) extension universal serial bus connected line is connected with the fifth, the sixth, seventh and eighth pins (s-1)-th extension universal serial bus, and the fifth, sixth, seventh and eighth conclusions s-th extension universal serial bus connected respectively to the first, second, third and fourth output (s+1)-th extension universal serial bus, fifth and sixth conclusions the last L-th extension universal serial bus connected respectively with the first conclusions of the first and second signal lines, seventh and eighth conclusions the last L-th extension universal serial bus connected respectively with the first conclusions of the first shared bus and the first power rail, the second the conclusions of the first and second signal lines are connected respectively with the first and second findings of the rising port of the second chip controller hub universal serial bus, a second output of the first signal line connected in series through the third correction pattern transition characteristics of the cable and a fifth matched load is connected to the third output of the rising port of the second chip controller hub universal serial bus, a second output of the second signal line connected in series through the fourth correction pattern transition characteristics of the cable and the sixth matched load soedinenie with the fourth output of the rising port of the second chip controller hub universal serial bus, the second output of the first shared bus is connected to the fifth output of the second chip controller hub universal serial bus, the first findings from the fourth and fifth filters for noise reduction on diet, the first findings of the second voltage and the first power source, the sixth output of the second chip controller hub universal serial bus is connected to the second pins of the fifth filter designed to reduce noise on the power supply and the second voltage, the second output of the first power rail is connected with the second output of the fourth filter designed to reduce noise on the power supply, the third output of the second voltage and the second output of the first power source, each data channel contains M downstream ports of the second chip controller hub universal serial bus and M controllers M peripheral devices, each data channel to each i-th of the M downlink ports of the second chip controller hub universal serial bus connected to the corresponding i-th controller of the i-th peripheral device, the first output of each i-th of the M downlink ports of the second chip controller hub universal serial bus is connected to the first output of the i-th control the EPA of the corresponding i-th peripheral device, the second output of each i-th of the M downlink ports of the second chip controller hub universal serial bus is connected with the second output of the i-th controller corresponding to the i-th peripheral device, the first output of each of the i-th downstream port of the second chip controller hub universal serial bus is connected through appropriate this conclusion is consistent load with the third output of the same i-th port of the second chip controller hub universal serial bus, a second output of each of the i-th downstream port of the second chip controller hub universal serial bus is connected through appropriate this conclusion is consistent load with the fourth output of the same the i-th port of the second chip controller hub universal serial bus, the third output of each of M controllers M peripheral devices connected with the second output of the first shared bus, the fourth output of each of M controllers M peripheral devices connected with the second output of the first power rail, the first and second findings of the first downstream port of the second chip controller hub universal serial bus connected respectively with the first and second findings of the first controller of the first peripheral device, the first output of the first what about the downstream port of the second chip controller hub universal serial bus is connected through the seventh consistent load corresponding to the first output of the first downward port of the second chip controller hub universal serial bus with the third output of the first downstream port of the second chip controller hub universal serial bus, a second output of the first downstream port of the second chip controller hub universal serial bus is connected through eighth consistent load corresponding to the second output of the first downstream port of the second chip controller hub universal serial bus with the fourth output of the first downstream port of the second chip controller hub universal serial bus, the third and fourth findings of the first controller of the first peripheral device is connected respectively with the second pins of the first shared bus and the first power rail, the first and second findings of the M-th downward port of the second chip controller hub universal serial bus connected respectively with the first and second findings of the M-th controller M-th peripheral device, the first output of the M-th downward port of the second chip controller hub universal serial bus is connected through ninth consistent load corresponding to the first output of the M-th downward port of the second chip controller hub universal serial bus with the third output of the M-th nicholasroberts second chip controller hub universal serial bus, the second output of the M-th downward port of the second chip controller hub universal serial bus is connected via a tenth consistent load corresponding to the second output of the M-th downward port of the second chip controller hub universal serial bus with the fourth output of the M-th downward port of the second chip controller hub universal serial bus, the third and fourth conclusions M-th controller M-th peripheral devices connected respectively with the second pins of the first shared bus and the first power rail, the first hub controller chip universal serial bus contains N downstream ports, which correspond to the N data channels, each j-mu of N downstream ports of the first chip controller hub universal serial bus connected to the corresponding j-th channel data, the first output of each of the j-th of the N downstream ports of the first chip controller hub universal serial bus is connected to the first output of the corresponding j-th channel data, the second output of each of the j-th of the N downstream ports of the first chip controller hub universal serial bus is connected to vtorym output of the corresponding j-th data channel, the third conclusion of each j-th of N falling the x port of the first chip controller hub universal serial bus connected to a third output corresponding to the j-th data transmission channel, the fourth conclusion of each j-th of the N downstream ports of the first chip controller hub universal serial bus is connected to the fourth output of the corresponding j-th data channel, the third output of the controller computer is connected also with the fifths conclusions N data channels, the fourth output controller computer is connected also with sixth forms conclusions N data channels, the first output of the first downstream port of the first chip controller hub universal serial bus is connected to the first output of the first channel data, the second output of the first downstream port of the first chip controller hub universal serial bus is connected with the second output of the first channel data the third output of the first downstream port of the first chip controller hub universal serial bus connected to the third output of the first channel data, the fourth output of the first downstream port of the first chip controller hub universal serial bus is connected to the fourth output of the first channel data, the third output of the controller computer is connected with the fifth output of the first channel data, the fourth output controller computer is connected also with the sixth output of the first channel data, the PE the first output of the N-th downstream port of the first chip controller hub universal serial bus is connected to the first output of the N-th data transmission channel, the second output of the N-th downstream port of the first chip controller hub universal serial bus is connected with the second output of the N-th data transmission channel, the third output of the N-th downstream port of the first chip controller hub universal serial bus connected to the third output of the N-th data transmission channel, the fourth output of the N-th downstream port of the first chip controller hub universal serial bus is connected to the fourth output of the N-th data transmission channel, the third output of the controller computer is connected with the fifth output of the N-th data transmission channel, the fourth output controller computer is connected also with the sixth output The N-th channel data.

2. High-speed multi-channel device for transmitting data between a computer and peripheral devices, made in the form of universal serial bus, according to claim 1, characterized in that each of the said extensions universal serial bus contains a third and a fourth signal line, the second common bus and the second power rail, the first conclusions which are respectively the first, second, third and fourth terminals of the extension universal serial bus, second third and fourth signal lines connected respectively with the first and second the m conclusions the rising port of the third chip controller hub universal serial bus, the second output of the third signal line connected in series through the fifth correction pattern transition characteristics of the cable and the eleventh matched load is connected to the third output of the rising port of the third chip controller hub universal serial bus, a second output of the fourth signal line connected in series through sixth correction pattern transition characteristics of the cable and the twelfth matched load is connected also with the fourth output of the rising port of the third chip controller hub universal serial bus, the first and second findings of the downstream port of the third chip controller hub universal serial bus connected respectively to the fifth and sixth output extension cable universal serial bus, the first output of the downstream port of the third chip controller hub universal serial bus connected in series through the seventh correction pattern transition characteristics of the cable and the thirteenth matched load is connected to the third output of the downstream port of the third chip controller hub universal serial bus, a second output of the downstream port of the third chip controller hub universal serial bus through consequently the United eighth correction pattern transition characteristics of the cable and the fourteenth matched load is connected also with the fourth output of the downstream port of the third chip controller hub universal serial bus, a second output of the second shared bus is connected to the seventh output extension cable universal serial bus, with the fifth output of the third chip controller hub universal serial bus, the first conclusions of the sixth and seventh filter designed to reduce noise on the power supply, the first conclusions of the third voltage and the second power source, the sixth output of the third chip controller hub universal serial bus is connected to the second pins of the seventh filter designed to reduce noise on the power, and the third voltage, the second output of the second power rail is connected to the eighth output extension cable universal serial bus, with the second output of the sixth filter designed to reduce noise on the power supply, the third output of the third voltage and the second output of the second power source.



 

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The invention relates to computing and information exchange in computer network

FIELD: systems and method for software control of access between one or more nodes and multiple devices connected thereto.

SUBSTANCE: system has system of parallel used memorizing devices and node, programmed for identification of each memorizing device and masking access from node to at least one memorizing device. System for controlling access to multiple memorizing devices in system of memorizing devices has node, programmed for determining, whether for each of multiple memorizing devices masking should be performed relatively to node and interface for selective modification of programmed data structure. Method describes operation of system for controlling access to multiple parallel use memorizing devices by multiple computers.

EFFECT: possible concurrent transfer of frames in both directions at speed, exceeding 1 Gbit per second, for distance over 10 km.

6 cl, 13 dwg

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