Field mis transistor

FIELD: electricity.

SUBSTANCE: in field MIS transistor drain and source regions each contain two serially connected sections, the main and the additional ones, at that the main sections of drain and source regions have high concentration of alloying admixture, and additional sections that are installed between channel and main sections have low concentration of alloying admixture. Abovementioned additional sections stretch into abovementioned semiconductor wafer deeper than the abovementioned main sections and enclose these main sections inside themselves, with their overlap in semiconductor wafer, and on the surface of semiconductor wafer border of this additional section on the one side is at least superposed with projection of one of gate sides on semiconductor wafer, and from the other sides it is distant from border of protective area at the value that is not less than sum of values of width of space charge areas formed in semiconductor wafer by drain, source regions and protective area, at that projection of end areas of gate ends onto surface of semiconductor wafer is superposed with border of protective area, and all surface of semiconductor wafer is coated with dielectric, the thickness of which does not exceed gate thickness.

EFFECT: increase of resistance to external actions, percentage of proper produce, fast-action.

5 dwg

 

The invention is intended for use in integrated microelectronics in the design and manufacture of single and complementary MOS IC digital and analog applications.

Known field MOS transistor [patent USA No. 5851861, NPK 438/166, publ. 1998, "MIS semiconductor device having an LDD structure and a manufacturing method therefor" item 6 claim of the patent]containing semiconductor substrate of the first conductivity type, the gate of conductive material located on said semiconductor substrate and isolated therefrom by a dielectric layer, the area of the drain and source of the second conductivity type and the scope of protection of the first conductivity type, located in the above-mentioned semiconductor substrate having high dopant concentration relative to the concentration of dopant in the above-mentioned semiconductor substrate, and the area of the source and drain are composed of two parts with different concentration of dopant in each part, and these parts are butt-jointed to each other, and when this low area drains, the sources overlap the area of protection, and the gate is located over the channel and over the area of protection.

The disadvantages of this design of the field MOS transistor are low percentage of yield due to the presence of the relief of insulating dielectric, the occurrence of faults PR is the work of the IP in terms of external influences because of the low impurity concentration in the areas of protection, the high value of the range of values of the electrical characteristics due to variation of geometric dimensions of the channel length due to the changing geometry of the shutter on the ends during the oxidation processes occurring in the manufacture of the device, and a simultaneous change in the surface concentration of impurities in the areas of wastewater, the sources and in the field of protection, low performance due to the large magnitude of the feedthrough capacitances gate - drain formed due to the large overlap of the gate areas and protection areas drain - source overlap regions of the flow area of protection.

The closest technical solution adopted for the prototype, is a field MOS transistor [patent USA No. 6078082 And, IPC 7 01L 29/76, publ. 2001, "Field-effect transistor with multiple channel'] containing semiconductor substrate of the first conductivity type, the gate of conductive material located on said semiconductor substrate and isolated therefrom by a dielectric layer, the area of the drain and source of the second conductivity type, the drain region contains two series-connected area, one of which, the principal, has a high concentration of dopant, and an additional site located between the canal and the main plot, which has a low concentration of dopant, and the additional IP is an eye and runoff, adjacent to the stopper, covered wall to the gate dielectric.

The disadvantage of this design of the field MOS transistor are the same properties and similar, but manifested to a lesser degree, namely low resistance to external influences and understated the percentage yield of the chips due to the high magnitude of variation of the electrical characteristics due to the change of the geometric dimensions of the channel length due to the changing geometry of the shutter on the ends during the oxidation processes occurring in the manufacture of the device, and a simultaneous change in the surface concentration of impurities in the areas of wastewater, the sources and in the field of protection, low performance due to the large magnitude of the feedthrough capacitances gate the runoff generated due to the large overlap of the gate areas of protection and overlapping areas of the drain - source region of protection.

The problem to which this invention is directed, is the achievement of the technical result consists in increasing the resistance to external influences, percentage yield of products by increasing the concentration of dopant in the buffer zone, improve the reproducibility of the electrical parameters and characteristics of the elements of the MOS transistor and improve performance by reducing the quantities of migratory emkosti the MOS transistor.

The problem is solved in the field MOS transistor-containing semiconductor substrate of the first conductivity type, the gate of conductive material located on said semiconductor substrate and isolated therefrom by a dielectric layer, the area of the drain and source of the second conductivity type, in this region of the drain, source, each contain two series-connected area, primary and secondary, with the main areas of the areas of the drain and source have a high concentration of dopant, and additional land areas of the drain, source, located between the canal and the main areas that have a low dopant concentration, while above additional areas areas of the drain and the source, each located between the channel and above the main areas of the drain and the source, extend in the above-mentioned semiconductor substrate deeper than the above are the main areas of the drain and the source and make these main areas of the drain and the source within yourself, overlapping them in a semiconductor substrate and on the surface of the semiconductor substrate, the boundary of this additional area on the one hand, at least, combined with the projection of one side of the gate on a semiconductor substrate, and on the other sides is separated from the boundary area of protection on value, not IU is greater, than the sum of the width of the space-charge regions formed in the semiconductor substrate areas of the drain, the source and scope of protection, while the projection end regions of the ends of the shutter on the surface of the semiconductor substrate aligned with the border protection, and the entire surface of the semiconductor substrate including the drain, source, scope of protection, and area of a semiconductor substrate, located between the areas covered by the dielectric, the thickness of which is not greater than the thickness of the shutter, the dielectric contains the contact window, located under the metal wiring located on the dielectric, and gate.

Thus, the distinctive features of the invention are the location of the main sections of the areas of the drain, the source having a high concentration of dopant, within the land areas of the drain, the source having a low concentration of dopant, and the boundary of this additional area on the one hand, at least, combined with the projection of one side of the gate on a semiconductor substrate, and on the other sides is separated from the boundary area of protection an amount not less than the sum of the width of the space-charge regions formed in the semiconductor substrate areas of the drain, the source and scope of protection, while p is occia end regions the ends of the shutter on the surface of the semiconductor substrate aligned with the border protection and the entire surface of the semiconductor substrate including the drain, source, scope of protection, and area of a semiconductor substrate, located between the areas covered by the dielectric, the thickness of which is not greater than the thickness of the shutter, the dielectric contains the contact window, located under the metal wiring located on the dielectric, and gate.

This set of distinctive features allows you to achieve the technical result consists in increasing:

resistance to external influences by increasing the concentration of dopant in the buffer zone to the maximum values, the percent yield of products by improving the reproducibility of the electrical parameters and characteristics of the elements of the MOS transistor performance by reducing the value of feedthrough capacitances of a MOS-transistor.

The invention is illustrated by drawings.

Figure 1÷5 schematically shows the topology of the field MOS transistor, a top view, and a schematic section views of the structure of the field MOS transistor.

Figure 1 schematically presents the topology of the field MOS transistor. Topology is a top view of the field MOS transistor, prior to the opening of contact Windows to the areas of the drain, source and protection

where:

1 - silicon semiconductor wafers is of the first conductivity type,

2 - insulating region between the additional drain regions 8 and the source 3 and region conservation 9,

3 - the main area of the source,

4 - additional area source, located between the shutter 6 and the main area of source 3,

5 - end of the gate,

6 - gate,

7 - additional drain region, located between the shutter 6 and the main drain region 8,

8 - the main area of flow,

9 - the scope of protection.

Figure 2 schematically shows the topology of the field MOS transistor. Topology is a top view of the field MOS transistor, opened in the dielectric contact Windows to the areas of the drain, source and protection

where:

1 is a silicon semiconductor wafer of the first conductivity type,

2 - insulating region between the additional drain regions 8 and the source 3 and region conservation 9,

3 - the main area of the source,

4 - additional area source, located between the shutter 6 and the main area of source 3,

5 - end of the gate,

6 - gate,

7 - additional drain region, located between the shutter 6 and the main drain region 8,

8 - main region

10 - pin box for protection

11 - pin box to the source,

12 - pin box to the field of flow.

Figure 3 schematically shows the topology of the field MOS transistor. Topology is above on top of the field MOS transistor, with metal wiring, creating electrical contacts to the gate and through the contact window creating electrical contacts to the drain regions, the source and protection

where:

1 is a silicon semiconductor wafer of the first conductivity type,

2 - insulating region between the additional drain regions 8 and the source 3 and region conservation 9,

3 - the main area of the source,

4 - additional area source, located between the shutter 6 and the main area of source 3,

5 - end of the gate,

6 - gate,

7 - additional drain region, located between the shutter 6 and the main drain region 8,

8 - the main area of flow,

9 - the scope of protection,

10 - pin box to the field of protection, which made contact to the field of protection 9, covered with metal wiring,

11 - pin box to the source through which made contact to the area of source 3, is covered by a metal wiring,

12 - pin box to the field of flow,

13 - the metal wiring contact to protection

14 is a metal wiring contact area of the source,

15 is a metal wiring contact area of the gate,

16 is a metal wiring contact to a region of the flow.

Figure 4 schematically shows the section structure of the field MOS transistor produced along the length of the shutter across it the width,

where:

1 is a silicon semiconductor wafer of the first conductivity type,

2 - insulating region between the additional drain regions 8 and the source 3 and region conservation 9,

3 - the main area of the source,

4 - additional area source, located between the shutter 6 and the main area of source 3,

5 - end of the gate,

6 - gate,

7 - additional drain region, located between the shutter 6 and the main drain region 8,

8 - the main area of flow,

9 - the scope of protection,

10 - pin box for protection

11 - pin box to the source,

12 - pin box to the field of flow,

13 - the metal wiring contact to protection

14 is a metal wiring contact area of the source,

15 is a metal wiring contact area of the gate,

16 is a metal wiring contact to a region of the flow.

Figure 5 schematically shows the section structure of the field MOS transistor produced along the width of the shutter across its length,

where:

1 is a silicon semiconductor wafer of the first conductivity type,

2 - insulating region between the additional drain regions 8 and the source 3 and region conservation 9,

5 - end of the gate,

6 - gate,

7 - additional drain region, located between the shutter 6 and the main drain region 8,

8 - the main area of flow,

9 - the scope of protection,

10 - pin box for protection

15 is a metal wiring contact area of the gate.

An example of a field MOS transistor.

Field MOS transistor is located on the silicon wafer 1 (Fig 1÷5) e-type conductivity with orientation (100) and a resistance of 4.5 Ω×cm, above which is the gate oxide thickness of 20 nm, which is the gate of polycrystalline silicon of a thickness equal to 0.5 μm.

The field drains and the sources of the surrounded area protection 9, which is located at a distance of not less than 3 μm from the areas of the drain and the source.

The ends of the gate of the transistor is outside of sinks and sources at the same value (figure 5).

The thickness of the dielectric matrix, which opened the contact window areas (10÷12)located in the semiconductor wafer of 0.5 μm, which allows you to contact the metallized wiring area of the gate directly, without opening the contact Windows (figure 5).

The thickness of the metal wiring (13÷16) is equal to 1 micron.

Field MOS transistor-containing semiconductor substrate of the first conductivity type, the gate of conductive material located on said semiconductor substrate and isolated therefrom by a dielectric layer, the area of the drain and source of the second type is routenote, when this region of the drain, source each include two series-connected area, primary and secondary, with the main areas of the areas of the drain and source have a high concentration of dopant, and additional land areas of the drain, source, located between the canal and the main areas that have a low concentration of dopant, characterized in that the above additional land areas of the drain and source of each located between the channel and above the main areas of the drain and the source, extend in the above-mentioned semiconductor substrate deeper than the above are the main areas of the drain and the source, and enter into these main areas of the drain and source inside myself, overlapping them in a semiconductor substrate and on the surface of the semiconductor substrate, the boundary of this additional area on the one hand, at least, combined with the projection of one side of the gate on a semiconductor substrate, and on the other sides is separated from the boundary area of protection an amount not less than the sum of the width of the space-charge regions formed in the semiconductor substrate areas of the drain, the source and scope of protection, while the projection end regions of the ends of the shutter on the surface of the semiconductor substrate aligned with the border protection, and the whole surface is here a semiconductor substrate, including the area of the drain, source, scope of protection, and area of a semiconductor substrate, located between the areas covered by the dielectric, the thickness of which is not greater than the thickness of the shutter, the dielectric contains the contact window, located under the metal wiring located on the dielectric, and gate.



 

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