Shf ldmos-transistor

FIELD: electronic equipment.

SUBSTANCE: in SHF LDMOS - transistor, which contains semi-conductor substrate with high-resistance and high-alloyed layers of the first type of conductance, elementary transistor cells in high-resistance layer of substrate with channel field of the first type of conductivity, high-alloyed source, high-alloyed and low-alloyed drain regions of the second type of conductivity, gate dielectric from thermal silica dioxide and gate electrode above channel region of transistor cells, thermal silica dioxide and interlayer dielectric above low-alloyed drain region of transistor cells, source and drain electrodes of transistor cells on the face side of substrate, field screening electrodes in the gap between drain and gate electrodes, which are connected to one of transistor cells source electrode ends outside the limits of gate electrodes, common electrode of transistor structure drain on back side of substrate, field screening electrodes of transistor cells are made of gate electrode material and are installed at the interface of thermal silica dioxide - interlayer dielectric, at that width of thermal silica dioxide above low-alloyed drain region makes (1.0-3.5) of gate dielectric width, and border of gate dielectric coupling with layer of thermal silica dioxide above low-alloyed drain region is installed under gate electrode.

EFFECT: increase of permissible limit values of electric parameters and operation modes of SHF LDMOS - transistors and provision of conditions for organisation of profitable industrial production of these items.

1 dwg, 2 tbl

 

The invention relates to electronic semiconductor technology, in particular to the structures of power silicon microwave generator LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors.

Known design power silicon n-channel UHF LDMOS transistor is selected as the analogue of (LDMOS Family. New 1GHz RF LDMOS. - Information firm "STMicroelectronics", 2000 - http://www.st.com/ST/Products Presentation/Discrete/RF/LDMOS), consisting of: silicon p-p+the substrate with the upper high resistance (R-) and lower high-alloyed (R+) layers; basic transistor cell with a p-channel, high-n+- stokovoj, high-n+-stock and low-alloy n-stock areas in the high-resistance layer of the substrate; identical to the thickness of the layer of thermal silicon dioxide over the p-channel (gate dielectric) and low-alloy stock n regions of the transistor cells; electrodes shutter in the form of narrow rectangular polysilicon strips, shunted by top cobalt silicide (CoSi2over the gate dielectric and p-channel regions of the transistor cells; an interlayer dielectric of phosphorothioates or borophosphosilicate glass over the gate electrodes and thermal silicon dioxide covering low-alloy stock n-region of the transistor cells; IU allicance electrodes of the drain and source of the transistor cells on the front side of the substrate; the shielding electrodes on the interlayer dielectric extending over the gate electrodes and partially over low-alloy stock n regions, is designed as a continuation of the source electrodes of the transistor cells; diffusion through R+-jumper in the high-resistance p-layer of the substrate under the source electrode of transistor cells; a common electrode and source of the transistor structure at the rear side of the substrate. Introduced in the transistor cell additional field shielding electrode is designed to improve the breakdown voltage of the drain at the expense of leveling capacity and reduce the maximum field strength in the region of the cutoff low-alloy stock n-layer and simultaneously to reduce the entrance (the drain-gate capacity. However, this dramatically increases the likelihood of additional Samorodok and leakage currents between the shielding and gate electrodes of transistor cells, which is a significant disadvantage of this design.

Known other design power silicon microwave LDMOS transistor (second analogue), in which the above disadvantage is largely overcome due to the fact that field-shielding electrodes are in contact with only one end of the electrodes of the source outside of the gate electrodes and overlapping the only perifery the ing part of the sealing strips (O.Ishikawa, H.Yamada, H.Ecaki. "A 2.45 GHz power LD-MOSFET with reduced source inductance by V-groove connections" - a collection of articles "International Electron Devices Meeting, Washington, 1985, December 1-4, p.167-169).

As a prototype of the selected power silicon microwave LDMOS transistor (Richmond Road "Philips BLF 2022-90 Power MOSFET Structural Analysis Suite 500, Ottawa, ONK2H5B7, Canada, June 17, 2004) identical counterparts of the set of basic structural elements, in which the polysilicon gate electrodes of the transistor cells are shunted by the top metallization coating based on gold (the material of the electrodes of the drain and source), and field-shielding electrodes made of the same metallization coating and placed on the interlayer dielectric from bravoporno-silicate glass over low-alloy area of flow at approximately the same distance from the electrodes of the drain and source. That is, in the prototype screening and gate electrodes are not completely overlap with each other throughout their length, and therefore it is devoid of the above-mentioned lack of analogues. However, for the prototype and analogues the most serious technical problem is the difficulty of ensuring the stability of the parameters, due to the likely drift of ions of alkaline metals or other undesirable impurities along the boundary of thermal silicon dioxide - interlayer dielectric on the low-alloy drain region of the transistor cells. For wt is the substance of the possibility of this adverse effect when using these devices in electronic equipment have to limit their maximum allowable values of electrical parameters and operating modes (temperature patterns, power dissipation, output power, power supply, etc). This effect also leads to a reduction in the percentage of yield structures on the plate and fit plates in the party, increasing the cost of production and, as a result, prevents the establishment of profitable commercial production of these products.

The technical result of the present invention is to increase the maximum permissible values of electrical parameters and modes of operation of the UHF LDMOS transistors and providing conditions for the establishment of profitable commercial production of these products.

The technical result is achieved by the fact that in the known design of the UHF LDMOS transistor-containing semiconductor substrate with a high resistance and high-alloy layer of the first conductivity type, the elementary transistor cells in the high resistance layer of the substrate with a channel region of the first conductivity type, high stokovoj, high-alloyed and low-alloy stock regions of the second conductivity type, the gate dielectric of thermal silicon dioxide and the gate electrode above the channel region of the transistor cells, thermal silicon dioxide and an interlayer dielectric over low-alloy stock area of the transistor cells, the electrodes of the drain and source of the transistor cell is and the front side of the substrate, field-shielding electrodes between the electrodes, drain and gate connected to one of the ends of the source of the transistor cells outside of the gate electrodes, the common electrode and source of the transistor structure at the rear side of the substrate, field-shielding electrodes of the transistor cells are made from a material of the gate electrode and is placed at the interface of thermal silicon dioxide - interlayer dielectric, and the thickness of thermal silicon dioxide over low-alloy region of the flow is (1,0 3,5...) the thickness of the gate dielectric and the interface between gate dielectric and a layer of thermal silicon dioxide over low-alloy stock region located under the gate electrode.

Comparative analysis with the prototype shows that the claimed design is different: the new material of the field-shielding electrodes of the transistor cells and the new location field shielding electrode in the active region of the transistor structure; new, strictly regulated by the ratio between thicknesses of the gate dielectric and thermal silicon dioxide over low-alloy region of the drain of transistor cells; the presence of additional the interface between gate dielectric and a layer of thermal dioxide to amnia over low-alloy stock area of the transistor cells and it is strictly regulated by the location in the active region of the transistor structure. Thus, the claimed design meets the criteria of the invention of "novelty."

Perform field-shielding electrodes from a material of the gate electrodes (in the prototype and the equivalent of the material of the electrodes of the drain and the source) allows you to place the shielding electrodes are not on the interlayer dielectric (as in the prototype and analogues), and at the interface thermal silicon dioxide - interlayer dielectric on the low-alloy drain region of the transistor cell.

The implementation of screening and gate electrodes of the same material, placement of the shielding electrodes at the interface thermal silicon dioxide - interlayer dielectric, in conjunction with the passivation thermal silicon dioxide over low-alloy stock area phosphorothioate glass and possible additional stabilization of thermal silicon dioxide by introducing into it a low-energy ions of phosphorus or arsenic, allow to reduce to zero the probability of drift of ions of alkaline metals or other undesirable impurities between the drain electrodes and the gate of transistor cells along the boundary of thermal silicon dioxide - interlayer dielectric and get thus from the primary disadvantage of the prototype and designs in its class.

Regulated by the claims di is the range of ratios between the thicknesses Pastorova dielectric and thermal silicon dioxide over low-alloy region of the drain of transistor cells, first, it provides an effective stabilization of these layers of thermal silicon dioxide phosphorothioate glass in a single technological process and, secondly, by the partial output of gate electrodes on a thicker (in the extreme case up to 3.5-fold) compared to the gate dielectric layer of thermal silicon dioxide over low-alloy stock area of the transistor cells avoids breakages gate electrodes on the steps of oxide at the interface of thin and thick dielectrics. Minimum thickness of thermal silicon dioxide over low-alloy stock area depends on its dielectric strength (106...107In/cm) and should exclude the possibility of dielectric breakdown under the shielding electrodes when applying to stock the transition maximum allowable for the transistor structure voltage drain-source Usi maxThus, when the dielectric strength of silicon dioxide ESiO2=3·106V/cm and Usi max=80 minimum thickness of thermal silicon dioxide over low-alloy stock area dSiO2min should be less of 0.27 μm. At ESiO2=8·106V/cm and Usi max=80 In dSiO2 min≅0.1 µm, and in this case, thermal silicon dioxide over the channel and low-alloy the current regions of the transistor cells can be formed in the same thickness in a single technological process.

Regulated by the claims of the invention the location of the boundaries of the pair of gate dielectric with a layer of thermal silicon dioxide over the low-alloy drain region of the transistor cells is dictated in order to minimize the capacitance gate-drain transistor structure and does not degrade the gain in power.

In the present invention is a new material used for the field-shielding electrodes of the transistor cells, the new location of the shielding electrode in the active region of the transistor structure, a new relation between thicknesses of the gate dielectric and thermal silicon dioxide over low-alloy stock area of the transistor cells is strictly regulated the location of the interface between gate dielectric and a layer of thermal silicon dioxide over low-alloy stock area of the transistor cells, provide the ability to create powerful silicon UHF LDMOS transistors identical to the prototype and analogues frequency properties and energy parameters (given in the load capacity of Po, gain power Tour, efficiency stock chain ηc), but having compared them with the higher performance n what dinasty and higher maximum values of electrical parameters and operating modes, that is, manifests a new technical property. Therefore, the claimed design meets the criterion of "inventive step".

This invention also essential, as it provides a significant technical effect, i.e. sustainable profitable industrial output power silicon microwave LDMOS transistors with operating frequencies up to 2,0...2,5 GHz and the level given in the load capacity up to 100...200 watts, opening new perspectives in the solution of important problems of complex microminiaturization electronic equipment, the improvement of its feasibility and mass-dimensional characteristics.

The drawing shows a cross section structure of the claimed UHF LDMOS transistor according to the invention, where we have introduced the following notation:

1 is a semiconductor substrate;

2 - high resistance layer of the substrate;

3 - alloyed layer of the substrate;

4 - alloyed ishikawae region of the transistor cells;

5 - channel region of the transistor cells;

6 - alloyed stock region of the transistor cells;

7 - low-alloy stock region of the transistor cells;

8 is a cross-cutting high-alloy diffusion jumper in the high-resistance layer of the substrate;

9 - gate dielectric of thermal silicon dioxide;

10 is a layer of thermal silicon dioxide over low-alloy region of the drain of transistor cells;

11 - the source electrode of transistor cells;

12 - electrode of the gate transistor cells;

13 - field shielding electrode of transistor cells;

14 - the drain electrode of transistor cells;

15 - interlayer dielectric from phosphorothioates or borophosphosilicate glass;

16 - the metal wire connecting end portion of the shielding and stokovyh electrodes of the transistor cells outside of the gate electrodes;

17 - the metal wire connecting the gate electrodes of the transistor cells in a single system;

18 - induced channel;

19 - the common electrode and source of the transistor structure;

20 - boundary thermal silicon dioxide - interlayer dielectric on the low-alloy drain region of the transistor cells;

21 - interface Pastorova dielectric with a layer of thermal silicon dioxide over the low-alloy drain region of the transistor cell.

Example

To implement the claimed design and prototype-specific products was designed set of photomasks A3926 and based on fabricated samples generator power silicon n-channel UHF LDMOS transistors with a step structure 38 μm (in this case, at the step structure refers to the distance between the centers of high-alloy n+-stokovyh or n+-stock areas is transistory cells) and the length of the induced n-channel L Kahn=0,85...0.9 µm, designed to operate in the frequency range up to 2.0...2.5 GHz mode class AB in the circuit with a common source when the voltage on the drain Uc Pete=28...40 Century. and Those other devices were fabricated simultaneously in a single process using as the starting material silicon p-p+-substrate orientation (100) with the upper high resistance epitaxial R--layer (2) of thickness hp=6,5...of 7.0 μm and a resistivity of ρp=15...17 Om·cm and the lower alloyed p+-layer with hp+=380...400 μm and ρR+=0.03 Ohm·see Alloyed ishikawae (4) and a drain (6) n+-the field of transistor cells with a thickness of 0.25...0.4 µm and 0.8...of 1.0 μm was formed by introducing ions into the substrate of arsenic and phosphorus, the p-channel region (5) - implantation of boron ions, low-alloy stock n--region (7) thickness of 0,25...0,5 ám - implantation of arsenic ions and phosphorus, high end-to-end ishikawae p+-jumper (8) in the high resistance R-layer of the substrate (2) - spin-boron solid source (boron nitride) with subsequent diffusion justify impurities in the atmosphere of nitrogen and oxygen at a temperature of 1100°C. the Gate dielectric (9) of thermal silicon dioxide with a thickness of 0.08...of 0.15 μm and a layer of silicon dioxide (10) over low-alloy n-the scope of the current unit cells (7) thickness of 0.15...of 0.4 μm (in the present UHF LDMOS-transistor) formed by thermal oxidation of silicon in an environment of dry oxygen and water vapor at T=975° With subsequent simultaneous passivation dielectrics (9) and (10) phosphorothioate glass (diffusion of phosphorus from metaphosphate aluminum at T=970°With a nitrogen atmosphere). In the prototype layer of silicon dioxide (10) formed simultaneously with the gate dielectric (9) and served as its natural extension. The gate electrodes (12) of the transistor cells and the shielding electrodes (13) [the claimed design LDMOS transistor] in the form of narrow longitudinal strips of a width of 2.7...3.0 mm, a thickness of 0.2...0.25 μm and a length of 74 microns was created simultaneously from a pre-printed on the front side of the substrate magnetron sputtering of molybdenum by photolithography. The gate electrodes (12) in the inventive LDMOS-transistor partially (0.4...0.8 μm) were on the layer of thermal silicon dioxide (10)and the interface with the last gate dielectric (21) was located under the gate electrodes (12) and 0.1...0.3 microns separated from the p-channel region (5) of transistor cells. The shielding electrodes (13) in the inventive structure was located at the interface (20) of thermal silicon dioxide (10) - interlayer dielectric (15), and interlayer dielectric (15) of a thickness of 0,5...0,6 µm consisted of pyrolytic silicon dioxide and phosphorothioates glass. The source electrodes (11) and drain (14) transistor cell bus (16)connecting the ends stokovyh and shielding ele is trudov, the connecting bolt bus (17), coupling stock tires, pads, drain and gate (not shown), and the shielding electrodes (13) in the prototype were made simultaneously from a pre-printed on the front side of the substrate a single layer of aluminum or three-layer Ti-Pt-Au coating thickness 1,0...1,5 μm by photolithography. The shielding electrodes (13) in the prototype was placed not on the boundary (20), and the interlayer dielectric (15) under the top protective dielectric coating (not shown). The common electrode and source of the transistor structure (19) was formed after thinning of the crystal to a thickness of 120...150 μm and the heat soldering on the surface of the sintered body CT-25 with gold strip thickness of 20 μm at a temperature of 400...430°With inert gas. The channel of n-type conductivity (18) were induced at the ends of the p-channel regions (5)adjacent to the front surface of the transistor structure, when applying a positive voltage to the gate electrode. In the inventive design and prototype of a transistor structure with a size of 1.6 mm × 4.2 mm was included in 40 packages of elementary transistor cells, separated from each other by a thick (2,0...2,5 µm) layer of thermal silicon dioxide, 11 stock and 10 packing sites, accommodated the thick dielectric coating between packages transistor cells and intended for connection to a crystal, an external wire leads. Each package transistor cells contained 24 of the gate electrode (12), the total length of which was ˜1780 μm. The total length of the gate electrodes of the whole crystal (channel width) was ˜7,2 see

Electrical parameters made LDMOS structures (the claimed design, prototype) with different combination of the thicknesses of thermal silicon dioxide over the p-channel [dSiO2(p)] and low-alloy p--stock [dSiO2(p-)] areas of elementary transistor cells, measured directly on the plates, are presented in table 1. On LDMOS structures before and after exposure in the beginning of the 1st (UC=40 V, Uzi=0, the ambient temperature TOCD=150°s, time t=3 min), then 2nd (UC=80 V, Uzi=0, TOCD=150°S, t=3 min) speed load was measured: the breakdown voltage of stock RP-transition (Uwith samples) when voltage gate-source Uzi=0 at the level of current flow Iwith=3 mA; initial drain current (1 from the beginning) when the voltage of the drain-source UC=40 V and Uzi=0; threshold voltage (Uzi long) when the voltage UC=20 and Iwith=3 mA; residual voltage drain-source (Uc OST) when UC=20 and Ic=1 A. Pre plates were zabrakovyvali all LDMOS structure with leakage current gate IC ut>10 And, unstable gate node (instability was estimated by the shift of the threshold voltage when exposed to the structure of thermal and electrical loads) and parameter values Uc samples, Ifrom the beginningUzi longUc OSTother than those specified in table 1. During the tests identified:

1. When regulated by the claims ratios of the thicknesses dSiO2(p-)/dSiO2(p)=1,0 3,5...test parameters Uc samples, Ic nachUzi longUc OSTdeclare LDMOS structures after exposure to two levels of load remained unchanged.

2. The ratio of thickness dSiO2(p-)/dSiO2(p)>3.5 in the claimed design LDMOS transistor is not optimal (because of the complexity of simultaneous passivation of gate dielectric and thermal silicon dioxide over low-alloy stock p-the area of the transistor cells phosphorothioate glass), as in this case, after exposure to 1-St and 2-nd stages load 8,0...15% of test structures (table 1 marked with*), the tendency was to 10...15% growth values Uc OSTwith respect to the initial value of this parameter. Some structures were observed breakage of the metallization of the electrodes of the shutter on the steps of oxide at the interface of thin and thick layers of thermal dioxide credit the deposits.

3. After the impact load at all tested LDMOS structures of the prototype, the residual voltage drain-source increased by at least 10...15% relative to the initial value Uwith OSTand 15 percent of the structures after the 1st stage load and 35 percent of the structures after the 2nd stage load (table 1 marked with *) Uwith OSTincreased respectively 1.47 and 1.65 times.

For further research were selected and mounted in a small metal-ceramic housing with use strip conclusions and flat flange type CT-25 sixty samples LDMOS structures of the claimed design with the thickness ratio of thermal silicon dioxide dSiO2(p-)/dSiO2(p)=1,0; 2,5; 3,5 (20 pieces each liposomial) and 40 samples LDMOS structures of the prototype with dSiO2(p)=dSiO2(p-)=1000 Å (20 pieces) and dSiO2(p)=dSiO(p)=1500 Å (20 pieces), in which the care of a residual voltage drain-source after the 2nd stage of the load with respect to the initial values Uwith OSTamounted to no more than 15%. The assembled devices were exposed to 4-speed load and directly after each of them on the devices was measured: the drain current Iwithat voltages UC=15 V and Uzi=20 V resistance drain-source open (Rsi OTC) at voltages Uzi=20 and UC=1; energy is ski options - output power Pothe gain in power Tour(dB), efficiency stock chain ηwith(%) at the frequency f=1000 MHz at a supply voltage Uwith Pete=40 W mode class AB in the circuit with a common source. Previously on the devices was measured thermal resistance of the transfer - case (RTPK), which in this case was equal to ˜2,3°S/W. At each step load LDMOS transistors was aged for t=10 minutes at a voltage of the drain-source UC=40, the housing temperature TCorp=20°and the load current ICHor an equivalent amount dissipated by the power transistor PRuss=UC·ICHwas chosen such that, proceeding from the known ratio of ICH=(Tp-TCorp)/UC·RTPKtemperature patterns (crystal) Tpreached 150°C 170°, 190°and 210°With respectively the 1st, 2nd, 3rd and 4th stages of loading.

Presented in table 2 test results we can draw the following conclusions:

1. In LDMOS-FET of the claimed design under test options - Iwith, Rsi OTC, Roremain unchanged after exposure to all 4-speed load and therefore as the maximum allowable may be adopted by the temperature structure of the tours T p max=200°C.

2. In LDMOS-FET prototype testing options - Po, Iwith, Rsi OTCbegin to degrade at the temperature structure Tp=170°and after exposure to 4-Oh-stage load (Tp=210° (C) these parameters are changed relative to their values at Tp=150°With approximately 1.26...1.31 times. Therefore, for the prototype as a maximum can be accepted temperature structure Tp max≤150°C.

The gain in power (Kurand the efficiency of stock chain (ηwith) in the tested samples of the prototype and LDMOS transistors of the claimed design were comparable Tour=13...14 dB, ηwith=43...44% (table 2 not specified).

Technical and economic efficiency of the proposed design compared to the prototype consists of:

- the possibility of increasing the maximum allowable values of electrical parameters and modes of operation (temperature patterns, power dissipation, output power LDMOS RF power transistor;

- the possibility of reducing the cost and increasing the percentage of yield LDMOS structures on the plate and, as a result, in the provision of conditions for the establishment of profitable industrial output microwave power silicon LDMOS transistors new is ocalenia with enhanced reliability.

Table 1
Type LDMOS structuredSiO2 (p)< / br>
Å
dSiO 2(n-)< / br>
Å
Initial settings1st stage load: UC=40 V, Uzi=0, TOCD=150°S, t=3 min2nd stage load: UC=80 B, Uzi=0, TOCD=150°S, t=3 min
Uc samplesIn (Uzi=0, Ic=3 mA)Ifrom the beginningmA (UC=40B, Uzi=0)Uzi longIn (UC=20B, Iwith=3 mA)Uc OSTB (UC=20B, Ic=1 A)Uc samplesIn (Uzi=0, Iwith=3 mA)Ic nachmA (UC=40B, Uzi=0)Uzi longIn (UC=20B, Ic=3 mA)Uc OSTIn (UC=20B, Ic=1 (a)Uc samplesIn (Uzi=0, Iwith=3 mA)Ic nachmA (UC=40B, Uzi=0)Uzi longIn (UC=20B, Iwith=3 MA)Uwith OSTIn (UC=20B, Ic=1 A)
In accordance with the invention1000250089...910,1...0,8...2,3 2,10,85...0, 89...910,1...0,8...2,3 2,10,85 0,9...89...910,1...0,8...2,3 2,10,85 0,9...
1000350089...910,1...0,8...2,3 2,10,85 0,9...89...910,1...0,8...2,3 2,10,85 0,9...89...910,1...0,8...2,3 2,10,85 0,9...
1000370089...910,1...0,8...2,3 2,10,85 0,9...89...910,1...0,8...2,3 2,10,85...0,93* (*8%)89...910,1...0,8...2,3 2,10,85...0,98* (*12%)
1500150089...910,1...0,8...2,3 2,10,85 0,9...89...910,1...0,8...2,3 2,10,85 0,9...89...910,1...0,8...2,3 2,10,85 0,9...
The placeholder1000100089...910,1...0,8...2,3 2,10,85 0,9...89...910,1...0,8...2,3 2,10,95...1,25* (*15%)89...910,1...0,8...2,3 2,10,98...1,4* (*35%)
15001500 89...910,1...0,8...2,3 2,10,85 0,9...89...910,1...0,8...2,3 2,10,95...1,25* (*15%)89...910,1...0,8...2,3 2,10,98...1,4* (*35%)

Table 2
Device typedSiO2 (aq)< / br>
Å
dSiO2 (n-)< / br>
Å
Tp=150°C (Ucu=40B; ICH=1,41; Ppac=56,5 W; RTPK=2,3°C/W; Tcor=20°C; t=10 min)Tp=170° (UC=40; ICH=1,63; Ppac=65,2 W; RTPK=2,3°C/W; Tcor=20°C; T=10 min)Tp=190° (UC=40 B; ICH=1,84; Ppac=73,9 W; RTPK=2,3°C/W; Tcor=20°C; t=10 min)Tp=210° (UCH=40; ICH=2,11; Praces=82,6 W; RTPK=2,3°C/W; Tcor=20°C; t=10 min)
IcThat A (UC=15B, Uzi=20)Rsi OTCThat ω (Uzi=20 V, UC=1 In)Pout, W (f=1000 MHz, UcPete=40B, CL AVI)IcThat A (UC=15B, Uzi=20)Rsi OTCThat ω (Uzi=20 V, UC=1 In) Pout, W (f=1000 MHz Uc Pete=40, CL AVI)IcThat A (UC=15 V, Uzi=20)Rsi OTCThat ω (Uzi=20 V, UC=1 In)Pout, W (t=1000 MHz, Uc Pete=40, CL AVI)IcThat A (UC=15 B, Uzi=20)Rsi OTCThat ω (Uzi=20 V, UC=1 In)Pout, W (f=1000 MHz, Uc Pete=40, CL AVI)
The claimed design100025009,8 10,2...0,82 0,8...36...379,8 10,2...0,82 0,8...36...379,8 10,2...0,82 0,8...36...379,8 10,2...0,82 0,8...36...37
100035009,8 10,2...0,82 0,8...36...379,8 10,2...0,82 0,8...36...379,8 10,2...0,82 0,8...36...379,8 10,2...0,82 0,8...36...37
150015009,8 10,2...0,82 0,8...36...379,8 10,2...0,82 0,8...36...379,8 10,2...0,82 0,8...36...379,8 10,2...0,82 0,8...36...37
The placeholder100010009,8 10,2... 0,82 0,8...36...379,3...9,70,83...0,8634...358,9...9,10,9...0,9330...32...8,0 7,50,98...1,127...29
150015009,8 10,2...0,82 0,8...36...379,3...9,70,83...0,8634...358,9...9,10,9...0,9330...32...8,0 7,50,98...1,127...29

UHF LDMOS transistor-containing semiconductor substrate with a high resistance and high-alloy layer of the first conductivity type, the elementary transistor cells in the high resistance layer of the substrate with a channel region of the first conductivity type, high stokovoj, high-alloyed and low-alloy stock regions of the second conductivity type, the gate dielectric of thermal silicon dioxide and the gate electrode above the channel region of the transistor cells, thermal silicon dioxide and an interlayer dielectric over low-alloy stock area of the transistor cells, the electrodes of the source and drain of transistor cells on the front side of the substrate, field-shielding electrodes between the electrodes, drain and gate connected to one of the ends of the source electrode transistor cells out of gate electrodes, the common electrode and source of the transistor structure at the rear side of the substrate, wherein the field-shielding electrodes of the transistor cells are made from a material of the gate electrode and is placed at the interface of thermal silicon dioxide - interlayer dielectric, and the thickness of thermal silicon dioxide over low-alloy area of flow is 1.0-3.5 thickness of the gate dielectric and the interface between gate dielectric and a layer of thermal silicon dioxide over low-alloy stock region located under the gate electrode.



 

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4 cl, 2 dwg

FIELD: electronic equipment.

SUBSTANCE: in SHF LDMOS - transistor, which contains semi-conductor substrate with high-resistance and high-alloyed layers of the first type of conductance, elementary transistor cells in high-resistance layer of substrate with channel field of the first type of conductivity, high-alloyed source, high-alloyed and low-alloyed drain regions of the second type of conductivity, gate dielectric from thermal silica dioxide and gate electrode above channel region of transistor cells, thermal silica dioxide and interlayer dielectric above low-alloyed drain region of transistor cells, source and drain electrodes of transistor cells on the face side of substrate, field screening electrodes in the gap between drain and gate electrodes, which are connected to one of transistor cells source electrode ends outside the limits of gate electrodes, common electrode of transistor structure drain on back side of substrate, field screening electrodes of transistor cells are made of gate electrode material and are installed at the interface of thermal silica dioxide - interlayer dielectric, at that width of thermal silica dioxide above low-alloyed drain region makes (1.0-3.5) of gate dielectric width, and border of gate dielectric coupling with layer of thermal silica dioxide above low-alloyed drain region is installed under gate electrode.

EFFECT: increase of permissible limit values of electric parameters and operation modes of SHF LDMOS - transistors and provision of conditions for organisation of profitable industrial production of these items.

1 dwg, 2 tbl

FIELD: electricity.

SUBSTANCE: in field MIS transistor drain and source regions each contain two serially connected sections, the main and the additional ones, at that the main sections of drain and source regions have high concentration of alloying admixture, and additional sections that are installed between channel and main sections have low concentration of alloying admixture. Abovementioned additional sections stretch into abovementioned semiconductor wafer deeper than the abovementioned main sections and enclose these main sections inside themselves, with their overlap in semiconductor wafer, and on the surface of semiconductor wafer border of this additional section on the one side is at least superposed with projection of one of gate sides on semiconductor wafer, and from the other sides it is distant from border of protective area at the value that is not less than sum of values of width of space charge areas formed in semiconductor wafer by drain, source regions and protective area, at that projection of end areas of gate ends onto surface of semiconductor wafer is superposed with border of protective area, and all surface of semiconductor wafer is coated with dielectric, the thickness of which does not exceed gate thickness.

EFFECT: increase of resistance to external actions, percentage of proper produce, fast-action.

5 dwg

FIELD: information technology.

SUBSTANCE: flash memory element for electrically programmable read-only memory is meant for data storage when power is off. On a semiconductor base with a source and drain between the latter, there is a tunnelling layer, an auxiliary tunnelling layer, a memory layer, blocking layer and a switch. The auxiliary tunnelling and blocking layers are made from material with high dielectric permeability, from 5 to 2000, exceeding the dielectric permeability of the material of the tunnelling layer made from SiO2.

EFFECT: as a result there is reduction of voltage (4 V) and time (10-7 s) for recording/erasing information and increase in data storage time (up to 12 years).

7 cl, 1 dwg

Field transistor // 2358355

FIELD: physics, radio.

SUBSTANCE: invention is to find application in microelectronics. Concept of the invention is as follows: the proposed field transistor is composed of a source electrode, a drain electrode, a gate insulator, a gate electrode and an effective layer; the effective layer contains an amorphous oxide with an electronic media concentration less than 1018/cm3 and the electronic mobility increasing proportional to the electronic media concentration. Of the source, drain and gate electrodes at least one is visual light translucent with the current flowing between the source and the drain electrodes never exceeding 10 mA unless there is a voltage applied to the gate electrode.

EFFECT: development of a transistor enabling improvement of at least one of the following properties: translucency, thin film transistor electrical properties, gate insulation film properties, leakage current prevention and adhesiveness between the effective layer and the substrate.

21 cl, 12 dwg

FIELD: physics.

SUBSTANCE: invention relates to an amorphous oxide, used in the active layer of a field-effect transistor. The amorphous oxide, which contains at least one microcrystal and has concentration of electron carriers from 1012/cm3 to 1018/cm3, contains at least one element, chosen from a group consisting of In, Zn and Sn, and the boundary surface of the grains of the said microcrystal is coated with an amorphous structure.

EFFECT: obtaining an amorphous oxide which functions as a semiconductor for use in the active layer of a thin-film transistor.

6 cl, 8 dwg

FIELD: electrical engineering.

SUBSTANCE: proposed invention relates to field transistor with oxide semiconductor material including In and Zn. Atomic composition ratio expressed as In/(In+Zn) makes at least 35 atomic percent and not over 55 atomic percent. With Ga introduced into material, aforesaid atomic composition ratio expressed as Ga/(In+Zn+Ga) makes 30 atomic percents or smaller.

EFFECT: improved S-characteristic and drift mobility.

9 cl, 25 dwg

Field transistor // 2390072

FIELD: electricity.

SUBSTANCE: in field transistor, comprising active layer and gate-insulating film, active layer comprises a layer of oxide, comprising In, Zn and Ga, amorphous area and crystalline area. At the same time crystalline area is separated from the first surface of interface, which is surface of interface between a layer of oxide and gate-insulating film, distance of 1/2 of active layer thickness or less, and it within the limits of 300 nm from surface of interface between active layer and gate-insulating film or is in point condition in contact with this surface of interface.

EFFECT: production of field transistor with high drift mobility.

4 cl, 4 dwg, 2 ex

FIELD: chemistry.

SUBSTANCE: amorphous oxide compound having a composition which, when said compound is in crystalline state, has formula In2-xM3xO3(Zn1-YM2YO)m, where M2 is Mg or Ca, M3 is B, Al, Ga or Y, 0 ≤ X ≤ 2, 0 ≤ Y ≤ 1, and m equals 0 or is a positive integer less than 6, or a mixture of such compounds, where the said amorphous oxide compound also contains one type of element or several elements selected from a group consisting of Li, Na, Mn, Ni, Pd, Cu, Cd, C, N, P, Ti, Zr, V, Ru, Ge, Sn and F, and the said amorphous oxide compound has concentration of electronic carriers between 1015/cm3 and 1018/cm3.

EFFECT: amorphous oxide which functions as a semiconductor for use in the active layer of a thin-film transistor.

6 cl, 8 dwg

FIELD: physics.

SUBSTANCE: in a field-effect transistor which includes an oxide film as a semiconductor layer, the oxide film has a channel part, a source part and a drain part, and concentration of one of hydrogen or deuterium in the source part and in the drain part exceeds that in the channel part.

EFFECT: invention enables to establish connection between the conducting channel of a transistor and each of sources and drain electrodes, thereby reducing change in parameters of the transistor.

9 cl, 13 dwg, 6 ex

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