Method and decoding device for correction of two errors in accepted code

FIELD: physics, communication.

SUBSTANCE: invention is related to the field of communication and may be used in devices for transmission of discrete information in communication line with interferences. Device contains memorising register, unit of error detection, unit of error correction, switching unit, which consists of two "AND" circuits, two registers of generator polynomial, two summators by module two, two decoders, programmable logical matrix, comparison unit, processor, inverter. Also method is disclosed for correction of two errors in cyclic code, which is realised by this device.

EFFECT: increase of communication channels equipment interference protection.

2 cl, 2 dwg, 1 tbl

 

The invention relates to the field of communication and can be used in devices of discrete information transmission in communication with the noise.

Known methods of determining the location of errors in the received code based on the calculation of the syndrome generating polynomial (see, for example, Peterson U., Weldon E. error-correcting Codes. M.: Mir, 1976. 594 S., Mack-Williams, F., Sloan NJ. theory of error-correcting codes. M: Communications, 1979. 744 S.).

When implementing the algorithm for decoding the syndrome make a table showing the syndromes siand the leaders of eithe corresponding cosets. The decoding algorithm is as follows:

1. Compute the syndrome s(u) of the received vector u.

2. The syndrome s(u)=sidetermine the leader of eithe respective adjacent class.

3. Determine the sent vector ν as the difference ν=u-ei.

With all the simplicity and transparency of the syndromic algorithm decoding has a serious disadvantage in that the device implementing this method of decoding must store information about the leaders and syndromes. The volume of this information is very large even for moderate lengths of code words (of the order of several tens). For binary (50, 40)code will be 1024 leaders and the same number of syndromes, and (50, 30)code the number of them is not what will happen a million.

A disadvantage of the known methods of decoding of cyclic codes is the excessive complication of the apparatus for syndrome decoding.

Closest to the proposed method is described in the book Schwartzman B.C., Emelyanov GA Theory of discrete information transmission. M: Communications, 1979, p.305-306 adopted for the prototype.

The prototype method is based on the property of separability of the cyclic code R(x)=f(x)=q(x)·g(x)=xn-km(x)+r(x) without remainder by the generating polynomial g(x). The remainder of dividing the received polynomial R(x) by the generating polynomial g(x) is called a syndrome. The presence of the remainder of dividing the received polynomial R(x) by the generating polynomial g(x) indicates the presence of errors introduced during transmission of the signal over the communication channel.

To correct the detected error code syndrome is constructed so that the polynomial of error was given when divided by g(x) different residues. Code syndrome determine the position of the erroneous bit in a received polynomial R(x)arising on the transfer in a binary communication channel.

The disadvantage of the prototype method is a correction not more than one symbol of the received cyclic code.

To eliminate this drawback in the way of correcting two errors in the decoding device cyclic code of degree n generated by the transmitter, based on calculating the remainder r(x)by dividing the received signal into a code polynomial of the cyclic code, represents the amount of information of the polynomial A(x), the control bit and the polynomial error, generating an irreducible polynomial g(x), the address calculation erroneous characters on the check matrix H(x) and then inverting the erroneous bits received signal, according to the invention together with the information polynomial A(x) and check bits of the code polynomial in the transmitter imposes an additional control bits b(x)obtained as the result of the division of information of the polynomial A(x) an irreducible polynomial g1(x)≠g(x), which when decoding a received cyclic code is used to build additional code polynomial F1(x), representing the sum of the control bit b(x), data bits A(x) and the polynomial error, the calculation of the additional polynomial r1(x) as the remainder of division of a polynomial F1(x) by a polynomial g1(x), the column definition i0and j0the corresponding check matrix H(x) and H1(x) with subsequent synchronous cyclic shift of the columns of the check matrix H(x) and H1(x) on s bits to match the numbers of columns of the check matrix H(x) and H1(x), then define in the code polynomial positions of the erroneous bits i and j from the expression: i≡i0-s(new games available at) and j≡j0+s(mod n), then invert.

redlagaemyi method of determining the location of errors in the received code is as follows.

The received code is stored in three registers, the first register storing information part code sequence; in the second and third register memorizing generating polynomials which divide the received code by the generating polynomial g(x) and g1(x), respectively. Received the remnants of the division are used to determine the number of columns in the check matrix H(x) and H1(x) by the substitution for them of the obtained residue and a comparison between them. Next is the inversion of the bits in the columns, where errors are found.

The proposed method of determining the location of errors in the received code is implemented in the following sequence.

Suppose you want to send over the communication channel affected by interference, the code word consisting of k information bits, which may be represented by a polynomial c0

For a cyclic code of length n=2m-1, we form the polynomial

A(x)=a(x)+c0(x)·xm=a(x)+C(x),

where

check the symbols resulting from the division of the polynomial C(x) an irreducible polynomial

which is generate for a given cyclic code.

The polynomial a(x) can also be pellucens by using the check matrix of size (n× m)

wherei∈0,1) - primitive element, the degree of which run over all Galois field GF(2m) modulo g(x).

Define additional control characters

as the remainder of division of a polynomial C(x) an irreducible polynomial g1(x)

Note that the polynomial b(x) can be obtained also by using the check matrix H1(x)

wherei∈0,1) - primitive element, the degree of which run over all Galois field GF(2m) modulo g1(x).

Next, you will generate a code polynomial of the form

According to the presence of noise in the communication channel, different from zero polynomial error

moreover, i≠j.

Then the received polynomial D1(x) will have the following form:

Finding and correcting two errors in the code polynomial D1(x) as follows.

The sequence of symbols representing a code polynomial D1(x) enters the first of the three mentioned registers implements the polynomial. In the second case sustained the t sequence of symbols F(x)=a(x)+C(x)+E(x), which contains information polynomial C(x), a polynomial of the error E(x) and a check polynomial a(x)generated by using the check matrix H(x). In the third register receives a sequence that implements the code polynomial F1(x)=b(x)+C(x)+E(x), which contains a check symbols b(x), obtained by using the check matrix H1(x).

In the second case will be the remainder of division of a polynomial F(x) irreducible polynomial g(x) in the form of a polynomial

where i and j are the number of distorted bits of code polynomial F(x).

In the third case will be the remainder of division of a polynomial F1(x) an irreducible polynomial g1(x) in the form of a polynomial

where i and j are the number of distorted bits of code polynomial F(x).

In the third case will be the remainder of division of a polynomial F1(x) an irreducible polynomial g1(x) in the form of a polynomial

where i and j are the number of distorted bits of code polynomial F1(x).

The following variants are possible distortion of the polynomial error: E(x)=0, E(x)=xiE(x)=xi+xj. Let us analyze these cases.

1. E(x)=0, then we can write

However, we must have r(x)=r1(x)=0.

2. E(x)=xi. Thus

a) 2m≤i≤(2+k-1). Then r(α)=αiand. Degree α and α1will be equal and point to the location of the erroneous bit;

b) m≤i≤(2m-1). Then get

Use the following expressions to determine the erroneous symbolwhen 0≤i≤(m-1):

3. E(x)=xi+xjwhen i≠j. Thus

a) m≤i≤(2m-1) and 2m≤j≤(2m+k-1), then from expressions (11) and (12) determine the location of the erroneous bit:

The location of one erroneous bit can be determined from the last expression. Using the matrix H(α) you can define a polynomial αj. To determine the location of the second erroneous bits can from the equation

b) 2m≤i≤2m+k-1 and 0≤j≤m-1. Similar to the previous reasoning, we get

in) 2m≤i≤2m+k-1 and 2m≤j≤2m+k-1. Then to determine the location of the erroneous bit will use the expressions (11) and (12). Multiply both parts of this formula for xsthat corresponds to a cyclic shift of a polynomial r(αand r11) 's positions. The result will be

When 0≤i+s≤m-1 runsaccording to the definition of the Oia check matrices H(α ) and H1(α). Consider the case (i+s)=0, then the system of equations (11)-(12) is converted to the form

where

From the system of equations (19), we can determine the position of one erroneous bit. The position of the second erroneous bits define the expression

g) 0≤i≤m-1 or m≤j≤2m-1. In this case, the information symbols there are no errors, so it is not possible to determine the position of the erroneous bit.

Thus, when decoding of the polynomial D1(x) it can be determined the location of any single erroneous bit and any two erroneous bits, provided that at least one of them is in the information bits.

The proposed method of determining the location of the two errors in the received code may be implemented in a decoding device.

Known decoding device, determining a bit error in the received code, see, for example, the book Mack-Williams, F., Sloan NJ. theory of error-correcting codes. M: Communications, 1979. S, RES.

This decoding device includes a delay unit, two shaper for the calculation of the syndrome, the outputs of which are connected to the input device, the output of the delay block is connected to the first input of block error correction, with its input connected to the output of decode the respective device, and the second input is connected with the output of the block definition locator polynomial error, and inputs connected to the inputs of the driver evaluator syndrome.

The disadvantage of this decoding device is its complexity, as well as to ensure the possibility of correcting two erroneous bits when encoding it is necessary to reduce the number of information bits in the code polynomial by increasing the number of check bits.

The closest in technical essence to the present invention is a decoding device described in the book Schwartzman B.C., Emelyanov GA Theory of discrete information transmission. M: Communications, 1979, s, RES.

The decoding device is a prototype, whose schema is shown in figure 1, includes a storage register 1, register a generating polynomial 2, the inputs of which are combined and input of the decoding device, the output of storage register connected to the first input of block error correction 3 whose output is the output device, the second input unit of error correction associated with the output block error detection 4, the inlet of which is connected to the output register of the generating polynomial 2.

The device prototype works as follows. The inputs of the storage register 1 and register a generating polynomial 2 receives the code sequence. After joining code is howling sequence, consisting of n bits, is its record in the storage case 1. At this time, concurrently with the division by the generating polynomial. As a result, in the case of a generating polynomial 2 is recorded syndrome. Syndrome, desifrirati in the block of error detection 4 indicates the location of the detected error in the code sequence. At the output of block error detection 4, which is connected to the unit error correction 3 is the number of erroneous bits. Further there is a shift code sequence recorded in the storage case 1, with the sum modulo two of the signal at the output of block error detection 4. As a result, the output of the prototype generated code sequence with an error corrected in a bit.

The disadvantage of the decoding device of the prototype is the inability to detect and correct more than one error bit of the received code, which leads to low noise immunity of the equipment of communication channels.

To address these shortcomings in the decoding device containing serially connected storage register and the block error correction, the output of which is the output of the device, and the first register of the generating polynomial and the block error detection, the output of which is connected with the second input block is error correction, the first input of the storage register is an input device according to the invention introduced a switch unit comprising first and second circuit And the first input of which is connected to the input device, the outputs are connected to first and second registers of the generating polynomial, the outputs are connected to first inputs of the first and second modulo two, the outputs of which are connected with inputs of the first and second decoders, respectively, programmable logic array (PLA), the first and second inputs connected to the outputs of the first and second decoder and the first and the second input of the comparison, the output of which is connected to the input processor, the first and second outputs of which are connected to control inputs of the first and second registers of the generating polynomial, a third output connected to the second input of the error detection, the fourth output of which is connected to the control input of the storage register, the fifth and sixth outputs of the processor is connected to the second inputs of the circuits And the seventh output of which is connected to the input of the inverter, the output of which is connected to the second inputs of adders modulo two, and managing input PLA, the output of the Comparer is connected to a second input of block errors.

The proposed scheme decoding device shown in figure 2, where is bonacina:

1 - storage case;

2, 8 is the first and the second register of the generating polynomial;

3 - block error correction;

4 - block error detection;

5 - switch unit;

6, 7, the first and second circuit "And";

9 - CPU;

10 - programmable logic matrix;

11, 12, the first and second decoder;

13, 14, the first and second modulo two;

15 - inverter;

16 - Comparer.

The proposed decoding device comprises serially connected memory register 1 and the block error correction 3 whose output is the output of the device, and the first register of the generating polynomial 2 and the block error detection 4, the output of which is connected to a second input of block error correction 3, the first input storage register 1 is the input device, the switch unit 5, which consists of the first 6 and second 7 circuit And the first input of which is connected to the input device, the outputs are connected to the first 2 and the second 8 registers of the generating polynomial, the outputs are connected to first inputs of the first 13 and second 14 modulo two, the outputs of which are connected with inputs of the first 11 and second 12 decoders, respectively, programmable logic array (PLA) 10, the first and second inputs connected to the outputs of the first 11 and second 12 decoder and the first and W is returned to the input unit of comparison, 16, the output of which is connected to the input of the processor 9, the first and second outputs of which are connected to control inputs of the first 2 and the second 8 registers of the generating polynomial, a third output connected to the second input of the error detection 3, the fourth output of which is connected to the control input of the storage register 1, fifth and sixth outputs of the processor are connected to second inputs of the circuits And 6 and 7, the seventh output of which is connected to the input of the inverter 15, the output of which is connected to the second inputs of adders modulo two 13 and 14, and managing input PLA 10, the output unit is connected to a second comparison entrance block error detection 16.

The storage case 1 is a binary shift register, which represents a series-connected multiple triggers, having at least two modes of operation: recording information and shift information. Managed shift information of the clock pulses applied to the input triggers.

Registers a generating polynomial 2 and 8 represent registers-dividers at the input sequence by the generating polynomial. As a result, the register is written, the remainder of the division, which then can be counted in parallel or serial code.

Block error correction 3 is a modulo two. It has two ravnos is cnyh login but can be considered one of the input information and the second control. If the control input is low potential (logical zero), the output signal equals the input. If the control input is high potential (logical unit), then the output signal will be inverted relative to the input. This is its ability to correct the information symbols.

It requires that the control device, which determines the moments of "fixes" bit of the received code. This function performs a block error detection 4, a logical unit the output of which determines the moments fixes the corresponding bit code sequence.

The switch unit 5 is a composite of two schemes "And" 6 and 7. When applying to one of the inputs of the circuit And a logical zero, the output will also be zero regardless of the level of the signal at the other input.

The CPU 9 performs the main functions of information processing and management of the computation process. The CPU 9 typical system commands, organization, firmware management, bus organization of the exchange, the number and designation of the internal registers, the interrupt processing, the number of batteries. The internal structure of the processor there are three main parts: the control unit, Ari is eticheskoe logic unit (ALU) with internal registers, circuit data transmission, or tires.

The device control processor provides synchronization and sequence commands, generates control signals that define the current function ALU, processes interrupt signals, generates information about the state of the processor and other

PLA 10 is programmed to perform functions similar to those of the check matrix H(x) and H1(x), i.e. it contains the column numbers and recorded them in vectors, ie,

the column number: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

The shift by one digit is cyclic transition to the adjacent column, i.e. after reaching the column on one edge of the subsequent matrix is at the beginning of the opposite edge.

In PLA 10 receives codes from the outputs of the decoders 11 and 12 and control signals (exit 7) from the CPU 9. The output signal of the PLA 10 is input to the CPU 9.

The decoders 11 and 12 are devices that transform a sequence of incoming pulses into separate signals.

The inverter 15 converts the logic zero at the input of a logic unit and Vice versa.

The Comparer 16 provides a comparison of numbers of columns PLA 10 or signals at the output of the decoders. In the case of non-issued a Signa is.

Consider the operation of the decoding device for correcting the erroneous bits in the received sequence of binary symbols.

First are pre-zeroing registers 1, 2 and 8.

When the signal at the input device in the CPU 9 starts program execution decoding.

If it be received code word with the higher categories, on the fifth and sixth output processor 9 is set to a high potential (logical unit). As a result, the outputs of circuits And 6 and 7 are signals coincident with the input device. To clock pulses on the first, second and fourth outputs of the processor 9 to record the information in the registers 1, 2 and 8. Moreover, their number in the storage register 1 will be equal to the sum of the degrees of the code polynomial and the degree of the generating polynomial, and in registers 2 and 8 only degree code polynomial. After the adoption of information pulses to the number of clock cycles equals the duration of one bit on the degree of the generating polynomial, closes the input schema And 7 (a logical zero on the fifth output processor 9) and cannot receive the clock pulses to the first output of the processor 9. Through the period of time that equals the duration of one bit on the degree of the generating polynomial, closes the input schema And 6 (logicheskie on the sixth output processor 9) and will cease to receive pulses at the input of the register 2. The result in registers 2 and 8 will be written remnants of the division code of the polynomial for generating, in the storage case 1 can be written the complete code sequence generated in the transmitter with distorted characters.

When the high potential at the seventh output processor 9 at the output of the inverter 15 will be low, which will be on the second inputs of adders modulo two 13 and 14, which will ensure the transfer of residues from the division code of the polynomial for generating the registers 2 and 8 in the decoders 13 and 14. When this transfer will be accompanied by the clock pulses on the first and second outputs of the processor 9. As a result, the output of the decoders 11 and 12 will be established codes, providing the initial selection of the columns of the matrix H(x) and H1(x) PLA 10, the clock pulses coming from the seventh output processor 9 will shift the columns of the matrix H(x) and H1(x) PLA 10. In block 16 comparison will compare the resulting numbers of columns, as shown in the table. In case of coincidence with the output of the PLA 10 is received by the input processor 9, where the results of their operations will be carried out to determine the positions (bits) of the received code, which was the distortion of the signal.

On the fourth output processor 9 will appear heartbeats, resulting in code that is written to remember the rd register 1, will be transmitted to the output through the block error correction 3. When will be undistorted bit, the output of block error detection 4 set low potential. When will be garbled bits, the output of block error detection 4 will be high potential. Fix erroneous bits in the received sequence of binary symbols in the block of error correction 3 (figure 2).

If in a received code polynomial D1(x) embarrassed distorted only one bit, then the appearance of the pulse at the second output of the processor 9 is block level logical units on the output of the inverter 15, the output of which is connected to the inputs of the adders modulo two 13 and 14 (figure 2). The output of the comparison circuit 16, connected to the first input of the block error detection 4, you will receive a high level. The output of block error detection 4 connected to the input of block error correction 3, will provide the inverting (fix) erroneous bits at the output of block error correction 3. As a result, the sequence of symbols at the output of block error correction 3 (device) will not be distorted bits.

An example implementation of a method for determining the location of the two errors in the received signal, with 19 bits (n=24-1=15), for which the irreducible polynomials are chosen according to the table shown in Soi is E. Peterson U., Weldon E. error-correcting Codes. M.: Mir, 1976. 594 S.:

g(x)=1+x+x4,

g1(x)=1+x3+x4.

In this case, the test matrices of size (15×4) will be

Suppose you want to transmit over the communication channel affected by interference, some code with0(x)=x+x4+x10. Then for the implementation of the proposed method of determining the location of the two errors in the received code, you must do the following steps:

1. The computed polynomial C(x)=C0(x)·x4that is equal to C(x)=x5+x8+x14,

2. Using the formula (2), the computed polynomial a(x)=(x+x2)+(1+x2)+(1+x3)=x+x3,

3. Using the formula (5), the computed polynomial b(x)=(1+x+x3)+(x+x2+x3)+(x2+x3)=1+x3,

4. Generated code polynomial D(x)=1+x3+(x+x3+x5+x8+xl4)·x4=1+x3+x5+x7+x9+x12+x18,

5. Set the type of the polynomial error E(x), which will contain two members of F(x)=x9+x15,

6. The polynomial D1(x), where due to the interference disappeared bits x9and appeared bits x15according to expression (10) takes the form

D1(x)=x+x3+x5+x7+xl2+x15+x18,

7. Form mn is goklany

F(x)=x+x3+x8+x11+x14,

F1(x)=1+x3+x8+x11+x14,

where there is no interference bits xj=x9-x4=x5and falsely present bit xi=x15-x4=x11.

8. The computed polynomial r(x), which is the remainder on division of F(x) g(x)

F(x)=Q(x)·g(x)+r(x),

where r(x)=x3,

9. The computed polynomial r1(x), which is the remainder on division of F1(x) on g1(x)

F1(x)=Q1(x)·g1(x)+r1(x),

where r1(x)=x+x3,

10. Define the polynomial r(α) substitution α in the polynomial r(x)

r(α)=α3,

11. The computed polynomial r11) substitution α1in the polynomial r1(x)

12. According to (18) of the table is determined by the value of s at which the system of equations takes the form (19)

The table shows that s=4, a j1=9,

13. Defined according to equation (20) the location of the first error

j=j1-s=5,

14. From the expression (21) determine the position of the second error

i=-s=11,

For the condition 3.a. possible polynomial E(x)

5.a. E(x)=x6+x15.

r(x)-1
Implementation of the algorithm of the calculation of erroneous bits
sr(α)r(x)r(α)-1r11)r1(x)r1(x)-1r11)-1
0α3X31+x3α14x+x21+x+x2
1α41+xx1x2+x31+x2+x3
2α5x+x21+x+x2α1010-
3α6x2+x31+x2+x3α13x1+x
4α71+x+x3x+x3α9x2 1+x2

6.a. The polynomial D1(x), where due to the interference appeared erroneous characters x6and x15according to expression (10) takes the form

D1(x)=1+x3+x5+x6+x7+x9+x12+x15+x18.

7.A. Define the polynomials

F(x)=x+x2+x3+x5+x8+x11+x14,

F1(x)=1+x3+x5+x8+x11+x14,

because of the interference present erroneous bits xj=x6-x4=x2and xi=x15-x4=x11.

A. The computed polynomial r(x), which is the remainder on division of F(x) g(x)

F(x)=Q(x)·g(x)+r(x),

where r(x)=x+x3,

9. well. The computed polynomial r1(x), which is the remainder on division of F1(x) on g1(x)

F1(x)=Q1(x)·g1(x)+r1(x),

where r1(x)=1+x2+x3,

10.A. Define the polynomial r(α) by the substitution in the polynomial r(x)

r(α)=α9,

11. The computed polynomial r11) substitution α1in the polynomial r1(x)

Where can we find j=11.

A. On the basis of the system of equations (15) defined

αj=r(α)·αj4112.

Where get i=2.

Thus, proposed is the range of the method allows to determine the location of the two errors in the received code and using the decoding device will correct two erroneous bits in a received code polynomial. This provides both increased correcting ability of the decoding device, and increase the noise immunity of the communication channel.

The technical effect of the use of the invention: improved correcting ability of the decoding device and increase the noise immunity of the communication channel. Together, this means improving the reliability of delivery of encoded messages (information).

1. Way of correcting two errors in the decoding device cyclic code of degree n generated by the transmitter, based on calculating the remainder r(x) by dividing the received signal into a code polynomial of the cyclic code representing the amount of information of the polynomial A(x), the control bit and the polynomial error, generating an irreducible polynomial g(x), the address calculation erroneous characters on the check matrix H(x) and then inverting the erroneous bits of the received signal, characterized in that together with the information polynomial A(x) and check bits of the code polynomial in the transmitter form additional control bits b(x)obtained as the result of the division of information of the polynomial A(x) an irreducible polynomial g1(x)≠g(x), which when decoding a received cyclic code is used to build additional code polynomial F1 (x), representing the sum of the control bit b(x), data bits A(x) and the polynomial error, the calculation of the additional polynomial r1(x) as the remainder of division of a polynomial F1(x) by a polynomial g1(x), the column definition i0and j0the corresponding check matrix H(x) and H1(x) with subsequent synchronous cyclic shift of the columns of the check matrix H(x) and H1(x) on s bits to match the numbers of columns of the check matrix H(x) and H1(x), then define in the code polynomial positions of the erroneous bits i and j from the expression i=i0-s(mod n) and j=j0+s(mod n), then invert.

2. The decoding device containing serially connected storage register and the block error correction, the output of which is the output of the device, and the first register of the generating polynomial and the block error detection, the output of which is connected to a second input of block error correction, the first input of the storage register is an input device, characterized in that the input switch unit comprising first and second circuit And the first input of which is connected to the input device, the outputs are connected to first and second registers of the generating polynomial, the outputs are connected to first inputs of the first and second modulo-two you the odes which are connected with inputs of the first and second decoders, respectively, programmable logic array (PLA), the first and second inputs connected to the outputs of the first and second decoder and the first and the second input of the comparison, the output of which is connected to the input of the processor, the first and second outputs of which are connected to control inputs of the first and second registers of the generating polynomial, a third output connected to the second input of block error detection, the fourth output is connected to a control input of storage register, fifth and sixth outputs of the processor are connected to second inputs of the circuits And the seventh output connected to the input of the inverter, the output of which is connected to the second inputs of adders modulo two and the control input of the PLA, the output of the Comparer is connected to a second input of block errors.



 

Same patents:

FIELD: communications engineering, possible use in data transmission systems, for remote measurement, remote control, in radio-transmitting equipment of small spacecrafts and for deep space telemetry.

SUBSTANCE: in accordance to the invention, at transmitting side code words are generated by encoding information symbols using cyclic code without usage of synchronizing patterns, parameters of cyclic code are changed depending on level of interference, transferred information is accumulated at receiving side, thus creating a selection, then for phasing by code words limits of code word are determined, supposed length of code word is set, and in set window "sliding" symbol-wise discrete Fourier transformation is performed in Galois field for whole volume of selection being analyzed, while at each step of "sliding" discrete Fourier transformation in Galois field, selection of zero spectral components is performed as well as determining of quantity thereof together with building a function of number of zero spectral components at each step of "sliding" discrete Fourier transformation in Galois field, then decimation of given function is performed with step, equal to supposed length of code word, with building of a function estimate of mathematical expectation of number of zero spectral components, phasing moments reach maximum of mathematical expectation estimation function of number of zero spectral components, with consideration of resulting maximum, code words are selected, and then estimate of mathematical expectation of code word spectrums is performed and parameters of cyclic code are evaluated on basis of resulting code words, and then cyclotomic classes are determined, the generative polynomial of cyclic code is restored and code words are decoded.

EFFECT: increased interference resistance of cyclic code receipt, automatic adaptation of characteristics of transferred signal to interference intensity, increased speed of information transfer and accelerated phasing process during transfer of code words without synchronizing patterns.

4 dwg

FIELD: communications engineering, in particular, engineering of data transfer systems for decoding cyclic interference-resistant codes without preliminary phasing.

SUBSTANCE: during decoding of cyclic interference-resistant code, range of presumed lengths of code combinations [nmin-nmax] is determined, and assumed phase of beginning of code combination f is set, from phase f in received code series several presumed code combinations Si are selected and pairs are formed from selected combinations in accordance to condition Si≠Sk, N of greatest common divisors, represented by polynomials, is calculated, and from calculated polynomials a polynomial of least order is selected, which is considered equal to original polynomial g(x) of cyclic interference-resistant code, if N of greatest common divisors is equal to "1", then length of proposed code combination n is increased by one, phase of proposed beginning of code combination is altered for one, if greatest common divisor, different from "1", is not found for all n∈[nmin-nmax], combinations of errors are determined in code word and selected code combinations are decoded.

EFFECT: development of method for decoding cyclic interference-resistant code under conditions of adaptation of interference-resistant code to quality of information transfer channel.

3 cl

FIELD: communications engineering; data transfer, telemetering, and telecontrol systems.

SUBSTANCE: proposed codec has on sending end code-word data part shaper whose output and that of code-word synchronizing part shaper are connected to modulo two adder input; on receiving end it has binary filter whose code-word data part shaper output is connected to accumulator connected to synchronizing sequence decoder and to error connection unit whose outputs are connected to respective inverting inputs of code-word data part shaper; output of the latter functions as data output of device; output of binary-filter code-word synchronizing part is connected through switching unit to input of code-word data part shaping unit; synchronizing sequence decoder output is connected to control input of switching unit and to error correction unit input; on receiving end accumulator outputs are connected to inputs of code-word data part shift decoder whose output is connected to input of delay circuit whose output functions as second control input of switching unit and as synchronizing output of device.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

The invention relates to the field of communication technology and can be used in data transmission systems, systems, telemetering and telecontrol

The invention relates to a coder/decoder in a communication system, and more particularly to a device for encoding/decoding of linear block codes by analyzing serial concatenated codes

FIELD: mobile communications, in particular, device and method for encoding-decoding low density block codes with parity check.

SUBSTANCE: the method includes stages, at which dimensions of parity check matrix are determined on basis of speed of encoding during encoding of information with low density block code with parity check and length of code word; parity check matrix of certain dimensions is divided onto a predetermined number of blocks; blocks are classified as blocks, corresponding to informational part; permutation matrices are positioned in predetermined blocks among blocks classified as first checking part, and identity matrices are positioned in full lower triangular form in predetermined blocks among blocks, classified as second checking part; and permutation matrices are positioned in blocks classified as informational part, resulting in minimal cycle duration being maximized and weight values being irregular on the coefficients graph of low density block code with parity check.

EFFECT: increased reliability of data transmission and improved correcting ability of low density code with parity check.

FIELD: computer engineering, possible use in devices for transformation of numbers from polynomial system of residual classes to positional code.

SUBSTANCE: device contains shift register, synchronization block, constant memory block, group of AND elements, positional accumulating adder, error detection block, data storage block, modulus two correcting adder. Error detection block is made in form of three-layered neuron network.

EFFECT: increased speed of transformation, expanded functional capabilities of device due to ensured error correction.

2 cl, 2 dwg, 5 tbl

FIELD: computer engineering, possible use in modular neuro-computer systems.

SUBSTANCE: in accordance to invention, neuron network contains input layer, neuron nets of finite ring for determining errors syndrome, memory block for storing constants, neuron nets for computing correct result and OR element for determining whether an error is present.

EFFECT: increased error correction speed, decreased amount of equipment, expanded functional capabilities.

1 dwg, 3 tbl

FIELD: computer engineering, in particular, modular neuro-computer means, possible use for finding and correcting errors in modular codes of polynomial residual class system.

SUBSTANCE: in accordance to invention, polynomial residual class system is used, in which as system base minimal polynomials pi(z), i=1,2,...,7, are used, determined in extended Galois fields GF(25) and neuron network technologies, and also modified zeroing constants determined in current polynomial residual class system are used in parallel.

EFFECT: increased speed of detection and correction of errors in modular codes of polynomial residual class system.

2 dwg, 7 tbl

FIELD: computer engineering, possible use in combination devices, and also devices for storing and transferring information.

SUBSTANCE: device contains original circuit, four groups of AND elements, group of OR elements, encoding device, folding circuit, register, error syndrome circuit, checks circuit, three decoders, corrector.

EFFECT: decreased number of controlling discharges.

1 dwg, 1 app

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, inversion block, decoder, even parity check circuit, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, inversion block, decoder, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, even parity check circuit, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

FIELD: computer science.

SUBSTANCE: network has end ring neuron network, Hopfield neuron network, demultiplexer and multiplexer.

EFFECT: broader functional capabilities, higher efficiency, higher speed of operation.

1 dwg

FIELD: automatics and computer science, possible use for controlling and correcting errors during relaying of information, and also for performing arithmetical operations by computer.

SUBSTANCE: device has two blocks for calculating error syndrome on basis of control bases, made on two-layer neuron network, register, memory block, output adder, and also due to application of polynomial residuals system, in which as system base, minimal polynomials are used, determined in extended Galois fields GF(2ν) and in terms of neuron network technologies.

EFFECT: decreased dimensions of equipment, higher speed of detection and correction of errors.

3 dwg, 2 tbl

FIELD: engineering of printers and memory devices for printers.

SUBSTANCE: in accordance to suggested method for detecting error in data, received from memory device of replaceable printer component, ensured is first evenness control bit, associated with first data element. First data element and first evenness control bit are stored in memorizing device. Printer includes a set of electro-conductive lines. Memorizing device includes a set of bits. At least one of electro-conductive lines is associated with each bit. First data element and first evenness control bit are read from memorizing device. Electric test of at least one of electro-conductive lines is performed. Error is identified in first data element on basis of first evenness control bit, read from memorizing device, and electric test. Other inventions of group envelop printing system, two variants of realization of replaceable printer component for printing system and method for storing information in replaceable printer component are provided.

EFFECT: creation of memory device with increased reliability, timely detection and correction of errors in replaceable components of printers ensures their continuous operation.

5 cl, 7 dwg

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains original circuit, three groups of AND elements, AND element, group of OR elements, OR element, encoding device, register, error syndrome circuit, checks circuit, three decoders.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains original circuit, four groups of AND elements, group of OR elements, encoding device, register, error syndrome circuit, checks circuit, three decoders, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

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