Method and device for implicit preliminary charging of dynamic operative memory (dram)

FIELD: physics; computer technology.

SUBSTANCE: invention refers to the method and device for the implicit preliminary charging of dynamic operative memory. The memory device contains at least one bank consisting of memory cells, organised into a set of lines of memory cells; and the logic control facility connected with at least one bank, and reacting to reception by the memory device to a command of activation of a single line for opening a particular line in such a manner that if there are no open lines when the command has been given, then at least in one bank it opens, and if in the bank another line is open, then the other line closes and the particular line opens. The device of management of memory contains the first site of storage in which is stored data relative to the lines in bank of memory cells in the memory device and a logical control tools transformed, committed to the memory cells. The methods describe the work of the specified devices.

EFFECT: expanding the functional capabilities of the device for preliminary charging of dynamic operating memory.

22 cl, 6 dwg

 

PRIOR art

Device dynamic random access memory (DRAM) give the advantages of higher density storage and less power consumption compared to other memory technologies, including, and most notably, devices, static RAM (SRAM). However, these advantages are achieved by introducing a variety of necessary delays before and/or after each use to read, write and other functions to enable the memory and other components in the device dynamic random access memory (DRAM) to prepare for subsequent treatment. Examples of such delays: pre-charging lines, operations regeneration, activation of rows, etc. Attempts to effectively manage these countless delays led to the creation of teams to allow more precise control of time, in which occur these various delays, but this creates additional system costs of additional commands that need to pass between calls to read and write.

Well established practice to try to reduce costs as well as the physical size of the device dynamic RAM, multiplexer many functions on the input and output of various signals. However, this multiplexing requires a lot f the C for sending commands and/or addresses, actually replacing the physical separation of signals by time division, in which more time is required to enable inputs and outputs various signals to first serve a single function and then maintain at least a second function, if not more. One example of multiplexing, which makes such expenditure of time, is the result of the division addresses passed to the device dynamic RAM (DRAM), at least two parts (usually at least address rows and columns), which are then multiplexed in the same input signals so that the first part of the address must be sent within one particular period of time, and it is followed by at least the second part addresses sent within at least one separate period of time. This division of time into distinct phases increases system costs countless necessary commands.

As devices are dynamic random access memory (DRAM) gradually became faster as a result of improvements in the construction as cells of a dynamic random access memory (DRAM), comprising the device dynamic RAM (DRAM), and transistors, etc. used for the formation of cells of a dynamic random access memory (DRAM) speed, where are the interfaces composed of multiplexed signals input and output devices, dynamic random access memory (DRAM), needed to increase. In the effort to achieve a higher interface speeds, maintaining the integrity of the transfer commands, addresses and data, established practice to synchronize the various phases and functions are multiplexed with inputs and outputs, clock signal to ensure that the status of the various inputs and outputs are transmitted and can be locked at the appropriate times. Initially, usually used whole clock cycles as the basis of timing for events on the memory bus. However, even faster devices are dynamic random access memory (DRAM) has led to the more recent adoption of half clock cycles for the basis of timing for events on the memory bus, which led to the so-called "dual clock" signal, or which in most cases is mentioned in connection with the conventional devices, synchronous dynamic RAM (SDRAM) as devices with "double data rate" (DDR). Although increased speed interfaces, it would seem, provide the opportunity to fully accommodate the system costs many commands, such higher is koroth interface has encountered difficulties in complying with the requirements of the fine tune signal and the synchronization delay of each of the different phases, required when transferring each of the countless commands and/or addresses. These difficulties were such that it was suggested that the commands and/or addresses were passed with the speed only up to half the clock frequency at which data is transmitted, what has been described as "2n synchronization", thus abandoning the advantages of dual sync to transfer commands and/or addresses.

The total time delay, which is the result of these various difficulties in the transfer of commands and/or addresses, started to become significant in extent, competing with the loss of time in preparing cells for dynamic random access memory (DRAM) to access them. Indeed, there is growing concern that the system overhead required to transfer addresses and/or commands may take longer available bus bandwidth memory than required for the actual data.

BRIEF DESCRIPTION of DRAWINGS

The objectives, features and advantages of this invention will be obvious to experts in the field of technology, taking into account the following detailed description in which:

Figure 1 - block diagram of a variant embodiment using the system memory;

Figa and 2b are diagrams of timing and action schemes relevant events for variants of the embodiment uses the memory bus;

<> Figure 3 - diagram of timing variant embodiment that uses the memory bus;

4 is a block diagram of a variant embodiment that uses a computer system;

5 is a sequence diagram of operations of a variant embodiment;

DETAILED DESCRIPTION

In the following description for purposes of explanation formulated numerous details, in order to ensure full understanding of the present invention. However, the specialist in the art it will be obvious that these specific details are not required in order to apply the invention in practice.

Variants of the embodiment of the present invention relate to integrated support implicit data transfer operations pre-charging on the open line in the Bank of memory cells in the memory device in a way that reduces the number of required commands and, therefore, reduces the bandwidth required for transmission of commands to do such operations pre-charging. Although the subsequent discussion focuses on devices, dynamic random access memory (DRAM), in which memory cells are organized into one or more two-dimensional arrays of rows and columns, specialists in the art will understand that the invention as it is claimed in the future, can be implemented to support the LCD any type of memory device, in which memory cells arranged in any of a variety of ways, including banks interleaved addresses, arrays of more than two dimensions (i.e., addresses with more than two parts), associative memory, etc. in Addition, although at least part of the subsequent discussion focuses on the storage devices in computer systems, specialists in the art will understand that the invention as it is claimed in the future, may be implemented in connection with other electronic devices having a memory device.

Figure 1 is a simplified block diagram of a variant embodiment that uses system memory. The memory system 100, at least partially consists of a controller 170 memory and device memory 190 are connected via a bus 180 memory. Specialists in the design of memory systems are easy to recognize that Fig. 1 depicts one form of a relatively simple system memory, and that a possible alternative embodiment, in which the exact location and configuration of components can be reduced, increased or modified in other ways without departure from the essence and scope of this invention as it is claimed in the future. For example, although the memory system 100 is depicted as having only one bus 180 memory and only one device 190 memory for the sake of simplicity will follow the discussion, specialists in the art will readily understand that other possible embodiments of the system 100 memory can consist of a number of memory buses and/or devices.

Controller memory 170 controls the functions performed by device 190 memory that is part of the access device 190 memory to external devices (not shown)connected to the controller memory 170. Namely, the external device connected to the controller 170 of memory issues commands to the controller 170 to the memory to retain data in the device memory 190 and retrieve the stored data from the device memory 190. The controller 170 memory accepts these commands and sends them to the device memory 190 in the format, with the timing and protocols that are compatible with the bus 180 memory and/or a combination of tools 191 logic control and buffer 197 data, which constitute the interface between the device 190 and memory bus 180 memory. In essence, the controller 170 memory coordinates treatment performed to the memory cells in the device 190 to the memory in response to commands read and write from external devices. In support of these functions in different embodiments, the controller 170 memory also coordinates various maintenance operations that must be performed to ensure that the saved data stored in the device memory 190, the second number of initiation of regular operations regeneration & events operations pre-charging, what is needed between requests.

Bus 180 memory composed of various signal lines of control, addressing and data, connecting together the controller 170 to the memory and the device memory 190. The exact number and characteristics of the various signal lines of various possible embodiments of the bus memory 180 can be configured to have the opportunity to interact with any of the many possible memory interfaces, including those that are implicit compatible with known types of memory devices, including devices, dynamic random access memory (DRAM), memory devices, fast page mode (FPM), dynamic RAM with extended time availability of data output (EDO), a dual-port video memory (VRAM)RAM WRAM (window RAM), memory with single data rate (SDR), memory with double data rate (DDR)dynamic random access memory RAMBUS™ etc. In some embodiments of the incarnation, where it is implied that the activity on the various signal lines is coordinated by the synchronization signal, one or more signal lines, the signal line control, serves to transmit the synchronization signal between the controller 170 memory and device memory 190. In some embodiments, embodiments one or more signals to control the means and the addressing signals can be multiplexed in a common signal lines so the control signals and addressing signals are transmitted at different times by common conductors for carrying signals between the controller 170 memory and device memory 190. In addition, in some embodiments, embodiments one or more signals addressing and data signals can be multiplexed in a common signal lines.

The device 190 memory device is a dynamic RAM with a tool pair, composed of logical tools 191 control and buffer 197 data configured to be able to communicate with the memory bus 180. In some embodiments the embodiment of the device memory 190 is a single integrated circuit. In other embodiments, the embodiment of the device 190 memory is composed of several integrated circuits removable memory module, such as a memory module with in-line pin (SIMM), the case with in-line pin (SIPP), RAM, ROM, and conclusions (DIMM), etc.

The memory device 190 memory are grouped into a number of banks, such as banks 199a-199d, each Bank arranged in a two-dimensional array of memory cells having rows and columns. In some embodiments the embodiment of the logical tool 191 management takes at least some of the commands and addresses from the controller 170 to the memory via the bus 180 memory and done the em these commands, using decoders 193a-193d line address decoder 194 address column and/or logical means 192 choosing a Bank to refer to one or more specific parts of one or more banks 199a-199d. Essentially, in order to access a memory cell in the device 190 to the memory, the address of this memory cell is composed of three parts, which are transmitted to the controller 170 of the memory device 190 to the memory bus 180 memory, namely the Bank, row and column in the memory cell. In response, at least at commands read and write, received from the controller 170 to the memory, the multiplexer 195 choice of I/o and buffer 197 data are used to store data in or retrieve data from one or more memory cells.

In some embodiments embodiment, the controller 170 memory supports buffers 179a-179d condition of the Bank, the relevant banks 199a-199d device 190 memory, which contains information regarding whether opened or not the line of the Bank, and the address of this string. The controller 170 memory relies on the contents of the buffers 179a-179d condition of the Bank to determine whether there is a need to transfer activation command-line to prepare the given string in the given Bank to access it, and is already open by another row in the same Bank, so that may require additional time for closed is I this another line by the operation of pre-charging, before this line opens in response to the activation command.

More specifically, in some embodiments, embodiment, if the controller 170 memory will refer to this line in the given Bank, the controller 170 memory checks the contents of each of the buffers 179a-179d state Bank corresponding to the Bank, to determine open whether this string, and if this line is not open, then to determine open or not open another line. As an example, if the controller 170 memory should refer to the row in the Bank 199a, the controller 170 checks the contents of the memory buffer 179a state Bank to determine open whether the given string. If this line is already open, the transfer command activation string for opening this line is not needed. However, if the string is not already open, the controller 170 checks the contents of the memory buffer 179a state Bank to determine open or not open another line at the Bank 199a. If none of the row in the Bank 199a is not open (which is sometimes called the "blank page"), the controller 170 memory must send the activation command-line device 190 memory to open this line at the Bank 199a during the preparation for the appeal, and the controller 170 memory should provide sufficient time between the transmission of the activation commands and performing Obraniak this line, to happen the preparation of this line to circulation. Alternatively, if this line is not open, but opened another line (which is sometimes referred to as "page missing"), the controller 170 memory must send the activation command prompt (with the implied command pre-charging) device memory 190 to close another line to open the line at the Bank 199a during the preparation for the appeal, and the controller 170 memory should provide sufficient time between the transmission of the activation commands and performing a treatment to the line, to cause a closing of the other string through the operation of pre-charging and preparation of the given string to convert.

Fig. 2a and 2b are diagrams and synchronization schemes appropriate action variants of the embodiment uses the transmission of signals on the memory bus. Both figa-b depict the transfer of activation commands to activate a row of memory cells in the Bank 299 memory, namely, the Bank 299, followed by the transfer command is a read or write to access a memory cell in an open line to extract or save some data. Both Figo and 2b depict the use of signals and timing compatible with the known synchronous interfaces dynamic random access memory (DRAM), to support the illustrative device the VA memory having multiple memory banks from which Bank 299 is only one. Although these figures and accompanying discussion will focus on variants of the embodiment of memory buses, which are transactions that are synchronized according to the synchronization signal, specialists in the art will readily understand that other variations of the embodiments may use other forms of timing, or may be asynchronous.

In Fig. 2a a row of memory cells is not open in the Bank 299 at the moment 286 time when transmitted the activation command line to open the line to which a call is made, the Bank 299. Simultaneously with the transmission of the activation commands may also be the transfer address of the Bank and/or row to which to apply the activation command, with the Bank 299 in this case. Minimum predetermined number of clock cycles occurs during the interval 287 time to provide sufficient time to process the opening line to which a call is made, has ended. As recognized experts in the art, other commands, addresses and/or data can be transmitted during interval 287 time, and sending these commands, addresses and/or data may affect other banks and/or memory devices. Also specialists in the field of technology is obvious that online is tearing 287 time may be longer, than just the time required to open a line to which a call is made to coordinate other aspects of memory management, unconnected with the opening line to which a call is made. At the moment 288 time initiated the actual circulation to the line to which a call is made, the transfer command is a read or write. Simultaneously with this transfer command is a read or write may also be passing the address of the Bank and/or column to which to apply the command to read or write.

On fig.2b another row of memory cells other than the line to which a call is made, is already open in the Bank 299 at the moment 286 time when transmitted the activation command line to open the line to which you are contacting the Bank 299. As shown in Fig. 2a, simultaneously with the transmission of the activation commands can also be the transfer address of the Bank and/or row to which to apply the activation command, the Bank is again the Bank 299. Again the minimum predetermined number of clock cycles occurs during the interval 287 of time during which it can be transferred to various unrelated commands, addresses and/or data. However, unlike what is shown in Fig. 2a, it is assumed that the predetermined number of clock cycles provides sufficient time to complete as implied by the sa pre-charging (i.e. closing another line, which was already open at the moment 286 time, and process the specified activation line to open the line to which a call is made. Therefore, the minimum number of clock cycles required to complete both processes during the interval 287 time in Fig. 2b, more than for the time interval 287 Fig. 2a. At the moment 288 time initiated the actual circulation to the line to which a call is made, the transfer command is a read or write, and along with this it is possible to simultaneously transmit the address of the Bank and/or column to which to apply the command to read or write.

As for the length of the interval 287 time on both Fig. 2a and 2b, the device transmitting the activation command line at the moment 286 time and/or command read/write at the moment 288 time, in some embodiments, embodiments may use some kind of buffer, the set of registers and/or other storage device in order to maintain current information about open or not open the line at the Bank 299, and if opened, the address of this string. Such information can be used to determine whether the activation command strings are interpreted as containing an implicit command pre-charging. When making such a determination, such information can be used to determine the minimum length of the interval 287 time necessary to ensure that the operations of activation lines that occur without a pre-charging operation and activation operations of the line, followed by the implicit pre-charging operations, provided enough time to complete. In some embodiments embodiment the length of the interval 287 time can be measured and/or distributed by the number of clock transitions or full clock cycles, as described in relation to both Figo and 2b. Alternatively, in other embodiments, embodiments, which can include the use of asynchronous approvals in time, the length of the interval 287 time can be measured and/or distributed in other ways. In addition, although a special mention of the transfer address of the Bank, row and column simultaneously with the transmission of specific commands in variants of the embodiment depicted in figa and 2b, the technical people easily recognize that any combination of signals, addresses and/or commands can be transmitted simultaneously with the transmission of the command activation line and/or read/write, or to ensure interoperability with existing specifications double data rate (DDR), or for other reasons, without departing from the essence and scope of this invention as it is claimed in the future.

Figure 3 shows the I-diagram of timing variations of the embodiment, using the transmission signals on the memory bus to multiple memory devices, depicting the transmission of the command activation line and read/write to two memory devices. One memory device selected by casting line-CS0 selection of the memory element in a state with a low level, as part of obtaining from the memory device or the transmission device memory addresses, commands and/or data, and other storage device selected by a similar cast line-CS1 selection of the memory element in a state with a low level. Both the memory device is depicted receiving the command, the appropriate opening line to which a call is made by the activation command prompt, after preliminary closing the other line, which was already open. Again, although this figure and the accompanying discussion will focus on variants of the embodiment of memory buses, which are transactions that are synchronized according to the synchronization signal, specialists in the field of technology will readily understand that other variations of the embodiments may use other forms of synchronization, or may be asynchronous.

The memory device selected through the line-CS0, is managed in a way compatible with the current Protocol to the double data rate (DDR), in which the string to which a call is made, can be opened for access is only after as another row in the same Bank was first explicitly closed via an explicit command pre-charging line. At the moment 381 time transmission such explicit command pre-charging occurs, possibly with simultaneous passing the address of the memory Bank to which is applied an explicit command pre-charging. Between 381 and 383 time given period of time, to allow explicit the pre-charging operation to be completed before it is passed to the activation command line to open the line to which a call is made, at the moment 383 time. In variants of the embodiment, implying compliance with the timing and/or protocols of the current implementations of double data rate (DDR), address of the Bank and/or row to which to apply the activation command-line, can also be transmitted simultaneously with the transmission of the activation commands line. Between 383 and 385 of time is given another period of time, to enable activation operation of the line to be completed before it is passed to the command to read/write at the moment 385 time, it is possible to simultaneously send the address of the Bank and/or column.

In contrast, other storage device, selected through the line-CS1, is controlled to perform the same operations, ka which has just been described with regard to the memory device, selected through the line-CS0, but without explicit commands pre-charging. Namely, at the moment 387 time passed the activation command prompt with implicit command pre-charging, possibly with corresponding delivery address of the Bank to which you apply the commands to activate and pre-charge, and/or possibly with a corresponding transmission line address to which the command applies activation. Between 387 and 389 of time given period of time, to give both the implicit operations pre-charging and explicit activation operation to be completed before it is passed to the command to read/write at the moment 389 time, it is possible to simultaneously send the address of the Bank and/or column.

Although the transfer of commands to each of the memory devices, selected through line-CS0 and-CS1, discussed separately, different variants of the embodiment of the memory controller (or other device used as a memory controller)that can transmit commands to the memory device, may include support for switching between using either explicitly transmitted commands pre-charging or implicit command pre-charging accompanying the transmitted activation command. Such a memory controller may allow obyedinenie memory devices, supports implicit command pre-charging, with other memory devices that do not support it. In order to promote interoperability with more limited current options double data rate (DDR), in which there is no support for implicit commands pre-charging, some variants of the embodiment of the memory controller may include one or more bits in one or more control registers to enable selective transfer of explicit commands pre-charging to support the more limited current versions of memory the double data rate (DDR). In addition, variants of memory devices that support the use of implicit commands pre-charging, can include one or more bits in one or more control registers or other storage device, to provide an indication of the availability of resources beyond the current options double data rate (DDR) using the implicit support team pre-charging to allow to identify the presence of such a possibility.

Figure 4 is a simplified block diagram of a variant embodiment that uses a computer system. Computer system 400, at least partially consists of a Central p is ocessor (CPU) 410, system logic 420 and device 490 memory. System logic 420 is connected with the Central processor 410 and performs various functions to support the Central processor 410, including the Central processor 410 access device 490 memory, with which the system logic 420 is also connected using controller 470 memory system logic 420. The CPU 410, the system logic 420 and device 490 memory are the type of kernel to the computer system 400 that is capable of supporting the execution of machine-readable commands by the CPU 410 and the storage of data and commands in the device 490 memory.

In different embodiments, the Central processor 410 may be any of a variety of types of CPUs, including the Central processor, capable of performing at least part of the widely known and used system commands "x86", and in other different embodiments may be more than one Central processor. In a different embodiment of the device 490 memory may be any of many types of dynamic random access memory, including a memory device fast page mode (FPM), dynamic RAM with extended time availability of data output (EDO)memory with single data rate (SDR)synchronous dynamic operator the main memory (SDRAM) with a single data rate (SDR) or double data rate (DDR), RAM of different technologies that use RAMBUS interface ™ and so on, and the controller 470 memory provides logic 420 corresponding interface for the memory type. At least part of the memory device 490 memory is divided into banks 499a-d, each of which is composed of memory cells arranged in rows and columns in a two-dimensional memory array. To access part of the memory cells in the device 490 memory, this part should apply using the controller 470 memory through a combination of addresses of the Bank, row and column. As skilled professionals in the art will understand that the description only memory device 490 with four banks of memory cells, namely banks 499a-499d is just an example of the memory system, which may be part of a computer system, and that can be used more memory devices and/or any other number of banks in the memory device without departure from the essence and scope of this invention as it is claimed in the future.

In some embodiments, embodiments of the system logic 420 is connected with the Central processor 410 and gives him access to a storage device 460 through which you can access data and/or commands, which are carried by the carrier 461 data. Media 461 data can be any of the wide variety of types and technologies, it is understood by experts in this field of technology, including CD-ROM, read-only (CD-ROM)or a digital disk, read-only (DVD-ROM), magnetic or optical disk, magnetooptical disk, tape, semiconductor memory, symbols or perforations on the paper or other material, etc. In some embodiments the embodiment of non-volatile device memory 430 is connected to the system logic 420 (or other part of a computer system 400) and provides storage for the initial sequence of commands at a time when computer system 400 or "reloaded", or initialized (for example, when computer system 400 is activated to perform the tasks necessary to prepare the computer system 400 to normal use. In some varieties such variants embodiment, after initialization or pre-loading of the computer system 400, the Central processor 410 accesses the non-volatile device memory 430 to retrieve commands that must be performed to prepare the memory controller 470 to the normal use to ensure the Central processor 410 accesses the device 490 memory. It is possible that these same extracted commands are executed to prepare systems the Yu logic 420 to the normal use to provide access to a storage device 460 and to any type of media 461 data which can be used storage device 460.

In some embodiments, embodiments of the media 461 data store available to the machine commands that must be executed by the CPU 410 to instruct the Central processor 410 to perform one or more checks device 490 memory to determine what type of device dynamic RAM may be the device 490 memory and/or to determine what features can support the device 490 memory. If it is determined that the device 490 memory can support the use of an implicit command pre-charging, embedded in the transmitted activation command line, as described above, the CPU 410 may be prescribed to program or otherwise configure the controller 470 memory to use such implicit commands pre-charging. In variants of the embodiment in which the controller 470 memory so programmed, the controller 470 memory can access a storage device or to contain a storage device, such as a buffer 479 access line to support the data regarding the status of the various rows in the device 490 memory. Such data, either stored in a separate buffer, such as buffer 479 access line, or not saved, can about what especial indication, which of the banks 499a-d has open lines, and addresses these open strings. The controller 470 memory can access this data to determine open if the string to which a call is made, this one of the banks 499a-d, and if not, is open is another row in the same Bank. If you find that the line to which a call is made, is already open, then the access can be performed without issuing an activation line. However, if you find that the line to which a call is made, is not open, the transfer command activation line and passing the predetermined minimum period of time should precede any treatment that needs to be done to the line to which a call is made. If it is determined that in the same Bank there is another line that is already open, then the activation command line will be interpreted by the device 490 memory as being implicitly team pre-charging to close another line, and a predefined minimum period of time will be longer, so as to provide as close a different row, and the opening line to which a call is made.

Figure 5 is a diagram of sequence variants of the embodiment. At step 510, it is determined as to whether open Liuge string to which a call is made. If the string to which a call is made, is already open, then at step 512 to a row address for read, write, etc. However, if the string to which a call is made, is not open, then at step 520 a determination is made as to whether open whether another string. If the other line is not open, then at step 522 is transmitted to the activation command line to open the line to which a call is made, at step 524 the opportunity to take the time necessary to complete the activation line to which a call is made, and at step 512 is being accessed. However, if the other line is already open, then at step 530 determination is made regarding whether the memory device having a Bank where as the other string, and the string to which a call is made, the use of implicit commands pre-charging. If the memory device supports implicit command pre-charging, then at step 542 the activation command-line with the implied command of the preliminary charge is transferred to the memory device, at step 544 the opportunity to take the time necessary to complete pre-charging (closing) the other line, along with passing on the stage 524 sub is ka time for activation string to which a call is made, and at step 512 is being accessed. However, if the memory device does not support implicit command pre-charging, then at step 532 is transmitted explicit command pre-charging to close another line, at step 534 the opportunity to take the time necessary to complete the closing of the other row, at step 522 is transmitted activation commands to open the line to which a call is made, along with passing on the stage 524 of time sufficient to give the possibility to be activated, and at step 512 is being accessed.

The invention has been described in some detail on the various possible options for implementation. It is evident that numerous alternatives, modifications, variations and use will be apparent to experts in the art in light of the preceding description. Specialists in the art will understand that the invention can be implemented in support of the many possible types of memory devices that use any of the many possible memory technologies. Specialists in the art will also understand that the invention can be carried out in support of electronic devices other than computer systems, such as AUD is about/video device for entertainment, control devices in vehicles, appliances, managed electronic circuits, etc.

1. The memory device, which contains:

at least one Bank, consisting of memory cells arranged in multiple rows of memory cells; and

logical management tool, United, at least one Bank, and responsive to receiving the memory device activation commands of a single line to open a specific row in such a way that, if there are no open strings, when adopted by the activation command prompt then the exact line, at least one Bank open, and if the Bank opened another line, distinct from a specific line, when adopted by the activation command-line, the other line is closed and the specific line is opened.

2. The memory device of claim 1, wherein the memory device is a dynamic random-access memory, and the activation command string is received via the memory bus connected to the memory device, and data transfer on the memory bus is synchronized by the synchronization signal transmitted by the memory bus so that some of the data may be transmitted in each half clock cycle.

3. The memory device according to claim 1, wherein the logical means of programmable control for closing the other line only in CTE is to receive an explicit command pre-charging.

4. The memory device of claim 1, wherein the memory device provides a display, which is readable by another device via a memory bus to which the memory device is connected, on the ability of logical controls the memory device to open a specific row, and close to another line in response to receiving the command activation line to open a specific row.

5. The memory device according to claim 4, in which the display also provides a description of the period of time required by the memory device to close another line.

6. The memory device according to claim 5, containing separately available non-volatile storage device, which can be read indication of the ability of logical controls the memory device to open a specific row, and close to another line in response to the activation command prompt.

7. Device control memory, which contains:

the first storage location in which data is stored relative to the rows in the Bank of memory cells in the memory device; and

logical management tool appeals committed to memory cells connected with the first storage location to validate the data in the first storage location to determine open whether a particular string is in the Bank, on which I validate the data in the first storage location, to determine open if another row if the particular row is not already open, to send commands activation line and waiting for a first predetermined period of time, to make the activation command prompt to open a specific row, if it is determined that the Bank specific line is not open and there are no other open strings before passing the access command involving the Bank, and to transfer commands the activation of a single line, which also involves team pre-charging, and expectations during the second predetermined period of time to be implemented as the activation command prompt to open a specific row, and the implied command pre-charging as part of the same team activation of a single line for closing the other line, if it is determined that the Bank specific line is not open and open another string before passing the access command involving the Bank.

8. Device control memory according to claim 7, in which the activation command string is passed to logic means controls the memory device via a memory bus that is connected as a control device and a memory device, and data transfer on the memory bus is synchronized by the synchronization signal transmitted by the memory bus is thus what part of the data it is possible to pass in each half clock cycle.

9. Device control memory according to claim 7 also containing a second storage location, coupled with logical management tool for storing readout from the memory device regarding whether the memory device to respond to receiving the command the activation of a single line to open a specific row in a Bank, in which you open another line, performing the pre-charging operation for closing the other line and command activation line to open a specific row.

10. Device control memory according to claim 9, in which the second storage location also stores an indication from a memory device on the length of time required by the memory device to perform the operation of pre-charging for closing another string.

11. Device control memory according to claim 9, wherein the logical control refers to the second storage location to determine whether the memory device to respond to reception of the activation commands prompt to open a specific row in a Bank, in which you open another line, performing the pre-charging operation for closing the other line and command activation string for opening specific with the rocky.

12. A computer system that contains:

processor;

a memory device having at least one Bank in which many memory cells organized in rows; and

a memory controller coupled to the processor and memory device, for transmitting commands activation string for opening a specific line, at least one Bank of memory devices, and expectations during the first predetermined period of time, to the memory device operation was performed activation line before sending the command to access a specific row, if there are no open strings, at least one Bank, and to transfer commands the activation of a single line with the implicit operation of pre-charging to open a specific row, at least one Bank of the memory device and waiting for the second predetermined period of time to be executed as mentioned, the operation of pre-charging associated with the activation command of a single line for closing the other line and activation of the row-related activation command of a single line, before sending the command to access a specific line, if you have opened another line, distinct from a specific line.

13. Computer system 12, in which the memory controller also will gain logic means for receiving the indication from the memory device on can the memory device to respond to the transmission controller memory activation commands prompt to open a specific row, at least one Bank when you open another line, at least one Bank, performing the pre-charging operation for closing the other line and operation activation line to open a specific row.

14. A computer system according to item 13, in which the memory controller also includes logic means for receiving from the memory device an indication of the time required to perform pre-charging, and to wait for the second predetermined period of time, the length of the second predetermined period of time determined at least partially based on the indication from the memory device in relation to the time required to perform pre-charging.

15. Computer system 12, in which the memory controller and the memory device are connected through a memory bus, data which is synchronized by the synchronization signal transmitted on the bus, and being part of the data can be transmitted at least every half clock cycle.

16. Method for memory management, containing the following steps:

the definition is open or not concrete is th row in the Bank of memory cells, in which many memory cells arranged in rows in the memory device;

the definition is open or there is another line in the Bank, if a particular line is closed;

transfer activation commands the first line of the memory device for opening a specific line and wait for a first predetermined period of time, to the memory device operation was performed activation prompt before sending to the memory device commands for operation data access affecting a particular line, if it is determined that the Bank has no open strings; and

the transfer of command the activation of the second row of the memory device and wait for a second predetermined period of time, to the memory device were performed as operation activation string for access to data concerning specific string, if it is determined that the Bank opened another string.

17. The method according to item 16, containing the receiving the indication from the memory device regarding whether or not the memory device the opportunity to respond to the activation command prompt to open a specific row in a Bank when a particular line is closed and the other line is open, perform the pre-charging operation for closing the other line and operation activation string for opening concr the things of the string.

18. The method according to 17, also containing said transmission activation commands prompt the memory device to open a specific row in the Bank with the transfer of commands pre-charging the memory device for closing the other line at the Bank, which is open, if the memory device is no indication that the memory device supports the implementation of the pre-charging operation for closing the other line without issuing pre-charging.

19. Method for memory management, containing the following steps:

the reception team activation line to open a specific row in a Bank of memory cells, in which many memory cells organized in rows;

the operation activation line in response to the activation command of a single line to open a specific row, if the Bank has no open strings; and

performing as the pre-charging operation in response to the activation command of a single line for closing the other line, and the activation operation of the line to open a particular row if the particular row is closed and the other line is open.

20. The method according to claim 19, containing software memory controller the indication of availability to respond to command the activation string for activating a specific row in the Bank executing the command pre is preliminary charging for closing the other rows in the Bank in addition to command the activation line to open a specific row, if a particular line is closed and the other line is open.

21. Machine-readable media containing code which, when executed by a processor in an electronic device instructs the electronic device to perform the following steps:

check whether the memory device to respond to the activation command prompt to open a specific row in a Bank of memory cells having multiple memory cells arranged in rows, performing as the pre-charging operation for closing the other line and activation operation line for opening a particular row if the particular row is closed and the other line is open;

programming the memory controller to send the command, activation of a single line for activating a specific row in a Bank when a particular line is closed and the other line is open, and waiting for a predetermined period of time, perform the memory device commands, such as pre-charging for closing the other line and activation commands prompt for opening a specific line, before sending the device memory access commands affecting a particular string.

22. Machine-readable medium according to item 21, also directs the processor to determine the length of the predetermined period of time based on the features is from the memory device relative to the period of time, required to perform the pre-charging operation in response to receiving the command activation string.



 

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