Random sequences generator

FIELD: electricity.

SUBSTANCE: random sequences generator relates to computing processes, in particular, to discrete sequences generators and may be used in digital computers, TV, telecommunication systems, in generation of the orthogonal address sequences, as well as in the data protection systems. The said generator consists of the clock pulse generator, NO-component, n-digit counter, two AND-components, one shift register, function number register and trigger. The generator incorporates the units of generation of producing sequence, the key and the module 2 adder.

EFFECT: wider functions of the Wolsch function generator thanks to possibility of generation of random sequences.

2 cl, 2 dwg, 3 tbl

 

The invention relates to computer technology, in particular to the generators of discrete sequences, and can be used in digital computing devices, television, telecommunication systems when forming orthogonal address sequences, and information security systems.

Known generator of the Walsh function, contains a master oscillator, a shift register, the register number function, item NO, item And trigger, and the output of the register function rooms connected to the parallel information input of the shift register, the output of the master oscillator connected to the clock input of the shift register and to the input element, output element and a serial output of the shift register through the element And is connected to the counting input of the trigger (see USSR author's certificate No. 1076892, CL G06F 1/02, 1982).

However, this generator has significant complexity due to the large number of digits used in the shift register (2n-1 with 2n generated by the Walsh functions), since each bit of the shift register is a trigger.

The closest to the technical nature of the claimed invention is the generator of the Walsh function, containing the master oscillator, the element is NOT, the shift register, the register number function, element, And trigger, the n-bit counter and Supplement the sustained fashion element And (see RF patent №2275683, CL G06G 7/26, 2006).

The disadvantage of this device is its limited functionality, namely the lack of formation on the basis of the Walsh function derived sequences.

The purpose of the invention is to enhance the functionality of the generator of the Walsh function by providing the possibility of forming derivative sequences.

The invention consists in the implementation of the following method of forming derivative sequences.

It is known that the function (or sequence) Walsh, having a property of mutual orthogonality for all sequences, built on a unified algorithmic rule (i.e. part of the same ensemble of sequences), at the same time have very poor autocorrelation properties, which makes their use impractical in modern telecommunication systems.

Improve the autocorrelation properties of the Walsh sequences can be achieved through the formation of derived sequences. For this sequence of Walsh one of the ensemble must be literally stacked with producing a sequence of equal length sequences of Walsh, but with better autocorrelation properties of the I. These properties produce sequences correspond to the characteristic discrete sequence (CDA) (see: Sverdlik could BE Optimal discrete signals. M., "Soviet radio", 1975).

Comparative characteristics maximum emission periodic (Pak FA) and aperiodic (AACP) correlation functions of the Walsh sequences with length l=16, and sequences generated by combining sequences of Walsh and the CDA, are shown in table 1.

Type KFThe sequence of WalshDerived sequence
Rmax(m)Rmin(m)m(x)Rmax(m)Rmin(m)m(x)
The Pak FA1-1-0,039of 0.5330-0,333-0,0710,02
AACF0,866-0,944-0,0710,2780,311-0,421-0,0040,071

The table shows that the size of the maximum emission Rmax(m) cor is elezioni functions and largest variance emissions of side lobes of the correlation functions derived sequence significantly exceed the corresponding sequence of Walsh.

For the formation of the characteristic discrete sequences in the proposed generator uses the following algorithm:

1. The source data for the formation of the CDA is the modulus p, is equal to the desired duration of the sequence, which is a simple integer positive number, and the integral element θ over the field GF(p).

2. The steps are formed in two arrays of numbers: M(1) dimension R and M(2) dimension (R-1). Forming the array of M(1) is to determine at each step, the element number of the array by calculating the value (A+1) mod p (where A=(A'×θ) mod p, And' the value of a, obtained in the previous step calculations, and in the first step A=1) and assigning to the given element value equal to the step number calculation. The first element of the array M(1) is set to "1". The formation of the array M(2) is to assign the i-th element of the array (i - number calculation step) value (A+1) mod p, obtained in this step of the computation.

3. Upon completion of the formation of both arrays based on them incrementally formed the CDA in accordance with the following rule:

Hi=(M(1)j) mod 2, where j=(M(2)i)+1) mod p,

where i is C the step of calculation

Example

Let p=7, θ=5. In this case it is necessary to produce the (R-1)=6 computation steps for the formation of arrays of M(1) and M(2). At each step must be computed the value of A=(A'*θ) mod p. As the first step of the calculation A=1, the second A=(1*5) mod 7=5, the third A=(5*5) mod 7=4, the fourth A=6, the fifth And=2, on the sixth And=3. Thus, the second array element M(1) takes the value 1, the sixth - 2, fifth - 3, seventh - 4, the third is 5, the fourth - 6. The first element of the array M(2) takes the value (A+1)=2, the second 6, and the third is 5, the fourth is 0, the fifth - 3, sixth - 4.

Thus, upon completion of the formation of arrays of M(1) and M(2) will have the following form:

M1=[1 1 5 6 3 2 4], M2=[2 6 5 0 3 4].

Further, in accordance with paragraph 3 of the algorithm is formed the desired numeric sequence. The first element of the sequence H1=(M(1)(M(2)1)+1) mod 2=(M(1)3) mod 2=(5) mod 2=1. The second element of the sequence H1=(4) mod 2=0. Similarly, formed the rest of the elements in the sequence.

Thus, the resulting sequence will have the form:

H=1 0 0 1 0 1.

After the formation of the generating sequence of character she is modulo 2 with sequences of Walsh. The result of the addition will be the desired derivative of the sequence.

Figure 1 presents the scheme of the generator derived sequences, Phi is .2 - diagram of the processing unit produces the sequence.

The generator of the derived sequences consists of a generator 1 clock pulses, block 2 forming produces a sequence of key 3, item 4, the n-bit counter 5, the first item And 6, the shift register 7 register function rooms 8, of the second element And 9, the trigger 10, the adder 11 in module 2.

The output of the register function number 8 is connected to the parallel information input of the shift register 7, the output of the generator 1 clock pulses connected to the input of the key 3, and to the third input of block 2 of the producing formation sequence, the first output of which is connected to the control input of the key 3, the second output to the second input of the adder 11 in module 2, the exit key 3 is connected to the clock input of the shift register 7 and to the input element 4, the output element 4 and the serial output of the shift register 7 through the element And 9 connected to the counting input of the trigger 10, the shift register 7 is closed in the ring the feedback circuit through the element And 6, the second input is connected to the output of the high-order bit of the counter 5, the counting input of which is connected to the output of the key 3.

In the initial position of the key 3-open on the first and second input devices, respectively, serves the value of the integral element θ and module R. the high-order n-razryadnogo the counter 5 is set in the one state, and the remaining bits in the zero state, the trigger 10 is in one state.

Before you begin code combination representing a truncated code is the sequence number of Walsh, rewritten from the register 8 function rooms in the register 7 offset.

Binary code is the sequence number of Walsh, which must be recorded in the register 7 of the shift is determined by the following tables:

a) for N=4 (where N is the volume of the system sequences of the Walsh)

Table 1
Decimal sequence number of WalshThe binary number sequence of WalshBinary code is the sequence number of the Walsh
000
101
2

3
10

11
The combination stored in the register 7 offset

b) for N=8

Table 2
Decimal sequence number of WalshThe binary number sequence of WalshBinary code is the sequence number of the Walsh
000
1001
2010
3011
4100
5101
6

7
110

111
The combination stored in the register 7 offset

C) for N=16

Table 3
Decimal sequence number of WalshThe binary number sequence of WalshBinary code is the sequence number of the Walsh
00000
10001
20010
3UN
40100
50101
60110
70111
81000
91001
101010
111011
121100
131101
14

15
1110

1111
The combination stored in the register 7 offset

The formation of derived sequences begins with the start of the generator 1 clock pulses. From the output of the clock pulses fed to the input of counter 3 and to the third input of block 2 of the producing formation sequences.

Block 2 forming the generating sequence (figure 2) contains the control block 12, the key 13, the control unit 14, a multiplier 15 for the module, OR element 16, a counter 17, the first ROM 18, block 19 forming the remainder of the first adder 20, the switching block 21, the second ROM 22, block 23 forming the remainder of a modulo-2, the second adder 24.

In the initial position into the first and second inputs of the control block 12 serves accordingly, the value of the integral element θ and p module, and the data inputs are disconnected from the respective outputs of the block. The third output of the control block 12 serves to transmit to the control unit information on the value of the modulus and the change in modulus and a primitive element.

The formation produces the sequence begins with the appearance of the first unit clock pulse at the input of the key 13 and the first input of the control unit 14. In the initial position of the input key 13 is connected to the first output, so a single character from the first output key 13 goes n the first input of the multiplier 15. As the first stage to the other inputs of the multiplier 15 and the module data is not available, a single pulse is sent to a least significant bit of the output of the multiplier, which in binary form the number "1" is fed to the input of the first adder 20, and the feedback circuit. In the first adder 20 arriving at its input is increased by one by adding a unit in the least significant bit of the binary number. From the output of the first adder 20 received code number "2" is supplied to the first input of the switching block 21, the second input of which receives the value output from the counter 17. As with the first key 13 clock pulse through the OR element 16 is also fed to the counting input of the counter 17, the output of the counter on the first beat will be formed is "1". Given that on the first beat to the first input of the switching block 21 receives the value of the number "2", the value of the number "1" is written into the second cell of the second ROM 22. The first cell of the second ROM 22 has a value of "1".

From the output of the first adder 20 of the received code number is also supplied to the first input unit 19 form a residue. As the first stage to the second input unit 19 form a residue code module is not supplied, the value of the number "2" from the output unit 19 form a residue is input to the first ROM 18, which is written in the first cell.

After completion of the first clock pulse of the control unit 14 to the first output generates a signal for switching the input key 13 from the first to the second output and the second output signal for connecting the inputs of the account code of the integral element and module for respectively the first and second outputs of the control block 12. On the second and subsequent cycles of operation, the clock pulses read served on the clock input of the multiplier 15 for the module, as well as through the element OR 16 at the counting input of counter 17. At each step in the multiplier 15 and the module is multiplication modulo (the value of which is supplied to the fourth input of the multiplier) of the generated values in the given block in the previous cycle and received by the feedback circuit to the second input of the multiplier, the value of the integral element received at the third input of the multiplier.

The value obtained from the output of the multiplier 15 is supplied to the feedback circuit and to the input of the first adder 20. After the increase per unit is obtained from the output of the first adder 20 is supplied to the first input of the switching block 21, where defines the address of the cell of the second ROM 22 into which is written the value received from the counter 17 and to the first input unit 19 form a residue, to the second input of which receives the value of the module. From the output unit 19 form a residue obtained mn is the treatment received at the input of the first ROM 18, where is written in the i-th cell (i is the number of the cycle).

Thus, at each step, starting from the second, in the first ROM 18 alternately in each cell, starting from the second will be recorded the value of the remainder modulo p from the value of the number formed in the multiplier 15 for the module and increased by one, i.e. (A+1) mod p, (a+1)-th cell of the second ROM 22 will be recorded value of i (i is the number of the cycle).

Upon completion of the (p-1)-th cycle (p - module) unit 14 controls the first output generates a signal on the input key 13 on the third output of this block and the second output signal to disable the first and second outputs of the control block 12. On the third output control unit 14 will generate a signal to switch on the key 3 and the clock pulses on the elements of the generator is responsible for generating sequences of Walsh.

Under the influence of clock pulses coming from the output of the key 3 to the clock input of the register 7 of the shift, the information recorded in it, shifted and supplied to one input of the second element And 9, to the second input of which receives the inverted clock pulse. Information from the output of the register 7 offset is supplied also to one of the inputs of the first item And 6, to the second input of which receives a single potential output high-order bit of the counter 5. Information from the output of the first item And 6 will post the AMB to the input of the register 7 offset as long while the high order bit of the counter 5 will be located in a single state. Since the counter 5 has n bits, and before beginning his work in his eldest discharge was recorded as "1", it will happen in 2n-1cycles of operation of the generator 1. Thus, in the case 7 of the shift in the feedback circuit can be written (2n-1-1) characters that came out of it, and, therefore, they will re-fed to the input of the second element And 9, i.e. at the input of the second element And 9 will eventually do not truncated and the full code sequence number of Walsh.

The voltage at the output of the second element And 9 is strobilaceum with each binary interval minimum duration has one gate, and the duration of each of the gate is equal to half the duration of the clock interval. The signals from the input of the second element And 9 come to the counting input of the trigger 10 pre-installed in a single state. The moments of occurrence of logical units on the output of the second element And 9 correspond to the points of change of sign of the generated sequences of Walsh, the output of the trigger 10 is formed corresponding to the sequence of Walsh. The elements of a sequence of Walsh output trigger 10 receives at the first input of the adder 11 in module 2.

Simultaneously, in block 2 of the producing formation PEFC is the sequences of clock pulses from the third output of the key 13 will be transmitted to the clock inputs of both ROMs. Under their influence the value of each cell of the first ROM 18 in turn, starting with the first cell will be connected to the output of the first ROM 18, incremented at the second adder 24 and be received at the second input of the second ROM 22, which will determine the address of the cell whose value at this stage must be received by the output of the second ROM 22. This value will be the input unit 23 of the formation of residues modulo 2. With this unit, which is the second exit block 2 forming produces a sequence of symbols "1" or "0" will be transmitted to the second input of the adder 11, where the module 2 will be formed with the symbols of the Walsh sequence. At the output of the adder 11 in module 2 will form the elements of a derived sequence.

In case of changing the duration of the generating sequence (module p) or organization (primitive element θ) at the third output of the control block 12 is formed a signal, which goes to the second input of the control unit 14. The block 14 on the first entry will generate a signal on the input key 13 to the first output, the third input signal to shut down the key 3, the fourth output signal to reset the counter 17, after the formation of the derived sequence in accordance with the above algorithm.

1. Gene is ATOR derived sequences, contains the clock, item NO, n-bit counter, the first and the second element And the shift register, the register number function, trigger, and the output of the register function rooms connected to the parallel information input of the shift register, the output of the item and the serial output of the shift register through the element And is connected to the counting input of the trigger, the shift register is closed in a ring feedback circuit through the element And the second input is connected to the output of the high-bit counter, characterized in that it introduced the shaping unit produces the sequence key and modulo 2, and the generator output clock pulses connected to the input of the key, and to the third input of the processing unit produces the sequence, the first output of which is connected to the control input of the key, the second output to the second input of the adder modulo 2, the output of the key is connected to the clock input of the shift register to the input element and to the counting input of the counter, the first input of the processing unit produces a sequence connected to the input account code primitive element, the second input of the processing unit produces the sequence is connected to the input account code module, the trigger output is connected to the first input of the adder modulo 2, the output of which is output is enerator.

2. The device according to claim 1, characterized in that the processing unit produces a sequence contains a control unit, a key, a control unit, a multiplier module, element, OR counter, the first and second ROM, block the formation of the remainder, the first and second adder, the switching unit, the processing unit residue modulo 2, and the first input of the processing unit produces a sequence connected to the first input of the control unit, the second input of the processing unit produces a sequence connected to the second input of the control unit, the third input of the processing unit produces the sequence is connected to the input key and the first input of the control unit, to the second input which is connected to the third output control unit, the first output control unit connected to the third input of the multiplier module, the second output control unit connected to the fourth input of the multiplier module and to the second input of the block forming residues, the first output control unit connected to the control input of the key, the second output control unit connected to the third input of the control unit, the third output control unit is the first output of the processing unit produces the sequence, the fourth output control unit connected to the input of the reset of the counter, the first key is connected to the first input will multiply the I module and to the first input element OR the second output of the key is connected to the clock input of the multiplier module and to the second input of the OR element, the output of which is connected to the counting input of the counter, the third output of the key is connected to the clock inputs of both the ROM, the output of the multiplier module is connected to the input of the first adder and to the second input of the multiplier module, the output of the first adder connected to the first input of the switching unit, the second input of which is connected to the output of the counter and to the first input of the block form a residue, the output of the switching unit connected to the first input of the second ROM, the output of block forming residues connected to the input of the first ROM, the output the first ROM is connected to the input of the second adder, the output of the second adder connected to the second input of the second ROM, the output of the second ROM is connected to the input of the block forming the remainder of a modulo-2, the output of this block is the second output of the processing unit produces the sequence.



 

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