# Device and method for encoding-decoding low density block codes with parity check in mobile communications system

FIELD: mobile communications, in particular, device and method for encoding-decoding low density block codes with parity check.

SUBSTANCE: the method includes stages, at which dimensions of parity check matrix are determined on basis of speed of encoding during encoding of information with low density block code with parity check and length of code word; parity check matrix of certain dimensions is divided onto a predetermined number of blocks; blocks are classified as blocks, corresponding to informational part; permutation matrices are positioned in predetermined blocks among blocks classified as first checking part, and identity matrices are positioned in full lower triangular form in predetermined blocks among blocks, classified as second checking part; and permutation matrices are positioned in blocks classified as informational part, resulting in minimal cycle duration being maximized and weight values being irregular on the coefficients graph of low density block code with parity check.

EFFECT: increased reliability of data transmission and improved correcting ability of low density code with parity check.

__The scope of the invention__

The present invention relates in General to mobile communication systems and in particular to a device and method of encoding-decoding block codes low-density parity (NPC) (LDPC).

__The level of technology__

With the introduction of cellular mobile communication systems in the United States in the late 1970s, South Korea began to provide service voice communication system advanced mobile phone (WUMT) (AMPS) analog mobile communication system of the first generation (1G). In the mid-1990s, South Korea commercialized system multiple access, code-division multiplexing (mdcr) (CDMA) mobile communication system of the second generation (2G)to provide a voice service and low-speed data transfer.

In the late 1990s, South Korea has partially deployed international mobile telecommunication system IMT-2000 system for mobile communications third generation (3G), aimed at advanced wireless multimedia services, global roaming and service of high-speed data transmission. This mobile communication system of the third generation was developed to transfer data at high speed according to the rapid increase in data volumes serviced. That is, the mobile communication system of the third opening is of turned into a system of communication with the service packet, and this communication system with packet transmitting packets of data to multiple mobile stations and designed to transfer bulk data. Communication system with service packet is designed for high speed packet.

System for mobile communications third generation develops in the mobile communication system of the fourth generation (4G). The mobile communication system of the fourth generation is in the process of standardization for standardization interaction and integration between wired network and wireless network beyond simple wireless services, which were provided by the previous system for mobile communications. Wireless networks should be developed technology to transfer large amounts of data up to the level of bandwidth available in the network wired connection.

Because of the required high-speed and high-bandwidth communication system capable of processing and transmitting data such as image and radio data, as well as simple as data services, voice communication, it is necessary to increase the efficiency of transmission system using an appropriate channel coding scheme to improve the performance of the system. System for mobile communications inevitably manifests errors due to noise, interference and attenuation is according to channel conditions during data transmission. The error causes loss of data.

In order to reduce the loss of data due to error, it is possible to improve the reliability of the mobile communication system through the use of different methods of error detection. One method using error-correcting code is the most popular method of error detection. Below is a description of the turbo code and code low-density parity (nppc), which are typical of detecting error codes.

__Turbo code__

Turbo code is a detection of the error code used in the synchronous mobile communication system of the third generation, and in an asynchronous mobile communication system of the third generation. It is well known that for high-speed data transmission turbo code exceeds the gain in performance of the convolutional code, previously used as the primary error-correcting code. In addition, the turbo code is advantageous in that it can effectively correct an error caused by noise generated in the communication channel, thereby increasing the reliability of data transmission.

__Code nppc__

Code NPC can be decoded using the algorithm of iterative decoding on the basis of the algorithm is the summation of the multiplication of the count ratios. Due to the fact that on the encoder code NPC uses based on the algorithm summation-multiplication algorithm of iterative decoding, it is less complex than the decoder for the turbo code. In addition, the decoder for the code nppc easy to implement using the decoder of parallel processing in comparison with the decoder for the turbo code. When the code nppc is expressed through the graph of the coefficients on the graph of the coefficients of the code nppc there are cycles. It is well known that iterative decoding on the graph of the coefficients of the code NPC, where there are cycles is less than optimized (suboptimal). In addition, it is experimentally proved that the code nppc has excellent performance under iterative decoding. However, when the graph of the coefficients of the code nppc there are many cycles of short length, the code NPC suffers from performance degradation. Therefore, research to develop a method of constructing such a code NPC that on the graph of the coefficients of the code nppc not had cycles of short length.

The encoding process code NPC turns in the encoding process, which uses a matrix of parity, low density scales due to the characteristics of the generating matrix, usually with a high density of scales. "Weight" is an element with a non-zero value among the elements of generating matrix and matrix parity. In particular, if the partial matrix corresponding PR is Werke even parity in the matrix of parity, has a regular format, possibly more efficient encoding.

Because the code nppc includes various codes with a non-zero value, it is very important to develop an efficient encoding algorithm and the algorithm is efficient decoding for different types of codes NPC to enter the code NPC in practical use. In addition, since the matrix of the even parity code NPC defines the performance characteristics of code NPC, it is very important to construct the matrix parity with excellent performance. That is, the effective matrix parity with excellent performance, the efficient encoding algorithm and the algorithm is efficient decoding must be considered simultaneously in order to generate high-performance code NPC.

One code NPC is defined by a matrix of parity, in which major elements have a value of 0 and minor elements except for the elements having a value of 0 have a value of 1. For example, the code nppc (N, j, k) is a linear block code having a block length N, and is defined by a loose matrix of parity, in which each column has j elements with a value of 1, each row has k elements with the value 1, and all elements except elements with a value of 1, are set to 0.

To the d nppc, in which the weight value of each column in the matrix parity is fixed at "j", and the weight value of each row in the matrix parity is fixed at "k", as described above, is called "regular code NPC". Here, the weight value represents the number of scales. Unlike regular code nppc, code NPC, in which the weight value of each column in the matrix of the even parity and the weight value of each row in the matrix parity is not fixed, is called "irregular code NPC". It is well known that irregular code nppc better performance than regular code NPC. However, in case of irregular code NPC due to the fact that the weight value of each column and the weight value of each row in the matrix parity is not fixed, i.e. they are irregular, the weight value of each column in the matrix of the even parity and the weight value of each row in the matrix parity must be regulated to ensure superior performance.

Now, with reference to figure 1, will be described matrix parity code nppc (8, 2, 4) in the example code nppc (N, j, k).

Figure 1 is a diagram illustrating a matrix parity normal code nppc (8, 2, 4). Figure 1 is a matrix of N parity codepc (8, 2, 4) consists of 8 columns and 4 rows, and the weight value of each column is fixed at 2, and the weight value of each line is fixed at 4. Due to the fact that the weight value of each column and the weight value of each row in the matrix parity are regular, as described above, the code nppc (8, 2, 4), shown in figure 1, becomes a regular code NPC.

Count ratios code nppc (8, 2, 4), described in connection with figure 1, will now be described below with reference to figure 2.

Figure 2 is a diagram illustrating a graph of the coefficients of the code nppc (8, 2, 4) of figure 1. Figure 2 graph of the coefficients of the code nppc (8, 2, 4) consists of 8 nodes of variables x_{1}211, x_{2}213, x_{3}215, x_{4}217, x_{5}219, x_{6}221, x_{7}223 and x_{8}225, and 4 check nodes 227, 229, 231 and 233. When an item with a weight, i.e. with a value of 1, there is at the point where the i-th row and j-th column of the matrix of the even parity code nppc (8, 2, 4) intersect each other, there is a branch between the node xj and the i-th check node.

Since the matrix of the even parity code nppc has a small weight value, as described above, it is possible to perform decoding through a process of iterative decoding, even in a block code with a relatively large length, which shows the performance of approaching the bandwidth limit of pic is the competitiveness of sinonasal channel, such as turbo code, while continuously increasing the block length block code. It is proved that the process of iterative decoding of code NPC using the method of thread migration is almost complete approach to the process of iterative decoding of turbo code performance.

To generate high-performance code NPC, should be satisfied the following conditions.

__(1) Should be taken into account cycles on the graph of the coefficients of the code nppc__

"Cycle" refers to the loop formed by the edges connecting the variable nodes to the check nodes on the graph of the coefficients of the code NPC, and the length of the cycle is defined as the number of faces that make up the loop. Cycle, having a greater length, means that the number of edges connecting the variable nodes to the check nodes and the components of the loop on the graph of the coefficients of the code nppc, great. In contrast, the loop having a small length, means that the number of edges connecting the variable nodes to the check nodes and the components of the loop on the graph of the coefficients of the code nppc, small.

As the cycles in the graph of the coefficients of the code nppc become longer, the efficiency performance of the code NPC increases for the following reasons. That is, when the column of coefficients of the code NPC generated long cycles, it is possible to prevent such a deterioration of the working features, the istics of as the lower limit of errors, displays when too many cycles of small length are on the graph of the coefficients of the code NPC.

__(2) consider the efficient coding code nppc__

It is difficult to subject code NPC coding in real time in comparison with a convolutional code or a turbo code because of its high complexity encoding. To reduce the complexity of the encoding code nppc, proposed code with the re-accumulation (MO) (RA). Code MO also has a limitation in reducing the complexity of the encoding code NPC. Therefore, you should consider efficient coding code NPC.

__(3) consider the distribution of ranks of the graph of the coefficients of the code nppc__

Usually irregular code NPC superior in performance regular code NPC, because the graph of the coefficients of irregular code NPC has different grades. "Rank" refers to the number of edges connected to variable nodes and check nodes in the graph of the coefficients of the code NPC. Further, the distribution of ranks" on the graph of the coefficients of the code NPC refers to the ratio of the number of nodes having a particular rank to the total number of nodes. It is proved that the code NPC having a specific distribution of ranks is excellent in performance.

Figure 3 is a diagram illustrating a matrix parity conventional block code NPC. Before the date the description of figure 3,
it should be noted that the block code nppc is a new code nppc, which takes into account not only efficient coding, but also efficient storage and improved performance matrix parity, and that the block code nppc is the code nppc, advanced by generalizing patterns regular code NPC. Figure 3 matrix of the parity block of code NPC divided into a number of partial blocks, and the matrix of permutations is shown in each of these partial blocks. Figure 3 "R" represents a matrix of permutations of size N_{S}×N_{S}and the upper index (or exponent) a_{ij}matrix permutation P is equal to either 0≤a_{ij}≤N_{S}-1 or a_{ij}=∞. Figure 3 p represents the number of rows of partial blocks, and q represents the number of columns of the partial blocks. "i" means that the corresponding matrix of permutations is located in the i-th row of the partial block matrix parity, and "j" means that the corresponding matrix of permutations is located in the j-th column of the partial blocks of the matrix parity. That is,there is a matrix of permutations, located in a partial block, intersecting i-th row and j-th column.

Now with reference to figure 4 will be described matrix permutations.

Figure 4 is a diagram illustrating a matrix of permutations P in figure 3.
As shown in figure 4, the matrix of the permutation P is a square matrix of size N_{S}×N_{S}and each of the N_{S}the columns that make up the matrix of the permutation P has weight 1, and each of the N_{S}the rows comprising a matrix of permutations P, also has a weight of 1.

Figure 3 matrix of permutations with the upper index a_{ij}=0, i.e. the matrix R^{0}permutations is the identity matrixand the matrix of permutations with the upper index a_{ij}=∞i.e. the matrix R^{∞}is the zero matrix.

In full matrix parity block code nppc shown in figure 3, due to the fact that the total number of rows is N_{S}×p, and the total number of columns is N_{S}×q (for p≤q), when the full matrix of the even parity code nppc has full rank, the encoding speed can be expressed as equation (1) regardless of the size of partial blocks.

(1) |

If a_{ij}≠∞ for all i and j, the matrix of permutations corresponding to the partial blocks are zero matrices, and partial blocks are regular code NPC, in which the weight value of each column and the weight value of each row in each of the of atric permutations,
the respective partial blocks, equal to p and q, respectively. Here, each of the matrices permutations corresponding to the partial blocks will be referred to as "partial matrix".

Due to the fact that the full matrix parity has (p-1) dependent rows, the encoding speed is higher than the encoding speed, calculated using equation (1). In the case of a block of code NPC, if weight is the position of the first row of each of the partial matrices that make up the full matrix of the parity, and the weight are the positions of the other (N_{S}-1) rows. Therefore, the required memory size is reduced to 1/N_{S}compared with the case where the weights are chosen regularly to store information across the full matrix parity.

Figure 5 is a diagram illustrating a matrix parity regular block code NPC. Shown in figure 5 matrix parity is a matrix of the parity code of the array (s, r), i.e. regular block code NPC. The proposed code of array (s, r) is a typical regular block code NPC, and the pin array (s, r) corresponds to the block code NPC for N_{S}=s and q=s and p=r figure 3. Here "s" is an odd Prime number and "r" is always satises r≤s.

Matrix parity code Massi is a (s,
r) has s^{2}columns and r×s lines, and its rank becomes r×(s-1). The reason that the rank of the matrix of the parity code of the array (s, r) is r×(s-1), is that in the case where r is a partial matrix in the row direction of the matrix of the parity code of the array (s, r)if s rows in each of the partial matrices are summed, generated matrix in which all elements have the value 1. That is, due to the fact that generated r of rows in which all elements have the value 1, it can be understood that there is r dependent rows. Therefore, the speed of R_{array}encoding code of the array (s, r) can be expressed by equation (2):

(2) |

As described above, it can be noted that in the case of a code array (s, r) in the graph of coefficients has no cycle of length 4 because of its algebraic properties, and can also reduce the memory capacity, as described above.

However, because the code of the array (s, r) is a regular code NPC, he stands below the irregular code NPC in performance deterioration. Next, block code NPC cannot guarantee superior performance because of its randomness below. That is, the code array (s, r), although considered effective coding, still has a high complexity Cody is Finance, and in the code array (s, r), although there is a cycle with length 4, there is also a cycle of length 6. Further, since the distribution of grades is not considered, there is a deterioration in performance.

6 is a diagram illustrating a matrix parity conventional block code NPC. Before the description Fig.6, it should be noted that irregular block code nppc is a block code nppc specified by modifying the code of the array described in connection with figure 5, taking into account the effective coding. In the matrix parity irregular block of code nppc shown in Fig.6, "I" marks the identity matrix of size s×s and "0" marks the zero matrix of size s×s. Matrix parity irregular block of code nppc shown in Fig.6, corresponds to the matrix of the parity block of code NPC for N_{S}=s, q=k and p=r figure 3.

For efficient encoding code NPC coding is allowed in linear time due to the formation of a partial matrix corresponding to the parity of the full matrix parity as a full lower triangular matrix, as shown in Fig.6. The structure of the full matrix parity, i.e. the structure of the partial matrix corresponding to an information word, and a partial matrix corresponding to the parity will be is written here below. When a partial matrix corresponding to the parity, is formed in this way as a full lower triangular matrix, the matrix parity always has full rank due to their structural characteristics. Therefore, the length of the modified code block of the array, i.e. irregular code NPC becomes ks, and the speed of R coding can be expressed by equation (3):

(3) |

However, the irregular code NPC on 6 having a matrix of parity, in which the partial matrix corresponding to the parity, has the form of a full lower triangular matrix, is more efficient than the array, but does not take into account the grade distribution on the graph of the factors that should be considered during code generation NPPs, and were not considered deleting cycles of short length. So he has a lower than irregular code NPC with random-correcting ability. Accordingly, there is a need for irregular code NPC that maximizes correcting capability.

__The invention__

Thus, the purpose of the present invention is to provide a device and method of encoding-decoding code NPC with Maxi is siromoney correcting ability in the mobile communications system.

Another objective of the present invention is to provide a device and method of encoding-decoding code NPC with maximized minimum length of a cycle in the mobile communications system.

Another objective of the present invention is to provide a device and method of encoding-decoding code NPC with minimized complexity of coding in a mobile communication system.

The first object of the present invention is a method of generating a check matrix for parity block code low-density parity (nppc)to improve correcting ability, and matrix parity has an information part corresponding to the information word, and the first test part corresponding to the parity, and the second test part corresponding to the parity. This method includes steps in which: find the size of the matrix parity based on the coding rate used when encoding a data word of the block code NPC, and the length of the code word; share matrix parity, having found the size to a predetermined number of blocks; classify the blocks into blocks corresponding to an information part, the blocks corresponding to the first test part, and the blocks corresponding to the second Avenue is varochnoi part; place the permutation matrix in predetermined blocks among the blocks classified as the first test part, and place identity matrix in the full lower triangular form in predetermined blocks among the blocks classified as the second test part; and place the permutation matrix in blocks classified as the information part, so that the minimum length of a cycle is maximized, and the weights are irregular on the graph of the coefficients of the block of code NPC.

The second object of the present invention is a method of encoding a block of code low-density parity (nppc). This method includes the following steps: generate a matrix of parity, consisting of an information part corresponding to an information word, and the first test part and the second test parts, each of which corresponds to the parity, and define the method of deteremine and interleave method according to the matrix of the even parity; find the probability values of the reception signal; generating the first signal in the current decoding process by subtracting the signal generated in a previous decoding process from the probability values of the received signal; departmeat the first signal using the method of deteremine; find the values of verojatnost is by receiving depriming signal; generate the second signal by subtracting depriming signal from the probability values depriming signal; and a second alternating signal using the method of alternation and iteratively decode perenesennyj signal.

The third object of the present invention is a method of encoding a block of code low-density parity (nppc). This method includes the following steps: generate the first signal by multiplying the information word by a first partial matrix previously generated matrix parity, consisting of an information part corresponding to an information word, and the first test part and the second test parts, each of which corresponds to the parity; generate a second signal by multiplying the information word of the second partial matrix matrix parity; generate a third signal by multiplying the first signal by a matrix product of a third partial matrix and the inverse matrix from the fourth partial matrix of the matrix parity; generate a fourth signal by adding the second signal and the third signal; generating a fifth signal by multiplying the fourth signal, the fifth partial matrix of the matrix parity; generate a sixth signal by summing vtoro what about the signal and the fifth signal; generate a seventh signal by multiplying the sixth signal to the matrix product of a third partial matrix and the inverse matrix from the fourth partial matrix of the matrix parity; and multiplexers information word, the fourth signal as a first test part and the seventh signal as a second test parts according to the format code block NPC.

The fourth object of the present invention is a method of generating a check matrix for parity to improve correcting ability, and this matrix parity is placed in a matrix of rows and columns of a set of partial information blocks and many test partial blocks, the matrix parity is divided into an information part, consisting of matrices of partial information blocks, and a test section consisting of matrices test partial blocks, with each partial information block consists of a matrix representing the set of information bits, each of the partial test blocks consists of a matrix representing multiple bits of parity, each of the information partial block and partial test blocks exist in multiple rows in the matrix parity divided by the first information full the HQ, the first check matrix and the second check matrix, each of the partial information blocks and test partial blocks exist in many other lines except for the number of rows divided by the second information matrix, the third test matrix and the fourth check matrix; and the first and second information matrix, the first and third test matrix, and the second and fourth check matrix is placed in the same columns, respectively. The method includes the following steps: summarize the third test matrix and the product of the fourth test matrix, the inverse matrix of the second check matrix and the first check matrix so that the sum is the unit matrix; find a transposed vector of the first test vector corresponding to the first check matrix and the third test matrix, by multiplying the amount of the second information matrix and the works of the fourth test matrix, the inverse matrix of the second check matrix and the first matrix on the information vector corresponding to the first data matrix and the second information matrix; and are transposed vector of the second test vector corresponding to the second check matrix and the fourth test matrix, p is the multiplication of the inverse matrix of the second check matrix by the sum of the first data matrix and a transposed vector information vector and the works of the first check matrix, and transposed vector of the first test vector.

The fifth object of the present invention is a method of generating a check matrix for parity block code low-density parity (nppc)to improve correcting ability, and the matrix parity placed in a matrix of rows and columns from the set of partial blocks, and matrices permutations generated by shifting an identity matrix of size N_{S}×N_{S}on pre-determined exponent according to each of the partial blocks placed in each of the partial blocks. The method includes the following steps: find the block loop block code NPC as the first value; and finding a second value by multiplying the second value by a value determined by subtracting the sum of the exponents of the permutation matrices with odd exponent among matrices permutations placed in each of the partial blocks of the sum of exponents of permutations with an even exponent among matrices permutations placed in each of the partial blocks; and performing a control operation so that each of the partial blocks has a cycle corresponding to the product of the first value and the second value.

The sixth object of the present invention is a device for decoding a block code low PLO is particular with parity (nppc). This device includes a decoder for variable nodes for connecting the variable nodes according to the weight of each column of the matrix parity, consisting of an information part corresponding to an information word, and the first test part and the second test parts, each of which corresponds to the parity according to a predetermined control signal, and for finding the probability values of the received signal; a first adder for subtracting a signal generated in a previous decoding process from the signal issued from the decoder node variables in the current decoding process; departmental to deteremine signal issued from the first adder, using the method deteremine installed according to the matrix of the even parity; the decoder node checks for the connection of the check nodes according to the weight of each line constituting the matrix of the parity, and for finding the probability values of the signal issued from deteremines, according to a predetermined control signal; a second adder for subtracting the signal issued from deteremines, from the signal issued from the decoder node checks; interleaver to interleave signal issued from the second adder, using the method of alternation that is installed according to the matrix PR is checking even parity, and for deducing peremienko signal to the decoder of the variable nodes and the first adder; and a controller for generating a check matrix for parity and control method deteremine and method for interleave according to the matrix parity.

The seventh object of the present invention is a device for encoding a block of code low-density parity (nppc). This device includes a first matrix multiplier for multiplying a received data word to the first partial matrix matrix parity, consisting of an information part corresponding to an information word, and the first test part and the second test parts, each of which corresponds to the parity; the second matrix multiplier for multiplying a data word to the second partial matrix matrix parity; the third matrix multiplier for multiplying a signal issued from the first matrix multiplier, for matrix multiplication of a third partial matrix and the inverse matrix from the fourth partial matrix of the matrix parity; a first adder for adding the signal issued from the second matrix multiplier, and the signal issued from the third matrix multiplier; the fourth matrix multiplier DL the multiplication signal, issued from the first adder, the fifth partial matrix of the matrix parity; a second adder for adding the signal issued from the second matrix multiplier, and the signal issued from the fourth matrix multiplier; the fifth matrix multiplier for multiplying a signal issued from the second adder by a matrix product of a third partial matrix and the inverse matrix from the fourth partial matrix of the matrix parity; and switches for multiplexing a data word, the output signal of the first adder as a first test part and the output signal of the fifth multiplier as a second test parts according to the format code block NPC.

__Brief description of drawings__

The above and other objectives, features and advantages of the present invention will become clearer from the following detailed description together with the accompanying drawings, in which:

Figure 1 is a diagram illustrating a matrix parity normal code nppc(8, 2, 4);

Figure 2 is a diagram illustrating a graph of the coefficients of the code nppc (8, 2, 4) of figure 1;

Figure 3 is a diagram illustrating a matrix parity conventional block code NPC;

Figure 4 is a diagram illustrating a matrix P of permutations in figure 3;

Figure 5 is a Ki the scheme, illustrating the matrix parity regular block code NPC;

6 is a diagram illustrating a matrix parity regular irregular block of code NPC;

7 is a diagram illustrating the structure of the loop code block nppc, matrix parity which consists of 4 partial matrices;

Fig is a diagram illustrating the structure of the loop code block nppc, matrix parity which consists of 6 partial matrices;

Fig.9 is a diagram illustrating the structure of block loop block code NPC;

Figure 10 is a diagram illustrating the structure of block loop block code nppc in which duplicated 6 partial matrices from the matrix parity;

11 is a diagram illustrating the structure of block loop block code nppc in which duplicated 7 partial blocks of the matrix parity;

Fig is a diagram illustrating a matrix of parity, having the form of a full lower triangular matrix;

Fig is a diagram illustrating a matrix of parity, having a form similar to the form of a full lower triangular matrix;

Fig is a diagram illustrating a matrix of parity on Fig, which is divided into 6 partial blocks;

Field scheme, illustrating the transposed matrix of the partial matrix b, shown in Fig, the partial matrix E, the partial matrix T, and the inverse matrix of the partial matrix T;

Fig is a diagram illustrating a matrix of the parity block of code nppc according to a variant implementation of the present invention;

Fig is a flowchart of an algorithm illustrating the procedure of generating matrix of the parity block of code nppc according to a variant implementation of the present invention;

Fig is a flowchart of an algorithm illustrating the procedure of encoding the block of code nppc according to a variant implementation of the present invention;

Fig is a block diagram illustrating the internal structure of encoder for a block code nppc according to a variant implementation of the present invention; and

Fig is a block diagram illustrating the internal structure of a decoding device for block code nppc according to a variant implementation of the present invention.

__A detailed description of the preferred option exercise__

Now will be described in detail the preferred implementation of the present invention with reference to the attached drawings. In the following description, detailed description of known functions and configurations, including the military here omitted for brevity.

The present invention provides a scheme for encoding and decoding high-irregular code low-density parity (nppc). The present invention provides a scheme for encoding and decoding irregular code nppc, which maximized the minimum length of a cycle in the graph of coefficients minimizes the complexity of encoding and optimized distribution of ranks on the graph of the coefficients.

The term "cycle", since it is associated with the count ratios code nppc, refers to the loop formed by the edges connecting the variable nodes to the nodes of the checks in the column of coefficients, and the length of the cycle is defined as the number of faces that make up this loop. The cycle, which has a large length, means that the number of edges connecting the variable nodes to the nodes of the checks that make up this loop in the column of coefficients is large. As the cycles in the graph of coefficients are generated all over long operating characteristics code nppc become better. On the contrary, when the column of ratios, there are many cycles of short length, the code NPC deteriorates in its corrective ability, because there's such performance deterioration as the lower limit of errors. That is, when a lot of cycles with short length exist on the graph of the coefficients of information about a specific node, belonging to the cycle with a short length, starting from it, returns after a small number of iterations. As an increasing number of iterations, the information is returned to the appropriate site frequently, so the information may not be updated correctly, which causes deterioration correcting ability of the code NPC.

7 is a diagram illustrating the structure of the loop code block nppc, matrix parity which consists of 4 partial matrices. Before giving a description of Fig.7, it should be noted that the block code nppc is a new code nppc, which takes into account not only efficient coding, but also efficient storage and improved performance matrix parity. Block code NPC is also code nppc, advanced by generalizing patterns regular code NPC. Matrix parity block code nppc shown in Fig.7, is divided into 4 partial block, the sloping line represents the position where the elements with the value 1, and the parts other than the inclined parts represent positions where the elements with the value 0. In addition, "R" represents the same permutation matrix, and a permutation matrix, described in connection with figure 4. Here, the matrix P permutation, as described in connection with figure 4, is the Quadra is Noah matrix size of N_{
S}×N_{S}in which each of N_{S}the columns that make up the matrix P of permutations, has a weight of 1, and each of the N_{S}the rows comprising a matrix P of permutations, has a weight of 1. Here, the "weight" is an element with a non-zero value among the elements of the matrix parity.

In order to analyze the structure of the loop code block nppc shown in Fig.7, the element with a value of 1, located in the i-th row of the partial matrix R^{and}, is defined as the reference element, and the element with a value of 1, located in the i-th row will be denoted as "0-point". Here "partial matrix" will refer to the matrix corresponding to the partial block. 0-point is located at (i+a)-th column of the partial matrix R^{and}.

Element with a value of 1 in the partial matrix P,^{b}located in the same row as 0-point, will be referred to as "1-point". For the same reason as 0-point, 1-point is located at (i+b)-th column of the partial matrix P^{b}.

Further, the element with a value of 1 in the partial matrix R^{with}located in the same column, and 1 point will be referred to as "2-point". Since partial matrix R^{with}is the matrix obtained by shifting the corresponding columns of the identity matrix I to the right modulo N_{S}in C, 2-point raspolagaet the (i+b-c)-th row of the partial matrix R^{
with}.

In addition, the element with a value of 1 in the partial matrix P,^{d}located in the same row as 2-point, will be referred to as "3-point". 3-point is located at (i+b-c+d)-th column of the partial matrix P^{d}.

Finally, the element with a value of 1 in the partial matrix R^{and}located in the same column, and 3-point, will be referred to as "4-point". 4-point is located at (i+b-c+d-a)-th row of the partial matrix R^{and}.

In the loop structure of the code nppc shown in Fig.7. if the cycle length of 4 exists, 0-point and 4-point are in the same position. That is, the ratio between the 0-point and 4-point is determined by equation (4):

i≅i+b-c+d-a(mod N_{S}ori+a≅i+b-c+d(mod N _{S}) | (4) |

Equation (4) can be rewritten in equation (5):

a+c≡b+d(mod N_{S}) | (5) |

As a result, when satisfied, the ratio in equation (5), generates a cycle of length 4. In General, when the 0-point and 4-point identical to each other, sets the ratio i≡i+m(b-c+d-a)(mod N_{S}and satisfies the following relationship in equation (6):

In other words, if a positive integer with a minimum value among the positive integers that satisfy the equation (6) for given a, b, c, and d, is defined as "m", the cycle length 4m becomes a cycle of minimal length in the structure of the loop code block nppc shown in Fig.7.

In conclusion, as described above, for (a-b+c-d)≠0, if GCD(N_{S}a-b+c-d)=1, then m=N_{S}. Here GCD(N_{S}a-b+c-d) is a function to calculate the greatest common divisor of integers N_{S}and a-b+c-d. Therefore, the cycle of length 4N_{S}becomes a cycle of minimum length.

Described in connection with Fig.7 analysis cycle block code NPC can be applied even when the number of blocks constituting the matrix of the parity block of code NPC exceeds 4, i.e. when the number of partial matrices constituting the matrix of the parity exceeds 4. Now, with reference to Fig, description will be given of the structure of cycles code NPC, in which the number of partial matrices constituting the matrix of the parity, more than 4.

Fig is a diagram illustrating the structure of cycles block of code nppc, matrix parity which consists of 6 partial matrices. Matrix parity block code nppc shown in Fig, consists of 6 partial matrices. As shown in Fig, the sloping line represents the iciu, where are the items with a value of 1, and the parts other than the parts of the sloping lines represent the positions where the elements with the value 0. In addition, "R" represents the same matrix permutations that matrix permutations described in connection with figure 4. When the structure of the cycles code nppc shown in Fig, analyzed by the method described in connection with Fig.7, the cycle length 6m becomes a cycle of minimum length.

In General, when the 0-point and 6m-point, first of all, identical to each other, set the ratio i≡i+m(b-c+d-e+f-a)(mod N_{S}), and satisfies the following relationship shown in equation (7):

m(a-b+c-d)≡0(mod N_{S}) | (6) |

m(b-c+d-e+f-a)≡0(mod N_{S}) | (7) |

In other words, if a positive integer with a minimum value among the positive integers that satisfy the equation (7) for given a, b, c, d, e and f is defined as "m", the cycle length 6m becomes a cycle of minimal length in the structure of the loop code block nppc shown in Fig.

In conclusion, as described above, for (a-b+c-d+e-f)≠0, if GCD(N_{S}a-b+c-d+e-f)=1, then m=N_{S}. Therefore, the cycle of length 6N_{S}becomes a cycle of minimum length.

For the above block of code NPC you can display the following rules.

__Rule 1__

If the cycle length is Oh 2l exists in the block code nppc, should be satisfied with the condition of equation (8):

and_{1}+a_{3}+a_{5}+...+a_{2l-1}≡a_{2}+a_{4}+a_{6}+...+a_{2l}(mod N_{S}) | (8) |

In equation (8) a_{i}(i=1, 2, ..., 2l) is the exponent of matrix permutation, through which pass through the cycle of length 2l. That is, a cycle of length 2l passes through the partial blocks constituting the code parity block code NPC in order→→...→. Here not all values of a_{i}must necessarily be different from each other, and the corresponding cycle can again go through the same partial blocks.

__Rule 2__

"m" will be defined as the minimum positive integer that satisfies the equation (9).

0 (mod N_{S}), (1≤i, j≤2l) | (9) |

In equation (9) (a_{i}is the exponent of matrix permutation, chosen so that using block-based cycle is formed throughout the matrix of the even parity. As described in Rule 1, not all values of a_{i}must necessarily be different from each other, and the corresponding loop is prohodit again in the same partial blocks.
As a result of partial matrixhave the structure of cycles in which the minimum length is 2lm.

The structure of cycles block of code nppc easy to analyze using Rule 1 and Rule 2. For example, using Rule 1 and Rule 2 it is possible not only to determine how many cycles the minimum length of 6 distributed in the code array, but also easy to analyze the characteristic patterns using block-based cycle (block cycle") block code NPC, which will be described here below. Block cycle is an important factor used to adjust the length of the cycle for forming the matrix of the parity, and block cycle will be described with reference to figures 9, Rule 1 and Rule 2.

Fig.9 is a diagram illustrating the structure of block loop block code NPC. Figure 9 assumes that each of the blocks constituting the block code NPC, has a weight of 1, and when the blocks form a loop, said block cycle is formed. Fig.9 illustrates the left block cycle, made up of 4 blocks, block loop, made up of 6 blocks, and block the loop formed by 8 blocks. As described in Rule 1 and Rule 2, although the block is formed a loop with a short length, if the partial matrix corresponding to the blocks constituting the block cycle, SEL is Ana accordingly, you can perform a control operation so that a cycle with a short length are not generated in real matrix parity. However, when multiple block loops are duplicated in the block code nppc, the minimum length of real cycles in the block cycles is reduced. As a result, the cycles of short length undesirable generated in real matrix parity.

Now, with reference to figure 10, Rule 1 and Rule 2, will be given a description of the problem when multiple block loops are duplicated in the block code NPC, and reasons why you should avoid duplicated block cycles for generating the matrix of the even parity code NPC.

Figure 10 is a diagram illustrating the structure of block cycles block of code nppc in which duplicated 6 partial matrices in the matrix parity. The following sequential order of the blocks can be seen by the arrows shown in figure 10.

→→→→→→→→→→→ →

Exhibitors partial matrices, following the above sequential order of the blocks satisfies equation (10) regardless of the values of N_{S}.

and_{1}-a_{2}+a_{4}-a_{3}+a_{5}-a_{6}+a_{2}-a_{1}+a_{3}-a_{4}+a_{6}-a_{5}≡0(mod N_{S}) | (10) |

If equation (10) is applied to equation (9)described in Rule 2, then m=1. Therefore, in the case of block code nppc shown in figure 10, where there is a block cycle in which duplicated 6 partial matrices, even if you select any partial matrix, a component of the whole matrix of the even parity selected partial matrix always includes the structure of cycles of length 12. That is, if the block of code nppc shown in figure 10, where there is a block cycle in which duplicated 6 partial matrices, the minimum length of a cycle matrix parity is limited to a maximum of 12.

11 is a diagram illustrating the structure of block cycles block of code nppc in which duplicated 7 partial blocks of the matrix parity.

Figure 11 shows the structure of block cycles block of code NPC where duplicated 7 is a partial block matrix parity, and neither is sleduushii sequential block order can be viewed on the arrows, figure 11 shows.

→→→→→→→→→→→→→→

Exhibitors partial matrices, following the above sequential order of blocks that satisfy equation (11) regardless of the values of N_{S}.

and_{1}-a_{2}+a_{4}-a_{5}+a_{7}-a_{6}+a_{2}-a_{1}+a_{3}-a_{4}+a_{6}-a_{7}+a_{5}-a_{3}≡0(mod N_{S}) | (11) |

If equation (11) is applied to equation (9)described in Rule 2, then m=1. Therefore, in the case of block code nppc shown figure 11, where there is a block cycle in which duplicated 7 partial matrices, even if you select any partial matrix, a component of the whole matrix of the even parity selected partial matrix always includes the structure of cycles dlinoi. That is, if the block of code nppc shown figure 11, where there is a block cycle in which duplicated 7 partial matrices, the minimum length of a cycle matrix parity is limited to a maximum of 14.

As described above, if too many cycles are duplicated between the blocks that make up the matrix of the parity in the block code NPC, there is a constraint when maximizing the minimum length of the loop regardless of how to choose a partial matrix matrix parity, which causes deterioration in performance of the block code NPC. Therefore, the matrix of the even parity is generated in the block code NPC so that generated less block cycles, whereby to prevent the generation of redundant block cycles.

Next will be described how the generating matrix of the parity block of code NPPs taking into account the effective coding in addition to the block of the loop.

In the present invention as a method of encoding a block of code nppc method will be used Richardson-Urbanke. Because as a method of encoding method is used Richardson-Urbanke, the complexity of encoding can be minimized, so that the shape matrix of the even parity may be similar to the form of a full lower triangular matrix.

F. g is a scheme, illustrating the matrix parity, having the form of a full lower triangular matrix. Matrix parity, shown in Fig, has the form of a full lower triangular matrix and consists of the information part and a test part. The information part is part of the matrix parity displayed on real information word in the encoding process block code NPC, and the testing part is part of the matrix parity displayed in real parity in the process of encoding a block of code NPC. In the testing part, as shown in Fig, the zero matrix and the partial matrix are unity matrix I as their starting points, and partial matrices have a full lower triangular form.

Fig is a diagram illustrating a matrix of parity, having a form similar to the form of a full lower triangular matrix. Matrix parity, shown in Fig differs from the matrix parity, having the form of a full lower triangular matrix, shown in Fig, in the testing part. On Fig upper index (or exponent) a_{ij}matrix P of permutations is either 0≤a_{ij}≤N_{S}-1 or a_{ij}=∞. Matrix permutations with the upper index a_{ij}=0, i.e. the matrix R^{0
permutations is the identity matrixand the matrix of permutations with the upper index aij=∞i.e. the matrix R∞permutations is the zero matrix. On Fig m is the line number of partial blocks that are displayed on the information part and q is the column number of partial blocks that appear on the test part. "i" means that the corresponding matrix of permutations is located in the i-th row of the partial block matrix parity, "j" means that the corresponding matrix of permutations is located in the j-th column of the partial blocks of the matrix parity. That is,is the matrix of permutations, located in a partial block, intersecting i-th row and j-th column.}

In addition, the upper indices a_{i}x, y permutation matrices that appear on the test part, represent the upper indices of the permutation matrices, however, for convenience of explanation, these superscripts a_{i}x, y are the reference letters a great format to distinguish it from the information part. That is, Fig P^{a1}-P^{am}are permutation matrices, these matrices P^{a1}-P^{am}permutations are arranged in a diagonal part of the test part. Superscripts a_{1}-a_{m}indexed sequentially.
Matrices P^{X}and P^{Y}is a matrix of permutations, however, for convenience of explanation, the matrix P^{X}and P^{Y}permutations are represented by the reference letters a great format to distinguish it from the information part.

If it is assumed that the block length block code NPC having a matrix of parity, shown in Fig is N, the complexity of the coding block of code NPC grows linearly with respect to the length N of the block.

The biggest problem code NPC having a matrix of parity on Fig, is that if the length of the partial block is defined as N_{S}generated N_{S}the check nodes, the ranks of which is always equal to 1 on the graph of the coefficients of the block of code NPC. Here the ranks of check nodes may not affect performance on the basis of the iterative decoding. Therefore, the standard code NPC based on the Richardson method-Urbanke does not include site inspections with rank 1. Therefore, the matrix parity on Fig will be assumed as the main matrix of the parity to construct a matrix of parity, to provide an efficient coding, not including site inspections with rank 1. In the matrix parity on Fig consisting of partial matrices, you are the PR partial matrix is a very important factor to improve the performance of block code nppc,
so finding an acceptable criterion for partial matrix also becomes a very important factor.

Therefore, when the generated block code nppc, the matrix of the even parity is generated with the following criteria development.

__Criteria development for the matrix parity block code nppc__

(1) the Test part is formed so that it had a fixed form.

The fact that the test piece has a fixed form, means that she has the configuration in which a single matrix are as shown in Fig, which will be described here below.

(2) Partial matrix with a lower rank are selected sequentially first.

In the present invention "rank" partial matrix refers to the rank of between 3 and 5. In addition, the partial matrix are placed so that when a partial matrix with low rank are selected sequentially first generated block as little as possible cycles, and the cycle of minimal length among partial matrices with low rank are formed as long as possible.

(3) Partial matrix with a high rank are formed sequentially after formed a partial matrix with low rank. When placed partial matrix with a high grade, the minimum cycle length is formed as long as possible.

Now Bud is t describes how the design matrix of the parity block of code NPC on the basis of the above criteria development for the matrix parity block code NPC.

To facilitate method development matrix parity block code NPC and method of encoding a block of code NPC, it is assumed that the matrix parity, shown in Fig, is formed with six private matrix, as shown in Fig.

Fig is a diagram illustrating a matrix of parity on Fig, which is divided into 6 partial blocks. On Fig matrix parity block code nppc shown in Fig, is divided into an information part s, the first testing portion of the p_{1}and the second testing portion of the p_{2}. The information part s is part of the matrix parity displayed on real information word in the encoding process block code nppc and the information part, described in connection with Fig. 12 and 13, however, for convenience of explanation, the information part s is an excellent reference letters. The first testing portion of the p_{1}and the second testing portion of the p_{2}are part of the matrix parity displayed in real parity in the process of encoding a block of code NPC, similar test pieces described in connection with Fig. 12 and 13, and the test part is divided into two parts.

Partial matrices a and C correspond to the partial blocks a and C the information part s, frequent cnie matrix and D correspond to a partial blocks b and D of the first test part of the p_{
1}and the partial matrix T, and E correspond to a partial blocks T and E. the second test part of the p_{2}. Although the matrix parity is divided into 7 partial blocks on Fig, it should be noted that "0" is not a separate partial block, and therefore the partial matrix T corresponding to the partial block T has a full lower triangular form, the same region where the zero matrix are placed on the main diagonal, is represented by "0". The process of simplification of the encoding method using the partial matrix information part s, the first test of the p_{1}and the second test part of the p_{2}will be described later with reference to Fig.

Partial matrix on Fig will now be described herein below with reference to Fig.

Fig is a diagram illustrating the transposed matrix of the partial matrix b, shown in Fig, the partial matrix E, the partial matrix T and its inverse matrix of the partial matrix So On Fig partial matrix In^{T}represents a transposed matrix of the partial matrix b, and the partial matrix T^{-1}is the inverse matrix of the partial matrix T.

is.

Matrix permutations, shown in Fig, for example, R^{A1}is the unit matrix. As described above, if the upper Indus the KS matrix permutation,
ie and_{1}0, R^{A1}is the unit matrix. Also, if the upper index of the permutation matrix, i.e. a_{1}increases according to a predetermined value, the permutation matrix is a cyclic shift of a predetermined set value, so that the matrix R^{A1}is the identity matrix.

Fig is a flowchart of an algorithm illustrating the procedure of generating matrix of the parity block of code nppc according to a variant implementation of the present invention. Before to describe pig, it should be noted that to generate a block code nppc need to find the size of the code words and the encoding rate of the block code nppc subject to generation and the size of the matrix parity must be determined according to the detected size of the code words and the coding rate. If the size of the code words in the block of code NPC is represented as N, and the code rate is represented as R, the size of the matrix parity becomes N(1-R)×N. in fact, the procedure of generating matrix of the parity block of code nppc shown in Fig, is performed only once, because the matrix of the even parity is generated first, and the generated matrix of the even parity is used all the time communication systems.

On Fig nusage 1711 controller divides the matrix parity of size N(1-R)×
N on the total number of p×q units, including R units on the horizontal axis and q blocks on the vertical axis, and then proceeds to step 1713. Since each of the blocks has a size of N_{S}×N_{S}the matrix parity consists of N_{S}×p columns and N_{S}×q lines. In step 1713, the controller classifies R×q blocks, separated from the matrix parity, on the information part s, the first testing portion of the p_{1}and the second testing portion of the p_{2}and then proceeds to steps 1715 and 1721.

In step 1715, the controller divides the data portion to a non-zero blocks, or non-zero matrix, and zero blocks, or zero matrix, according to the distribution of ranks, in order to guarantee the good performance of the block code NPC, and then proceeds to step 1717. Since the distribution of ranks, in order to guarantee the good performance of the block code nppc described above, its detailed description is omitted here. In step 1717, the controller finds such matricespermutations that a minimum cycle length of block cycle should be maximized, as described above, in the non-zero parts of the matrix in blocks having the lowest rank among blocks found according to the distribution of ranks, in order to guarantee the good performance of the block code NPC and use the proceeds to step 1719.
Here the matrixpermutation should be determined taking into account the block cycles not only the information part s, but also the first test of the p_{1}and the second test part of the p_{2}.

In step 1719, the controller randomly finds the matrixchanges in non-zero parts of the matrix in blocks having the lowest rank among blocks found according to the distribution of ranks, in order to guarantee the good performance of the block code NPC, and then ends the procedure. Here, even when you define the matrixpermutations, subject to application to a non-zero parts of the matrices in blocks having a high rank of the matrixpermutation should be determined so that the minimum cycle length block code nppc is maximized, and the matrixpermutations are determined based on the block cycles not only the information part s, but also the first test of the p_{1}and the second test part of the p_{2}. Example matricespermutation placed in the matrix of parity, is illustrated in Fig.

In step 1721, the controller divides the first testing portion of the p_{1}and the second testing portion of the p_{2}4 is a partial matrix b, the,
D and E, and then proceeds to step 1723. In step 1723 controller does not introduce a zero matrix, but introduces matrix R^{Y}andpermutation 2 partial block among the partial blocks constituting the partial matrix B, and then proceeds to step 1725. The way of introducing zero matrix, but matrix R^{Y}andpermutation 2 partial block among the partial blocks constituting the partial matrix B, already described with reference to Fig.

In step 1725, the controller enters the identity matrix I in the diagonal partial blocks of the partial matrix T, introduces a specific matrix,,...,permutation (i, i+1)-th partial blocks under the diagonal components of the partial matrix T, and then proceeds to step 1727. The method of introducing the unit matrix I in the diagonal partial blocks of the partial matrix T, and the introduction of specific matrices,,...,permutation (i, i+1)-th partial blocks under the diagonal components of the partial matrix T already described with reference to Fig.

In step 1727 controller introduces the partial matrix R^{X}in the partial matrix D, and then proceeds to step 1729. In step 1729, the controller enters the matrix/img>
permutation only in the last partial block in the partial matrix E, and then ends the procedure. The method of introduction 2 matricespermutation only in the last partial block among the partial blocks constituting the partial matrix E, already described with reference to Fig.

If a partial matrix In the partial matrix D and the partial matrix E are respectively formed in the matrix of the parity block of code nppc, the encoding process for the block of code NPC you can easily manage. Now, description will be given of the process of formation of the partial matrix b, the partial matrix D and the partial matrix E matrix parity, to easily control the encoding process for the block of code NPC.

When the matrix parity on Fig is divided into partial matrix described in connection with Fig the above way, it is possible to consider Fig.

When the vector__with__the code word is divided into an information part s, the first testing portion of the p_{1}and the second testing portion of the p_{2}as shown in Fig, this vector__with__code words can be divided into vector__s__a data word, the first test vector__p___{1}and the second test vector__p___{2}. In this case, the product matrix of the parity vector__with__Konovalova can be expressed as equation (12) and equation (13):

As^{T}+Bp_{1} ^{T}+Tp_{2} ^{T}=0 | (12) |

(ET^{-1}A+C)s^{T}+(ET^{-1}B+D)p_{1} ^{T}=0 | (13) |

In equation (12) T denotes transposition, as in equation (13)__p___{1} ^{T}relating to the first test vector__p___{1}can be calculated as:

p_{1} ^{T}=φ^{-1}(ET^{-1}A+C)s^{T}(φ≅ET^{-1}B+D) | (14) |

In equation (14), since the complexity of the coding block of code NPC proportional to the square of the matrix size φ, the present invention sets the matrix φused to calculate the first test vector__p___{1}as the identity matrix I. due to the installation of the matrix φ as the identity matrix I thus, the complexity of the coding block of code nppc is minimized. With reference to Fig will describe the installation process of the matrix φ as the identity matrix I.

Matrixpermutations will be fixed to the identity matrix I. In partial block, partial matrix T^{-1}shown in connection with Fig part
represents the multiplicationmatrixthe matrix. Matrix φ can be calculated using equations (15)-(17) below.

First, pig because the partial matrix E includes all zero matrix except for one partial block, partial product matrix E and the inverse matrix T^{-1}partial matrix T can be expressed as the product of the last row of the inverse matrix T^{-1}partial matrix T and the last block of the partial matrix E, as shown in equation (15):

ET^{-1}= | (15) |

If the product of the partial matrix E and the inverse matrix T^{-1}partial matrix T is multiplied by the partial matrix B, the result can be expressed as shown in equation (16):

ET^{-1}In= | (16) |

where k is a specific natural number, found according to the position R^{Y}.

When the product of the partial matrix E and the inverse matrix T^{-1}partial matrix T is multiplied by the partial matrix B, as shown in equation (16), since the partial matrix includes sun is a zero matrix except for the two partial blocks,
the multiplication is performed only on two partial blocks in the partial matrix B, thereby simplifying the calculation.

If D=P^{X}=and=I, φ=ET^{-1}B+D=I. Therefore, the matrix φ becomes the unit matrix I. the Equation (17) below in a condensed form expresses the condition that the matrix φ becomes the unit matrix I:

x≡a_{m}+()(mod N_{S}), a_{m}+()+y≡0(mod N_{s}) | (17) |

As described above with reference to equations (15)-(17), if the matrix φ is set as the identity matrix I, the encoding process for the block of code NPC can be simplified in its complexity.

Next, with reference to Fig, description will be given of the procedure of encoding the block of code NPC using matrix parity, developed in the present invention.

Fig is a flowchart of an algorithm illustrating the procedure of encoding the block of code nppc according to a variant implementation of the present invention. On Fig in step 1811, the controller accepts a vector__s__information words, and then proceeds to steps 1813 and 1815. Here it is assumed that the length of the vector__s__information words received for codiovan the block code nppc,
equal to k. In step 1813, the controller matrix multiplies vector__s__information word matrix (A__s__) checks the parity, and then proceeds to step 1817. Since the number of elements with value 1 is present at a partial matrix a, is much smaller than the number of elements with value 0 is present at a partial matrix a, matrix multiplication, vector__s__a data word and a partial matrix And matrix parity can be implemented with a relatively small number of calculations of amounts of works. In addition, since the position of elements with a value of 1 in a partial matrix a can be expressed by the position of the nonzero block and an exponent of matrix permutation to block matrix multiplication can be performed using simple calculations in comparison with the concrete matrix parity. In step 1815, the controller matrix multiplies the partial matrix With the matrix of the parity vector__s__information words (C__s__), and then proceeds to step 1819.

At step 1817, the controller matrix multiplies a matrix EM^{-1}the result of the matrix multiplication vector__s__a data word and a partial matrix And matrix parity (ET^{-1}And__s__), and then proceeds to step 1819. As described above, since the number of elements with a value of 1 in the matrix EM^{-1}very little, if tol is known to the Exhibitor of the permutation matrix corresponding block,
matrix multiplication can be performed easily. At step 1819, the controller calculates the first test vector__p___{1}by adding the O^{-1}And__s__and C__s__(__p___{1}=ET^{-1}And__s__+C__s__), and then proceeds to step 1821. Here the calculation of the addition is by calculating the Exclusive OR (XOR), which are formed of the same bits, the result of addition becomes "0", and when you add up the various bits, the result of addition becomes "1". That is, in the process of step 1819 calculated first test vector__p___{1}from equation (14).

In step 1821, the controller multiplies the partial matrix In matrix parity on the first test vector__p___{1}(In__p___{1}), folds In__p___{1}and A__s__(A__s__+B__p___{1}), and then proceeds to step 1823. As described in connection with equation (12), if the vector__s__a data word and the first test vector__p___{1}known, the inverse matrix T^{-1}partial matrix T in the matrix parity must be multiplied in order to calculate the second test vector__p___{2}. Therefore, at step 1823, the controller multiplies the vector (A__s__+B__p___{1})calculated in step 1821, the inverse matrix T^{-1}partial matrix T, to calculate the second test vector__p___{2}(__p___{2}=T^{-1}(A__s__+Bu>
p_{1}), and then proceeds to step 1825. As described above, if the only known vector__s__a data word of the block code NPC, you can calculate the first test vector__p___{1}and the second test vector__p___{2}. As a result, you get the vector code words. In step 1825, the controller transmits vector__with__a data word generated by the vector__s__a data word, the first test vector__p___{1}and the second test vector__p___{2}, and ends the procedure.

Fig is a block diagram illustrating the internal structure of encoder for a block code nppc according to a variant implementation of the present invention. On Fig the encoder for a block code NPC consists of a multiplier 1911 matrices And multiplier 1913 matrix C, the multiplier 1915 matrix EM^{-1}the first adder 1917, multiplier 1919 matrix, the second adder 1921, multiplier 1923 matrix T^{-1}and switches 1925, 1927 and 1929.

When receiving the input signal, i.e. vector__s__information word length k encode block code nppc, the received vector__s__a data word is entered in each of the switch 1925, multiplier 1911 matrices and multiplier 1913 matrix C. the Multiplier 1911 matrix And multiplies vector__s/u>
a data word in the partial matrix And full matrix parity and outputs the result of multiplication by the multiplier 1915 matrix EM ^{-1}and the second adder 1921. The multiplier 1913 multiplies matrix With vectorsa data word in the partial matrix To full matrix parity and outputs the result of multiplication to the first adder 1917. The multiplier 1915 matrix EM^{-1}multiplies the signal is extracted from the multiplier 1911 matrix And a partial matrix EM^{-1}full matrix parity and outputs the result of multiplication to the first adder 1917.__

__The first adder 1917 folds signal, derived from a multiplier 1915 matrix EM ^{-1}and the signal is extracted from the multiplier 1913 matrix C, and outputs the result of addition to the multiplier 1919 matrix and switch 1927. Here the first adder 1917 computes the Exclusive OR bitwise basis. For example, when accepted as a vector of length 3 x=(x_{1}, x_{2}, x_{3}) and the vector of length 3 y=(y_{1},_{2},_{3}the first adder 1917 performs Exclusive OR operation on a vector of length 3 x=(x_{1}, x_{2}, x_{3}) and a vector of length 3 y=(y_{1},_{2},_{3}and outputs a vector of length 3 z=(x_{1}⊕y_{1}x_{2}⊕y_{2}x_{3}⊕y_{3}). Here the calculation of ⊕ pre which is the Exclusive OR calculation,
where are formed the same bits, the result of addition becomes "0", and when you add up the various bits, the result of addition becomes "1". That is, the signal output from the first adder 1917, becomes the first test vectorp_{1}.__

__The multiplier 1919 matrix multiplies the signal or the first test vector p_{1}output from the first adder 1917, a partial matrix To full matrix parity and outputs the result of multiplication to the second adder 1921. The second adder 1921 adds the signal output from the multiplier 1919 matrix, and the signal output from the multiplier 1911 matrix A, and outputs the result of multiplication by the multiplier 1923 matrix T^{-1}. The second adder 1921 as the adder 1917, performs Exclusive OR operation on the signal output from the multiplier 1919 matrix, and the output signal from the multiplier 1911 matrix A, and outputs the result to multiplier 1923 matrix T^{-1}.__

__The multiplier 1923 matrix T ^{-1}multiplies the signal output from the adder 1921, a partial matrix T^{-1}and outputs the result of multiplication to the switch 1929. Here the output of the multiplier 1923 matrix T^{-1}becomes the second test vectorp_{2}. Switches 1925, 1927 and 1929 are included only in the time of the transfer sootvetstvujushej the signal.
That is, during the transfer vectorsinformation words included switch 1925; during transmission of the first test vectorp_{1}turns on the switch 1927; and during transmission of the second test vectorp_{2}turns on the switch 1929.__

__Through appropriate selection of the partial matrix full matrix of parity, as described above, matrix multiplication for ET ^{-1}relatively simplified, whereby simplified calculation for ET^{-1}Ands^{T}. In addition, the matrix φ becomes the identity matrix I, so that the calculation process for φ^{-1}to calculate the P_{1} ^{T}omitted.__

__As described above, the block code NPC ensures high performance memory for storing information associated with the matrix parity according to its structural characteristics, and provides an efficient encoding for the account of the respective partial matrix in the matrix parity. However, due to the fact that the matrix of the even parity is generated on a block-by-block basis, reduces the randomness. The reduction of randomness can cause deterioration in performance of the block code NPC. That is, because of the irregular block code NPC outperforming regular block code NPC as described the above,
the choice of the partial matrix to full matrix parity acts as a very important factor in the development of block code NPC.__

__Now, with reference to Fig, will be given a detailed description of the method of generating a block code nppc, which shows excellent performance, while providing efficient coding in the accounting cycle characteristics block code NPC.__

__Fig is a diagram illustrating a matrix of the parity block of code nppc according to a variant implementation of the present invention. On Fig for structural simplicity, the matrix of the parity block of code NPC set so that=I (i=1,..., m-1),=P ^{1}, R^{X}=P^{1}and R^{Y}=P^{-1}. In this case, as described above, the matrix φ becomes the unit matrix I, thereby ensuring efficient encoding. Block length partial matrix of the matrix parity is N_{S}=3. Therefore, R^{-1}=P^{30}. Since the number of blocks for each column in the matrix parity is 32, is generated matrix parity block code nppc a total length of 32×31=992 and encoding speed 1/2.__

__In the block code nppc shown in Fig becomes irregular block code nppc, ostasis of 15 blocks with weight values 2,
12 blocks with weight values 3 and 5 blocks with weight values 11 on the basis of each column of the matrix parity. Therefore, the distribution of grades in the block of code nppc shown in Fig, can be expressed by equation (18):__

f_{2}=15/32, f_{3}=12/32, f_{11}=5/32,=7/16,=9/16 | (18) |

__In equation (18) f _{i}denotes the ratio of variable nodes with rank i to all nodes of the variables on the graph of the coefficients of the block of code NPC, and f_{pi}denotes the ratio of the test nodes of rank i to all the check nodes on the graph of the coefficients of the block of code NPC. For example, if a block of code NPC with block length N_{S}=32 columns of the matrix parity corresponding to 15 knots variables among all 32 nodes variables on the graph of the coefficients of the block of code NPC have a weight value of 2, the columns of the matrix parity, 12 corresponding to the variable nodes have a weight value of 3, and the columns of the matrix parity corresponding to the 5 nodes of the variables are the weights 11. Even for the matrix parity corresponding to the check nodes, the weight can be taken into account in the same way as is done for nodes variables. The distribution of ranks, showing the TES in equation (18),
closely approximates the distribution of ranks of the code NPC to the ideal threshold value n. Further, in the case of a block of code nppc shown in Fig, the minimum length of a cycle that exists between the node with rank 2 and node 3 grade equal to 12, and the minimum cycle length between all nodes is equal to 16.__

__Next, with reference to Fig, description will be given of the decoding process block code NPC using code parity according to a variant implementation of the present invention.__

__Fig is a block diagram illustrating the internal structure of a decoding device for block code nppc according to a variant implementation of the present invention. On Fig decoders for block code NPC consists of 2000 nodes variables, the first adder 2015, deteremines 2017, the interleaver 2019, controller 2021, memory 2023, the second adder 2025, 2050 part of the test sites and block 2029 tough decisions. Part of 2000 nodes variable consists of the decoder 2011 variable nodes and switch 2013, as part of the 2050 check nodes consists of a decoder 2027 check nodes.__

__The received signal received over the air, is introduced into the decoder 2011 nodes of variables in part of 2000 nodes, variables, and the decoder 2011 computes probability values of the received signal, updates the calculated probability values and displays updated the s values of the probability to switch 2013 and the first adder 2015.
The decoder 2011 variable nodes connects nodes of the variables according to the matrix parity, installed in a decoding device for block code NPC, and performs a calculation updates with so many input and output values as "1" is connected to the variable nodes. The number "1"is connected with each node variables is identical to the weight of each of the columns that make up the matrix of the even parity. Therefore, the internal calculation of the decoder 2011 nodes variables varies according to the weight of each of the columns that make up the matrix of the even parity.__

__The first adder 2015 receives the signal output from the decoder 2011 variable nodes, and the output signal of the interleaver 2019 in the previous iterative decoding, subtracts the output signal of the interleaver 2019 in previous iterative decoding of the signal output from the decoder 2011 sites of the variables in the current process of decoding, and outputs the result of subtraction on departmental 2017. If the decoding process is the initial process of decoding, the output signal of the interleaver 2019 should be treated as "0".__

__Departmental 2017 determiae the signal output from the first adder 2015, according to a predetermined method, and outputs departmeny signal to the second adder 2025 and decoder 2027 check nodes. Depere the resident 2017 has an internal structure,
the corresponding matrix of parity, because the output value for the input values of the interleaver 2019 corresponding to detereminately 2017, becomes different according to the positions of the elements with a value of 1 in the matrix parity.__

__The second adder 2025 receives the output signal of the decoder 2025 test sites during the previous iterative decoding and output signal of deteremines 2017, subtracts the output signal of deteremines 2017 from the output signal of the decoder 2027 test sites during a previous decoding and outputs the result of subtraction to the interleaver 2019. The decoder 2027 test connects nodes check nodes according to the matrix parity, installed in a decoding device for block code NPC, and performs a calculation updates with so many input and output values as "1" is connected to the check nodes. The number "1"is connected with each of the check nodes, identical weight to each of the rows comprising a matrix of parity. Therefore, the internal calculation of the decoder 2027 check nodes varies according to the weight of each of the rows comprising a matrix of even parity checking.__

__Interleaver 2019 under the control of the controller 2021 punctuates the signal output from the second adder 2025, according to a predetermined method is in and displays perenesennyj signal to the adder 2015 and decoder 2011 node variables.
The controller 2021 reads associated with the method interleave the information in memory 2023 and controls the interleave method of interleaver 2019 according to a few associated with the method interleave information. In addition, if the decoding process is the initial process of decoding, the output signal of deteremines 2017 should be considered as "0".__

__By repeatedly performing the above process, the decoding device provides error-free high-performance decoding, and after the decoding device performs iterative decoding as many times as the number of iterations is set in advance, the switch disables 2013 decoder 2011 sites of the variables from the second adder 2015 and at the same time connects the decoder 2011 sites of the variables to the block 2029 tough decisions, so that the signal output from the decoder 2011 sites of the variables is input to the block 2029 tough decisions. Block 2029 hard decision hard decision on the output signal from the decoder 2011 nodes, variables, and outputs the result of the hard decision, and the output value of the block 2029 hard decision becomes final decoded value.__

__As can be understood from the preceding description, the present invention provides a block code NPC with maximized minimum length of a cycle in the mobile system is th link,
whereby maximized correcting capacity and improve performance. In addition, the present invention generates an effective matrix parity, whereby minimizing the complexity of the coding block of code NPC.__

__Although the invention is shown and described with reference to his particular preferred implementation, the experts will be clear that it is possible to make various changes in form and detail without departing from the essence and scope of the invention as defined by the attached claims.__

__1. Method of producing a matrix of the parity block code low-density parity (nppc), and matrix parity has an information part corresponding to the information word, and the first test part corresponding to the parity, and the second test part corresponding to the parity, containing the following steps:__

__determine the size of the matrix parity based on the coding rate used when encoding a data word of the block code NPC, and length code words;__

__share the matrix parity, having a certain size, a predetermined number of blocks;__

__classify the blocks into blocks, the relevant info is made use of parts,
blocks corresponding to the first test part, and the blocks corresponding to the second test part;__

__place the permutation matrix in predetermined blocks among the blocks classified as the first test part, and will churn matrix permutation in full lower triangular form in predetermined blocks among the blocks classified as the second test part; and__

__place the permutation matrix in blocks classified as the information part, so that the minimum length of a cycle is maximized, and the weights are irregular on the graph of the coefficients of the block of code NPC.__

__2. The method according to claim 1, in which the process of placing permutation matrices in blocks classified as the information part, so that the weights irregular, contains the following steps: define the blocks, where the permutation matrix will be placed among the blocks classified as the information part; place a matrix of permutations for blocks with a grade less than a predefined rank among some of the blocks, which will include the permutation matrix, so that maximized the minimum length of a cycle; and randomly place the permutation matrix for blocks with a grade greater than or equal to a predetermined among certain blocks, which will include matrix purest the mode.__

3. The method according to claim 1, in which the matrix of permutations in full lower triangular form in predetermined blocks among the blocks classified as the second test part are unit matrices.

4. The method according to claim 3, in which the step of placing matrices permutations in predetermined blocks among the blocks classified as the first test part, and placing the unit matrix in the full lower triangular form in predetermined blocks among the blocks classified as the second test part, contains the following steps: classify the blocks constituting the first test part, into blocks corresponding to the first partial block, and blocks corresponding to a second partial block, and classify the blocks constituting the second test part, into blocks corresponding to the third partial block, and blocks corresponding to the fourth partial block; place matrix permutations in predetermined blocks among the blocks classified as the first partial block and a second partial block; place identity matrix in the full lower triangular form in predetermined blocks among the blocks classified as the third partial block; and placing the matrix of permutations in a predetermined block among the blocks classified as the fourth partial block.

5. The method according to the .4, in which the blocks where the identity matrix is placed among the blocks classified as the third partial block, blocks are the components of the diagonal among the blocks classified as the third partial block.

6. The method according to claim 4, further containing the step where the host matrix permutations in the lower blocks, parallel blocks, where the identity matrix is placed among the blocks classified as the third partial block.

7. The method according to claim 4, in which the block where the matrix permutations are placed among the blocks classified as the fourth partial block is the last block among the blocks classified as the fourth partial block.

8. The method according to claim 4, in which the matrix permutations are determined so that the matrix defined by adding the matrices permutations placed in the second partial unit, and the matrix product of matrices permutations placed in the fourth partial block, inverse matrix, matrices, permutations, placed in the third partial block, and matrices permutations placed in the first partial unit are unit matrices.

9. A device for decoding a block code low-density parity (nppc), containing

the decoder node variables for the connection of the variable nodes according to the weight of each column, is leaving the matrix parity, consisting of an information part corresponding to an information word, and the first test part and the second test parts, each of which corresponds to the parity according to a predetermined control signal, and for finding the probability values of the received signal;

a first adder for subtracting a signal generated in a previous decoding process from the signal issued from the decoder node variables in the current decoding process;

departmental to deteremine signal issued from the first adder, using the method of deteremine installed according to the matrix of the even parity;

the decoder node checks for the connection of the check nodes according to the weight of each row of the matrix parity, and for finding the probability values of the signal issued from deteremines, according to a predetermined control signal;

a second adder for subtracting the signal issued from deteremines, from the signal issued from the decoder nodes check;

interleaver to interleave signal issued from the second adder, using the method of alternation that is installed according to the matrix parity, and to derive peremienko signal to the decoder of the variable nodes and the first adder; and

the controller DL the generating matrix of the even parity and control method deteremine and method for interleave according to the matrix parity.

10. The device according to claim 9, in which the controller generates a matrix parity by finding the size of the matrix parity, so this size corresponds to the coding rate used to encode a data word of the block code NPC, and the length of the code words, the separation matrix of the parity of a certain size on a predetermined number of blocks, the classification of these blocks into blocks corresponding to an information part, the blocks corresponding to the first test part, and the blocks corresponding to the second test part, host matrices permutations in predetermined blocks among the blocks classified as the first test part, host matrices permutations in full lower triangular form in predetermined blocks among the blocks classified as the second test part, and accommodation matrices permutations in the blocks classified as the information part, so that the minimum length of a cycle is maximized and the weight values are irregular on the graph of the coefficients of the block of code NPC.

11. The device according to claim 10, in which the matrix of permutations in full lower triangular form in predetermined blocks among the blocks classified as the second test part are unit matrices.

12. The device according to claim 11, inwhich the controller finds the blocks, where matrix permutations will be placed among the blocks classified as the information part; allocates a matrix of permutations for blocks with a grade lower than a predefined rank among some of the blocks, which will include a matrix of permutations, so that the minimum length of a cycle is maximized; and randomly allocates a matrix of permutations for blocks with a grade greater than or equal to a predetermined rank among certain blocks, which will include a matrix of permutations.

13. The device according to claim 11, in which the controller classifies the blocks constituting the first test part, into blocks corresponding to the first partial block, and blocks corresponding to the second partial unit, classifies the blocks constituting the second test part, into blocks corresponding to the third partial block, and blocks corresponding to the fourth partial block, allocates a matrix of permutations in predetermined blocks among the blocks classified as the first partial block and a second partial block, places the identity matrix in the full lower triangular form in predetermined blocks among the blocks classified as the third partial block, and allocates a matrix of permutations in a predetermined block among the blocks classified as the fourth partial block.

14. The device according to claim 3, in which the controller places the identity matrix in blocks that make up the diagonal among the blocks classified as the third partial block.

15. The device according to item 13, in which the controller allocates a matrix of permutations in the lower blocks, parallel blocks, where the identity matrix is placed among the blocks classified as the third partial block.

16. The device according to item 13, in which the controller allocates a matrix of permutations in the last block among the blocks classified as the fourth partial block.

17. The device according to item 13, in which the controller finds the matrix of permutations, so that the matrix defined by adding the matrices permutations placed in the second partial unit, and the matrix product of matrices, permutations, placed in the fourth partial block, inverse matrix, matrices, permutations, placed in the third partial block, and matrices permutations placed in the first partial unit becomes a unit matrix.

18. A method of decoding a block code low-density parity (nppc), containing the following steps:

generate a matrix of parity, consisting of an information part corresponding to an information word, and the first test part and the second test parts, each of which corresponds to the verification of the e even parity, and define the method of deteremine and interleave method according to the matrix of the even parity;

determine probabilities of signal reception;

generate the first signal by subtracting the signal generated in a previous decoding process from the probability values of the received signal;

departmeat the first signal using the method of deteremine;

determine probabilities of depriming signal;

generate the second signal by subtracting depriming signal from the probability values depriming signal; and

alternating with the second signal using the method of alternation and iteratively decode perenesennyj signal.

19. The method according to p, in which the step of generating a check matrix for parity contains the following steps: determine the size of the matrix parity based on the coding rate when encoding information block code NPC and length code words; classify the blocks into blocks corresponding to an information part, the blocks corresponding to the first test part, and the blocks corresponding to the second test part; place matrix permutations in predetermined blocks among the blocks classified as the first test part, and will churn matrix permutations in full lower triangular form is in predetermined blocks among the blocks, classified as a second test part; and place a matrix of permutations in the blocks classified as the information part, so that the minimum length of a cycle is maximized and the weight values are irregular on the graph of the coefficients of the block of code NPC.

20. The method according to claim 19, in which the matrix of permutations in full lower triangular form in predetermined blocks among the blocks classified as the second test part are unit matrices.

21. The method according to claim 20, in which the step of placing permutation matrices in blocks classified as the information part, so that the weight values are irregular, contains the following steps: finding blocks, where there will be a matrix of permutations among the blocks classified as the information part; placement of permutation matrices for blocks with a grade less than a predefined rank among some of the blocks, which will include a matrix of permutations, so that the minimum length of a cycle is maximized; and the chaotic placement of matrices permutations for blocks with a grade greater than or equal to a predetermined rank among some of the blocks, which will include matrix permutations.

22. The method according to claim 20, in which the step of placing matrices permutations in predetermined blocks among the blocks, classification cat is qualified as the first test part, and placing the unit matrix in the full lower triangular form in predetermined blocks among the blocks classified as the second test part, contains the following steps:

classify the blocks constituting the first test part, into blocks corresponding to the first partial block, and blocks corresponding to a second partial block, and classify the blocks constituting the second test part, into blocks corresponding to the third partial block, and blocks corresponding to the fourth partial block; place matrix permutations in predetermined blocks among the blocks classified as the first partial block and a second partial block; place identity matrix in the full lower triangular form in predetermined blocks among the blocks classified as the third partial block; and placing the matrix of permutations in a predetermined block among blocks classified as the fourth partial block.

23. The method according to item 22, in which the blocks where the identity matrix is placed among the blocks classified as the third partial block, blocks are the components of the diagonal among the blocks classified as the third partial block.

24. The method according to item 22, further containing the step where the host matrix permutations in the lower blocks, parallel blocks, the de identity matrix placed among the blocks, classified as the third partial block.

25. The method according to item 22, in which the block where the matrix permutations are placed among the blocks classified as the fourth partial block is the last block among the blocks classified as the fourth partial block.

26. The method according to item 22, wherein the matrix permutations are determined so that the matrix defined by adding the matrices permutations placed in the second partial unit, and the matrix product of matrices permutations placed in the fourth partial block, inverse matrix, matrices, permutations, placed in the third partial block, and matrices permutations placed in the first partial unit are unit matrices.

27. Device for encoding a block of code low-density parity (nppc), containing the first matrix multiplier for multiplying a received data word to the first partial matrix matrix parity, consisting of an information part corresponding to an information word, and the first test part and the second test parts, each of which corresponds to the parity;

the second matrix multiplier for multiplying a data word to the second partial matrix matrix parity;

third matricin the second multiplier for multiplying the signal, issued from the first matrix multiplier, for matrix multiplication of a third partial matrix and the inverse matrix from the fourth partial matrix of the matrix parity;

a first adder for adding the signal issued from the second matrix multiplier, and the signal issued from the third matrix multiplier;

the fourth matrix multiplier for multiplying a signal issued from the first adder, the fifth partial matrix of the matrix parity;

a second adder for adding the signal issued from the first matrix multiplier, and the signal issued from the fourth matrix multiplier;

the fifth matrix multiplier for multiplying a signal issued from the second adder, the inverse matrix from the fourth partial matrix of the matrix parity; and

switches for multiplexing a data word, the output signal of the first adder as a first test part and the output signal of the fifth multiplier as a second test parts according to the format code block NPC.

28. The device according to item 27, in which the first partial matrix and the second partial matrix are partial matrices corresponding to the information part, and matrices permutations are placed so that the minimum cycle length is maximized and the weight values are irregular on the graph of the coefficients of the block of code NPC.

29. The device according to item 27, in which the fifth partial matrix and the sixth partial matrix are partial matrices corresponding to the first test part, the third partial matrix and the fourth partial matrix are partial matrices corresponding to the second test part; a fifth partial matrix and the sixth partial matrix are partial matrices, where the matrices permutations are placed in predetermined positions, and the fourth partial matrix is a partial matrix, where matrix permutations are in full lower triangular form.

30. The device according to clause 29, in which the matrix of permutations in full lower triangular form in predetermined blocks among the blocks classified as the second test part are unit matrices.

31. A method of encoding a block of code low-density parity (nppc), containing the following steps:

generate the first signal by multiplying the information word by a first partial matrix previously generated matrix parity, consisting of an information part corresponding to an information word, and the first test part and the second test parts, each of which corresponds to the parity;

generate a second signal by multiplying the information shall include words in the second partial matrix matrix parity;

generate a third signal by multiplying the first signal by a matrix product of a third partial matrix and the inverse matrix from the fourth partial matrix of the matrix parity;

generate a fourth signal by adding the second signal and the third signal;

generate a fifth signal by multiplying the fourth signal, the fifth partial matrix of the matrix parity;

generate a sixth signal by adding the first signal and the fifth signal;

generate a seventh signal by multiplying the sixth signal by the inverse matrix from the fourth partial matrix of the matrix parity; and

multiplexers information word, the fourth signal as a first test part and the seventh signal as a second test parts according to the format code block NPC.

32. The method according to p, in which the first partial matrix and the second partial matrix are partial matrices corresponding to the information part, and matrices permutations are placed so that the minimum cycle length is maximized and the weight values are irregular on the graph of the coefficients of the block of code NPC.

33. The method according to p, in which the fifth partial matrix and the sixth partial matrix are partial matrices corresponding to the first test part, the third partial matrix and the fourth partial matrix are partial matrices corresponding to the second test part; a fifth partial matrix and the sixth partial matrix are partial matrices, where the matrices permutations are placed in predetermined positions, and the fourth partial matrix is a partial matrix, where matrix permutations are in full lower triangular form.

34. The method according to p, in which the matrix of permutations in full lower triangular form in predetermined blocks among the blocks classified as the second test part are unit matrices.

35. The method of generating a check matrix for parity, and this matrix parity is placed in a matrix of rows and columns of a set of partial information blocks and many test partial blocks, the matrix parity is divided into an information part, consisting of matrices of partial information blocks, and a test section consisting of matrices test partial blocks, with each partial information block consists of a matrix representing the set of information bits, each of the partial test blocks consists of a matrix representing multiple bits of parity, each of the partial information b the shackles and testing partial blocks exist in multiple rows in the matrix of parity, divided into the first data matrix, the first check matrix and the second check matrix, each of the partial information blocks and test partial blocks exist in many other lines except for the number of rows divided by the second information matrix, the third test matrix and the fourth check matrix; and the first and second information matrix, the first and third test matrix, and the second and fourth check matrix is placed in the same columns, respectively, the method contains the following steps:

summarize the third test matrix and the product of the fourth test matrix, the inverse matrix of the second check matrix and the first check matrix so that the sum is the unit matrix;

determine the transposed vector of the first test vector corresponding to the first check matrix and the third test matrix, so that the transposed vector equal to the product of the sum of the second information matrix and the works of the fourth test matrix, the inverse matrix of the second check matrix and the first matrix on the information vector corresponding to the first data matrix and the second information matrix; and

determine transponieren the config vector of the second test vector, the corresponding second check matrix and the fourth check matrix, so that the transposed vector is equal to the product of the inverse matrix of the second check matrix by the sum of the first data matrix and a transposed vector information vector and the works of the first check matrix and the transposed vector of the first test vector.

36. The method according to p, in which the second check matrix is full lower triangular matrix.

37. The method according to p, in which the first information matrix and the second information matrix have irregular weights.

38. Method of producing a matrix of the parity block code low-density parity (nppc), and the matrix parity is placed in a matrix of rows and columns of a set of partial blocks, and matrices permutations generated by shifting an identity matrix of size Ns×Ns on pre-determined exponent according to each of the partial blocks are placed in each of the partial blocks, the method includes the following steps:

define block loop block code NPC as the first value; and

determine a second value such that the second value is the result of multiplying this second value is Oia value determined by subtracting the sum of the exponents of the permutation matrices with odd exponent among matrices permutations placed in each of the partial blocks of the sum of exponents of permutations with an even exponent among matrices permutations placed in each of the partial blocks, and performs a control operation so that each of the partial blocks has a cycle corresponding to the product of the first value and the second value.

39. The method according to § 38, in which the exponent is greater than or equal to 1 and less than or equal to the first value.

__
Method for transferring traffic indication message in broadband wireless access communication system // 2313913
Method for packet transmission of messages in communication networks with multidimensional routing // 2313187
Fault-tolerant device // 2297036
Fault-tolerant memorizing device // 2297035
Fault-tolerant information storage device // 2297034
Self-correcting device // 2297033
Self-correcting memorizing device // 2297032__FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

Fault-tolerant device // 2297031FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

Self-correcting information storage device // 2297030FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

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2 cl, 2 dwg, 5 tbl

FIELD: computer engineering, possible use in modular neuro-computer systems.

SUBSTANCE: in accordance to invention, neuron network contains input layer, neuron nets of finite ring for determining errors syndrome, memory block for storing constants, neuron nets for computing correct result and OR element for determining whether an error is present.

EFFECT: increased error correction speed, decreased amount of equipment, expanded functional capabilities.

1 dwg, 3 tbl

FIELD: computer engineering, in particular, modular neuro-computer means, possible use for finding and correcting errors in modular codes of polynomial residual class system.

SUBSTANCE: in accordance to invention, polynomial residual class system is used, in which as system base minimal polynomials p_{i}(z), i=1,2,...,7, are used, determined in extended Galois fields GF(2^{5}) and neuron network technologies, and also modified zeroing constants determined in current polynomial residual class system are used in parallel.

EFFECT: increased speed of detection and correction of errors in modular codes of polynomial residual class system.

2 dwg, 7 tbl

FIELD: computer engineering, possible use in combination devices, and also devices for storing and transferring information.

SUBSTANCE: device contains original circuit, four groups of AND elements, group of OR elements, encoding device, folding circuit, register, error syndrome circuit, checks circuit, three decoders, corrector.

EFFECT: decreased number of controlling discharges.

1 dwg, 1 app

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, inversion block, decoder, even parity check circuit, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

SUBSTANCE: device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, inversion block, decoder, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

SUBSTANCE: device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, even parity check circuit, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

SUBSTANCE: device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app