Semiconductor heterostructure of field-effect transistor

FIELD: heterostructures of semiconductor devices, primarily those of field-effect transistors.

SUBSTANCE: proposed semiconductor heterostructure of field-effect transistor has AlN single-crystalline substrate, GaN template layer, GaN channel layer, and AlxGa1-xN layer; disposed one on top of other between template and channel layers are intermediate AlyGa1-yN layer and AlzGa1-zN buffer layer, respectively; value of y at template layer boundary is 1 and at buffer layer boundary it equals buffer layer z value; in this case 0.3 ≤ x ≤0.5 and 0.1 ≤ z ≤0.5. Buffer layer in semiconductor heterostructure at channel layer boundary can be doped with Si through depth of 50 to 150 Å.

EFFECT: enhanced conductivity of heterostructure channel layer and, hence, enhanced working currents and power of field-effect transistors.

2 cl, 1 dwg

 

The invention relates to a heterostructure semiconductor devices, mainly field-effect transistors.

The creation of microelectronic and optoelectronic devices based on semiconductor compounds of group a3nitrogen (nitrides And3) is very important due to the significant expansion of functionality of these devices. In particular, there was a possibility of manufacturing of microwave field-effect transistors, the power of which is several times larger than the capacity of such transistors is made on the basis of traditional materials (arsenides And3). Simultaneously, the transistors on the basis of nitrides possess unique thermal resistance and can operate continuously at temperatures of 300-500°that was absolutely not available on traditional instruments.

However, a significant challenge in the industrial implementation of such a technical solution is a tendency nitride transistors to degradation, i.e. to the rapid change (deterioration) characteristics of the device over time. This degradation is observed during operation of the device and, moreover, recorded deterioration in characteristics of the transistor semiconductor structures in the absence of electric current. It is shown that the mobility and the concentration of electrons in the nitride heterostructure arbitrarily change over time, and is a few months these changes reach tens of percent (S.Elhamri et al. Study of deleterious aging effects in GaN/AlGaN II. Journal of Applied Physics, vol.93, 2, pp.1079-1082, 15 January 2003).

In terms of the relevant work, i.e. current flows under the action of the applied voltage, the nitride transistors change their characteristics over several hours, which is unacceptable for real world applications.

Known semiconductor heterostructures on sapphire substrate, in particular, see J.P.Ibbetson. "Polarization effects, surface states and the source of electrous in AlGaN/GaN heterostructure field-effect transistors," Applied Physics Letters, vol.77, No.2, p.250, 2000, USA.

On a sapphire substrate placed nucleation the A1N layer, then a buffer layer of GaN and AlGaN barrier layer.

This model requires the implementation of a compensation doping of magnesium (or carbon, iron, etc.) buffer layer to reduce leakage current. In addition, in this heterostructure is cracking of the barrier layer even at a relatively low tensile stresses, because the lattice constant of sapphire significantly (17%) differs from the lattice constants of GaN. The presence between the substrate and the GaN layer is very thin nucleating AlN layer practically does not affect the above error.

In addition, all heterostructures on sapphire substrate inherent bad heat sink, which limits the possibility of implementing high power modes RA is the notes of the devices due to the significant thermal degradation of the heterostructure.

Known and other heterostructures on sapphire substrate, in particular heterostructure field-effect transistor, EN 2222845 C1; heterostructure sequentially includes a substrate, an insulating layer made of AlyGa1-yN channel layer and the barrier layer made of AlzGa1-zN channel layer is made of AlxGa1-xN, where 0,12>x>of 0.03, while on the border of the channel and the insulating layers 1≥y≥x+0,1, on the border of the channel and barrier layers 1≥z≥x+0,1, a thickness of the channel layer is in the range from 3 to 20 nm, and x, y, z is the molar fraction of Al in the composition of AlGaN.

This heterostructure inherent disadvantages of semiconductor heterostructures associated with the sapphire substrate, although it provides the best electronic limitation in comparison with the above described equivalent.

Recently appeared a new class of semiconductor heterostructures, including monocrystalline substrate of AlN. The error constants of the crystal lattices of AlN and GaN is about 3%, which eliminates some of the disadvantages described above analogues, to reduce the density of native defects, virtually eliminate cracking of the barrier layer.

In particular, the conventional semiconductor heterostructure field-effect transistor comprising a monocrystalline substrate of AlN, e is facially the template layer AlN, channel layer of GaN and a barrier layer of AlxGa1-xN, see X.Hu atal, transistors Applied Physics Letters, "AlGaN/GaN heterostructure field effect on single-crystal bulk AlN" vol.82, N8, 2003, P.P.1299-1301, American Insitute of Physics, USA. This solution is accepted as the prototype of the present invention.

The disadvantage of the prototype is the following circumstance. When growing a channel layer of GaN directly on the template layer of AlN on the first stage of this process with small thickness of the channel layer have significant compressive stresses channel layer. If you continue increasing the channel layer at a certain critical thickness induces relaxation channel layer with formation of a large number of defects, which is unacceptable. Limiting the thickness of the GaN layer substantially limits the conductivity channel layer and, accordingly, limits the operating currents and power of the device.

The present invention is to increase the conductivity of the channel layer of semiconductor heterostructures and, therefore, increasing operating currents and power field-effect transistors.

According to the invention this problem is solved due to the fact that in the semiconductor heterostructure field-effect transistor comprising a monocrystalline substrate of AlN, the template AlN layer, a channel layer of GaN and a barrier layer of AlxGa1-xN, between the template and ka is the material layers located one above the other, accordingly, the transition layer of AlyGa1-yN buffer layer AlzCa1-zN, the value at the border of the template layer is 1, and at the boundary with the buffer layer is equal to the value of the z buffer layer, while 0,3≤x≤0,5 and 0,1≤z≤0.5; in the semiconductor heterostructure buffer layer at the boundary with the channel layer may be doped with Si to a depth of 50-150 Å.

The applicant has not identified any technical solution that is identical to the declared that allows to make a conclusion about conformity of the invention, the criterion of "novelty".

Thanks to the implementation of the distinguishing features of the invention is the possibility of growing a channel layer of a specified thickness in accordance with the required working currents and the installed capacity of the device; this is due to the fact that provides a high conductivity channel layer of GaN due to prevent reducing the electron mobility of defects in the increase of its thickness above the critical value. Furthermore, the presence of doped Si upper sublayer buffer layer provides an additional increase in the conductivity channel layer by increasing the concentration of electrons in it. These circumstances allow, according to the applicant, to make a conclusion on the compliance of the claimed technical solution the criterion of "inventive, Ural branch of the Yan".

The invention is illustrated in the drawing, which shows a diagram of a semiconductor heterostructure field-effect transistor.

Monocrystalline substrate 1 is made of aluminum nitride and has a thickness of 500 μm, the crystallographic orientation is (0001). On the substrate 1 is the template layer 2 of AlN thickness, in the specific example, 2100 Å. Above is the transition layer 3 AlyGa1-yN thickness 1400 Å. The value varies according to the thickness of the transition layer 1 on the border with the template layer to the z buffer layer 4. The value of z is constant throughout the buffer layer and is 0.1≤z≤0.5 in. The thickness of the buffer layer 4 in this example is 4200 Å, the z value is 0.3. Channel GaN layer has a thickness of 1400 Å. The buffer layer 4 on the border with the channel layer doped with Si to a depth of 100 Å concentration 1×1019cm-3. The barrier layer 6 has a thickness of 250 Å, the value of x is constant throughout the barrier layer and is 0.3≤x≤0.5 in. In a specific example, x=0,4. All semiconductor layers grown by molecular-beam epitaxy (IPE).

Manufactured and tested two versions of the heterostructure. The first option corresponds to claim 1 of the claims, and the second buffer layer at the boundary with the channel layer doped Si. Characteristics of both variants heterostructures shown in the table.

Tests showed a significant improvement of the parameters of heterostructures in comparison with the prototype. The obtained heterostructures are the basis of field-effect transistors high power.

The invention can be implemented both in the factory and in the laboratory using the IPE. This confirms the compliance with the criterion "industrial applicability".

Har-ka hetero-ryThe concentration of electrons deg, cm-2The electron mobility deg, cm2The conductivity of the channel, Ω-1The density of the saturation current of the transistor, A/mm
Option hetero-ry
1. The heterostructure according to claim 1, f-crystals of the invention1,6·101312000,0030720,8÷1,0
2. The heterostructure according to claim 2, f-crystals of the invention2,5·10138500,00340,9÷1,2
3. The placeholder1,0·101311000,001760,4

1. Semiconductor heterostructure field-effect transistor comprising a monocrystalline substrate of AN, the template AlN layer, a channel layer of GaN and a barrier layer of AlxGa1-xN, characterized in that between the template and channel layers located one above the other, respectively, the transition layer of AlyGa1-yN buffer layer AlzGa1-zN, the value at the border of the template layer is 1, and at the boundary with the buffer layer is equal to the value of the z buffer layer, while 0,3≤x≤0,5, a, 0,1≤z≤0.5 in.

2. Semiconductor heterostructure according to claim 1, characterized in that a buffer layer at the boundary with the channel layer doped with Si at a depth of 50-150Å.



 

Same patents:

The invention relates to semiconductor devices and can be used in radio, microwave devices etc

The invention relates to electronic equipment, namely, to field effect transistors on heterostructures with selective doping (FRI GSL)

FIELD: heterostructures of semiconductor devices, primarily those of field-effect transistors.

SUBSTANCE: proposed semiconductor heterostructure of field-effect transistor has AlN single-crystalline substrate, GaN template layer, GaN channel layer, and AlxGa1-xN layer; disposed one on top of other between template and channel layers are intermediate AlyGa1-yN layer and AlzGa1-zN buffer layer, respectively; value of y at template layer boundary is 1 and at buffer layer boundary it equals buffer layer z value; in this case 0.3 ≤ x ≤0.5 and 0.1 ≤ z ≤0.5. Buffer layer in semiconductor heterostructure at channel layer boundary can be doped with Si through depth of 50 to 150 Å.

EFFECT: enhanced conductivity of heterostructure channel layer and, hence, enhanced working currents and power of field-effect transistors.

2 cl, 1 dwg

FIELD: electric engineering.

SUBSTANCE: invention is related to power vertical transistors, comprising MOS-structure, produced with application of double diffusion, having source electrodes (emitter) and gate on one surface of substrate, and drain electrode (collector) on opposite surface of substrate. In transistor with current limitation, comprising substrate having the first and second opposite surfaces, DMOS-transistor installed on the first surface of substrate, alternating areas of N-type and P-type of conductivity arranged on the second surface of substrate, cells of DMOS-transistor on the first surface of substrate have a shape of strips, alternating areas of N-type and P-type of conductivity have a shape of strips on the second surface of substrate, moreover, strips on the second surface of substrate are arranged perpendicularly relative to strips on the first surface of substrate. In process of transistor manufacturing they form areas of N-type and P-type of conductivity on the second surface of substrate with a certain ratio of areas.

EFFECT: manufacturing of transistor of increased resistance to short circuit of load circuit with specified current limitation, increased accuracy of reproducibility of specified current limiter, increased yield of good transistors in percentage ratio, reduced prime cost of transistors manufacturing.

7 cl, 1 dwg

FIELD: electricity.

SUBSTANCE: in vertical field transistor containing the source connection, ohmic contact to the source, source, vertical conducting channels, gate made in the form of metal band, sink, the first and the second dielectric layers located on upper and lower surfaces of metal band and adjacent to side surfaces of vertical conducting channels, and substrate, to lower sink surface there in series applied is layer of ohmic contact, contact layer of ductile metal and damping layer of ductile metal, to lower surface of non-perforated end of metal band there in series applied is the first process layer, the second process layer and support for non-perforated end of metal band; substrate is made from heat-conducting dielectric material; to upper side of substrate there applied are the first and the second contact platforms which are galvanically connected to lower surfaces of damping layer and metal support, and all the transistor elements arranged on dielectric substrate, except the source connection, are enveloped with protective dielectric filling.

EFFECT: invention allows increasing output power of transistor and improving reliability and its life time.

8 cl, 3 dwg

FIELD: electricity.

SUBSTANCE: semiconductor device comprises a thinned substrate of single-crystal silicon of p-type conductivity, oriented according to the plane (111), with a buffer layer from AlN on it, above which there is a heat conducting substrate in the form of a deposited layer of polycrystalline diamond with thickness equal to at least 0.1 mm, on the other side of the substrate there is an epitaxial structure of the semiconducting device on the basis of wide-zone III-nitrides, a source from AlGaN, a gate, a drain from AlGaN, ohmic contacts to the source and drain, a solder in the form of a layer including AuSn, a copper pedestal and a flange. At the same time between the source, gate and drain there is a layer of an insulating polycrystalline diamond.

EFFECT: higher reliability of a semiconducting device and increased service life, makes it possible to simplify manufacturing of a device with high value of heat release from an active part.

3 cl, 7 dwg

FIELD: electricity.

SUBSTANCE: suggested device unites three field effect transistors into a unified vertical structure with channels of n- and p-type conductivity thus forming an electrical junction between them, at that the source of p-type channel is located opposite the source of n-type channel, and the source of p-type channel is located opposite the source of n-type channel. Sources of the channels are interconnected by a conductor and an additional zone with n+-type conductivity where the source of n-type channel is formed, and drains of the channels have separate outputs. The device can be equipped with one gate (three-terminal device - version 1) or two gates (four-terminal device - version 2) located at the other (second) lateral side of the channels. Current in the channels passes in one direction and creates back voltage in the junction thus locking the channels. The device can contain more than one structure, at that gates are common for neighbouring structures.

EFFECT: invention allows reducing dimensions, increasing operational speed, current and output power of the device.

4 cl, 6 dwg

FIELD: electricity.

SUBSTANCE: SHF high-power transistor with multilayer epitaxial structure contains a basic substrate of silicium, a heat-conductive polycrystalline diamond layer, epitaxial structure based on wideband III-nitrides, a buffer layer, a source, a gate, a drain and ohmic contacts. The heat-conductive polycrystalline diamond layer has thickness of 0.1-0.15 mm, and at the epitaxial structure surface between the source, gate and drain there is an auxiliary heat-conductive polycrystalline diamond layer, a barrier layer of hafnium dioxide and an auxiliary barrier layer of aluminium oxide placed in-series. At that the barrier layers of hafnium dioxide and aluminium oxide have total thickness of 1.0-4.0 nm, besides they are placed under the gate, at the epitaxial structure directly, as a layer of solid AlGaN solution with n-conductivity.

EFFECT: increase of heat transfer in the transistor active area and minimisation of current losses.

3 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: SHF high-power transistor contains basic substrate of silicium, a heat-conductive polycrystalline diamond layer, a multilayer epitaxial structure on wideband III-nitrides, a buffer layer, a source, a gate, a drain and ohmic contacts. At that the basic substrate of silicium has thickness less than 10 mcm, the heat-conductive polycrystalline diamond layer has thickness of at least 0.1 mm, and at the surface of the epitaxial structure there is an auxiliary layer of heat-conductive polycrystalline diamond and a barrier layer of hafnium dioxide with thickness of 1.0-4.0 nm, which is placed under the gate, directly at the epitaxial structure made of a layer of solid AlGaN solution with n-conductivity.

EFFECT: increase of SHF-power output, effective removal of heat from the transistor active area and minimisation of current losses.

3 cl, 4 dwg

FIELD: chemistry.

SUBSTANCE: invention relates to a method of producing cyclopropane fullerene derivatives of general formula 2 by heating a non-modified fullerene with tosylhydrazine in the presence of a solvent and a base. The process is carried out with tosylhydrazine of α-keto acetic ester of general formula 1 (R1-C(=N-NH-Ts)COOR (1), where in general formulae 1 and 2, the radical R denotes a linear or branched Cn aliphatic radical, where n ranges from 1 to 50; radical R1 denotes a C6 aromatic radical; Fu is fullerene C60 fullerene C70, or a higher fullerene C>70, or a mixture of fullerenes C60 and C70 (total content of 95.0-99.999% by weight) and higher fullerenes (C>70, content of 0.001-5.0% by weight). The method enables to obtain fullerene derivatives having in their structure an ester group which is directly bonded to the cyclopropane moiety in the fullerene sphere, using readily available α-keto acetic esters.

EFFECT: invention relates to use of cyclopropane fullerene derivatives of general formula 2 as semiconductor materials for electronic semiconductor devices, materials for an organic field-effect transistor and materials for an organic photovoltaic cell.

6 cl, 13 dwg, 3 ex

FIELD: electricity.

SUBSTANCE: invention is related to high-voltage gallium nitride high-electron mobility transistors (GaN HEMT), in particular to GaN HEMT design for high-voltage applications. A high-voltage gallium nitride high-electron mobility transistor is grown at a silicon substrate with coated template structure having thickness of 700-800 nm and consisting of alternate layers of GaN/AlN with thickness of 10 nm at most; between the buffer layer and barrier layers a spacer layer of AlN is introduced with thickness of 1 nm at most; passivation layer is covered by a field plate connected electrically to the gate; distance between the gate and drain and length of the field plate are interrelated quantities, which are selected on the basis of required breakdown voltage.

EFFECT: manufacture of high-voltage gallium nitride high-electron mobility transistor with high performance capabilities at simplification of the process cycle and reduction of material costs for its manufacture.

4 dwg

FIELD: chemistry.

SUBSTANCE: heterostructure modulated-doped field-effect transistor comprises a flange, a pedestal, a heteroepitaxial structure, a buffer layer, a source, a gate, a drain and ohmic contacts. The pedestal has thickness of 30-200 mcm and is made from a heat-conducting layer of CVD polycrystalline diamond with implanted Ni and annealed surface layers on two sides. On top of the pedestal there is a substrate made from monocrystalline silicon with thickness of 10-20 mcm and a buffer layer. On the surface of the heteroepitaxial structure, between the source, the gate and the drain, there are series-arranged additional layers of heat-conducting polycrystalline diamond, a barrier layer of hafnium dioxide and a barrier layer of aluminium oxide. The barrier layers have total thickness of 1.0-4.0 nm. Furthermore, in the gate region, the buffer layers are situated under the gate, directly on the epitaxial structure in the form of a layer of a solid AlGaN solution.

EFFECT: improved heat removal from the pedestal and the active region of the transistor, ensuring minimal current leakage from the gate and achieving the lowest noise factor in the GHz range.

6 cl, 6 dwg

Up!