Device and method for controlling liquid-crystalline color display

FIELD: control of liquid-crystalline color displays.

SUBSTANCE: in accordance to the invention, video signal of same size may be derived with lesser number of clock impulses. Device and method realize a block for controlling clock impulses, which provides clock impulses for operation of each module, interface block which receives 16-bit data for each clock impulse in accordance with control signal of block for controlling clock impulses, a pair of 18-bit RGB buffers, which preserve data transferred through interface block, graphic buffer, which preserves graphic data from a pair of RGB buffers, switch block, which preserves data signals from a pair of RGB buffers, in graphic buffer, and digital-analog converter which transforms digital R/G/B data, preserved in graphic buffer, to analog signal for output.

EFFECT: increased efficiency of data transmission due to reduced processing time of central processor unit.

2 cl, 9 dwg

 

The technical FIELD

The present invention relates to a color liquid crystal display and, more particularly, to device and method of controlling a color liquid crystal display. Although the present invention can be used in various fields, it is intended to reduce the processing time of the CPU with 16-bit interface.

PRIOR art

Liquid crystal display (LCD) is a device that displays a color video signal by receiving three types of signals R (red), G (green) and B (blue). LCD is widely used for commercial portable terminal supports mode 5:6:5 or mode 6:6:6. Mode 5:6:5 LCD represents the R, G and B with 5-th, 6-th and 5-th bits, respectively, to represent approximately 65,000 colors. And mode 6:6:6 LCD is R, G, and B with 6-th, 6-th and 6-bits each to represent about 260,000 colors.

LCD interfaces can be classified into interfaces parallel and serial type. The parallel interface type can be further classified into the interface 8-bit type 16-bit type and 18-bit type. And the interface, widely used for commercial portable terminal is parallel 16-bit interface as CPU, managing portable terminal, ensure which provides a 16-bit interface. In the case of 65000 colors (mode 5:6:5) on the LCD that uses a 16-bit parallel interface requires one clock pulse processor to transmit data in one pixel. Therefore, to represent the full video on the LCD, having a size 'N × M'must 'N × M' clock. In addition, in the case of 260,000 color (mode 6:6:6) on the LCD that uses a 16-bit parallel interface to transmit data in one pixel, you need twice the clock of the processor than the pulses that are needed to represent mode 5:6:5. It is necessary '2 × N × M' clock pulses to represent a single video signal on the LCD having a size of 'N × M', and the data transmission time in two times more than when you need to represent 65000 colors.

Block diagram of LCD controller according to the prior art, which uses a 16-bit parallel interface, presented in figure 1.

LCD controller contains the device 11 of the control frequency, the interface 12 input, RGB buffer 13, a graphics buffer 14 and D/A Converter 15.

Unit 11 controls the serial clock provides the basic clock pulses to work with each of the modules 12, 13, 14 and 15. The interface 12 of the input is to save 16-bit data input in the LCD module in the RGB buffer 13. RGB buffer 13 BP is Menno stores RGB data, configured with six bits each. Graphic buffer 14 stores the data of the full video that should be displayed on the LCD panel 20. The size of the graphics buffer 14 matches 'N × M', and each pixel is 18 bits. D/A Converter 15 converts the digital RGB data to an analog voltage for output. LCD panel 20 is a terminal device video output.

Figure 2 presents a diagram of the format of the output data of the known LCD controller.

16-bit data is entered via the interface 12 (Fig 1) input for each clock pulse controller. Entered data for two clock pulses, configure one pixel video size '2 × N × M'. That is, data entered for '2 × N × M' clock, configure one video.

RGB input in the format shown in figure 2, are stored in the RGB buffer, as shown in figa and 3B, and are stored in the graphics buffer under control of the control unit, a clock pulse.

Figa is an exemplary diagram of a format of 16-bit data to the first frequency in figure 2.

When data that configures one pixel, are entered in the LCD controller (figa), 6-bit data between D5˜D0 in the number of 16-bit data input to the first clock pulse, show brightness R.

Figv is about the chart format 16-bit data to the second clock pulse in figure 2.

The 6-bit data between D15˜D10 (pigv) in the number of 16-bit data input to the second clock pulse, show brightness G, and 6-bit data between D5˜D0 indicate the brightness of B. That is, the remainder of the bit information including full 32-bit data input for two clock pulses, not used (ignored).

All types of pixel information, repeatedly entered according to the above process are stored in the graphics buffer to configure one video. The video signals stored in the graphics buffer 14, is converted into an analog voltage through the D/A Converter 15. Analog voltage drives the LCD panel 20.

However, in the known system, since the data between D15˜D10 16-bit data input to the first clock pulse is not used when receiving data that configures one pixel, deteriorating the transmission efficiency. For this reason, '2 × N × M' heartbeats CPU used when transmitting composite video size 'N × M' on the LCD module, the appropriate time of data transfer.

The INVENTION

Therefore, the present invention relates to a device and method of controlling a color liquid crystal display, which can eliminate the disadvantages of the known devices the way.

The present invention is a device and method of controlling a color liquid crystal display for improving the efficiency of data transfer by changing the interface type input LCD controller.

Another objective of the present invention is to provide a device and method of controlling a color LCD display that provides an introduction video of the same size with a smaller number of clock pulses.

An additional object of the present invention is to provide a device and method of controlling a color liquid crystal display, providing increased practical application CPU.

Additional advantages of the present invention are disclosed in the following description with reference to the accompanying drawings.

The problem is solved by creating a method of controlling a color liquid crystal display according to the present invention includes the steps of receiving 16-bit data signal on each clock pulse and the data of the two pixels for every three clock pulse to represent 260000 colors.

In another aspect of the present invention a method of controlling a color liquid crystal display includes receiving 16-bit data signal on each clock pulse, BP is time saving R, G and B data are presented every six bits in a pair of 18-bit buffers data to be stored in a pair of 18-bit buffers according to the control signal of the control unit clock pulses, save the selected data in the graphics buffer and control color liquid crystal display using the video data stored in the graphics buffer.

According to another aspect of the present invention the control device is a color liquid crystal display includes a control unit, a clock pulse of each module, interface unit, receiving 16-bit data on each clock pulse according to the control signal of the control unit clock pulses, a pair of 18-bit RGB buffer that stores data received through the interface unit, a graphics buffer that retains image data of a pair of RGB buffers, the switch block, storing the data signals from a pair of RGB buffers in the graphics buffer, and digital to analog Converter that converts the digital R/G/B data stored in the graphics buffer in an analog signal to output.

The method of controlling a color liquid crystal display is characterized by the fact that admit a 16-bit data on each clock pulse, configure two pixels for every three clock pulse and transmit data is e video for '(3/2) × N × M' of the clock pulse.

BRIEF DESCRIPTION of DRAWINGS

The invention is further explained in the description of the preferred variant of the embodiment with reference to the accompanying drawings, in which:

figure 1 depicts a block diagram of a known LCD controller;

figure 2 depicts a diagram of the format of the output data of the known LCD controller;

figa depicts a diagram of the format of the 16-bit data to the first clock pulse in figure 2;

figv depicts a diagram of the format of the 16-bit data to the second clock pulse in figure 2;

figure 4 depicts a block diagram of the LCD controller according to the present invention;

figure 5 depicts a diagram of the format of the data input LCD controller according to the present invention;

figa depicts a diagram of the format of the 16-bit data to the first clock pulse of figure 5 according to the invention;

figv depicts a diagram of the format of the 16-bit data to the second clock pulse figure 5 according to the invention;

figs depicts a diagram of the format of the 16-bit data to the third clock pulse of figure 5 according to the invention.

A DETAILED DESCRIPTION of the PREFERRED EMBODIMENT VARIANTS of the INVENTION

4 shows the block diagram of the LCD controller according to the present invention.

LCD controller 100 according to the invention includes a control unit 110 clock and pulses, providing clock pulses for each module, interface unit 120, the receiving 16-bit data on each clock pulse, a couple of 18-bit RGB buffers 131 and 132 that stores data received through the interface unit 120, a graphics buffer 150, which saves image data of a pair of RGB buffers 131 and 132, block 140 of the switch, alternately reading data signals from a pair of RGB buffers 131 and 132 according to the clock pulses generated by the control unit clock pulses, to keep them in the graphics buffer 150, and a digital to analog Converter 160 converts the digital R/G/B data stored in the graphics buffer 150, an analog signal for output.

LCD controller according to the present invention differs from the LCD controller of the prior art in that it includes a pair of RGB buffers and additionally uses a switch block. A pair of RGB buffers 131 and 132 is used for temporarily storing the pixel data. Each of a pair of RGB buffers 131 and 132 includes 18-bit buffer to store the R, G and B data are presented every six bits. Block 140 of the switch plays a role in the selection of data from the R1, G1 and B1 buffers or data from the R2, G2 and B2 buffers according to the control signal of the control unit 110 of the clock pulses.

Figure 5 presents a diagram of the format of the data input LCD controller with the according to the present invention.

16-bit data is entered on each clock pulse through the input interface LCD controller. Data entered for three clock pulses, configure the two pixels. Suppose inputted pixel data with coordinates (Xn, Ym) and the pixel data of coordinates (Xn+1, Ym). The 6-bit data between D13˜D8 16-bit data input to the first clock pulse (figa)shows the brightness of R, configures the pixel with coordinates (Xn, Ym), and 6-bit data between D5˜D0 indicate the brightness of G that configures the pixel with coordinates (Xn, Ym). The 6-bit data between D13˜D8 16-bit data input by the second clock pulse (pigv), show brightness B that configures the pixel with coordinates (Xn, Ym), and 6-bit data between D5˜D0 indicate the brightness of R, configures the pixel with coordinates (Xn+1, Ym). The 6-bit data between D13˜D8 16-bit data entered on the third clock pulse (figs), show brightness G, configures the pixel with coordinates (Xn+1, Ym), and 6-bit data between D5˜D0 indicate the brightness B that configures the pixel with coordinates (Xn+1, Ym).

16-bit input after the third clock pulse, repeat the input formats of the previous three clock pulses. Therefore, it is necessary '(3/2) × N × M' clock pulse to completely transmit the data in one video.

<> The above RGB data is alternately stored in a pair of 18-bit buffers (R1/G1/B1 buffer and R2/G2/B2 buffer), respectively. Data from two RGB buffers 131 and 132 are alternately read by block 140 of the switch to keep them in the graphics buffer 150. In the end, the video data stored in the graphics buffer 150 is converted into a voltage through the D/A Converter 160, through which then is driven by the LCD panel 200. In addition, the block 110 controls the serial clock controls the timing between the device interface 120 of the input unit 140 of the switch.

Therefore, the LCD controller according to the invention allows the transmission of a video signal of the same size with less than in the prior art, the number of clock pulses, which allows to increase speed.

The present invention provides a signal processing for the time saved, which expands the practical application CPU.

For specialists in the art will understand that the present invention can be made of various modifications and changes without evasion essence or scope of the invention.

1. The method of controlling a color liquid crystal display, namely, that

take the 16-bit data signal on each clock pulse,

temporarily retain R, and the data presented every six bits, a pair of 18-bit buffers

choose the data stored in a pair of 18-bit buffers, according to the control signal of the control unit clock pulses,

save the selected data in the graphics buffer and

control the color liquid crystal display using the video data stored in the graphics buffer.

2. The method according to claim 1, characterized in that R, G, and data In the received 16-bit data of the video signal alternately retain paired RGB buffers.

3. The method according to claim 1, characterized in that the data of a pair of RGB buffers alternately read out according to the frequency received from the control unit clock pulses, to save in the graphics buffer.

4. The method according to claim 1, wherein if n is an integer greater than zero, the data stored in the graphics buffer, show the brightness of R and G is odd pixel to (3n+1)-th frequency, the brightness In the odd-numbered pixel and the brightness G even-numbered pixel to (3n+2)-th frequency or brightness G and In the even-numbered pixel to 3n-th frequency.

5. The method according to claim 4, characterized in that the 6-bit data between D13˜D8 16-bit data or the brightness of R In the odd pixel, or brightness G even-numbered pixel, and the 6-bit data between D5˜D0 16-bit data contain or brightness G is odd pixel, or the brightness of R, and In the even-numbered pixels is La.

6. The control device is a color liquid crystal display containing

the control unit clock providing clock pulses for each block device

interface unit, receiving 16-bit data on each clock pulse according to the clock pulses generated by the control unit clock pulses, to keep them in the graphics buffer,

a couple of 18-bit RGB buffers that store the data transferred through the interface block,

the graphics buffer that retains image data of a pair of RGB buffers

the switch block, alternate transmitting data signals stored in a pair of RGB buffers in accordance with the control clock pulses, in the graphics buffer,

digital to analog Converter that converts the digital R/G/B data stored in the graphics buffer into an analog control signal LCD display.

7. The device according to claim 6, characterized in that the interface unit is designed to toggle between save R, G, and data In the received 16-bit data in a pair of RGB buffers.

8. The device according to claim 6, wherein if n is an integer greater than zero, the data stored in the graphics buffer, show the brightness of R and G is odd pixel to (3n+1)-th frequency, the brightness In the odd peak of the El and the brightness G even-numbered pixel to (3n+2)-th frequency or brightness G and In the even-numbered pixel to 3n-th frequency.

9. The device according to claim 8, characterized in that the 6-bit data between D13˜D8 16-bit data or the brightness of R In the odd pixel, or brightness G even-numbered pixel, and the 6-bit data between D5˜D0 16-bit data contain or brightness G is odd pixel, or the brightness of R, and In the even-numbered pixel.



 

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